1 | \documentclass[a4paper,twoside]{article}
|
---|
2 |
|
---|
3 | \setlength{\topmargin}{0mm} %1 inch is always there!
|
---|
4 | \setlength{\oddsidemargin}{0mm} %1 inch is always there!
|
---|
5 | \setlength{\evensidemargin}{0mm} %1 inch is always there!
|
---|
6 |
|
---|
7 | \setlength{\textwidth}{16cm}
|
---|
8 |
|
---|
9 | \setlength{\headheight}{0mm}
|
---|
10 | \setlength{\headsep}{0mm}
|
---|
11 |
|
---|
12 | \usepackage[T1]{fontenc}
|
---|
13 | \usepackage[utf8]{inputenc}
|
---|
14 |
|
---|
15 | \usepackage{graphicx} % for pictures
|
---|
16 | \usepackage{float} % for figures (english)
|
---|
17 | \restylefloat{figure}
|
---|
18 | \restylefloat{table}
|
---|
19 |
|
---|
20 | \title{FAD Data Generation}
|
---|
21 | \author{D. Neise}
|
---|
22 | \date{08.02.2011}
|
---|
23 |
|
---|
24 | \begin{document}
|
---|
25 |
|
---|
26 | \maketitle
|
---|
27 | \tableofcontents
|
---|
28 | \newpage
|
---|
29 |
|
---|
30 |
|
---|
31 | \section{data order in 64bit address space}
|
---|
32 |
|
---|
33 | When data is input into Data-RAM by the DataGenerator, the data is fed in as words of 64bit.
|
---|
34 |
|
---|
35 | Each Event constists of an EventHeader, the so called ChannelData, and a small EventFooter.
|
---|
36 | Figure (\ref{64bitRAM}) shows how the data is stored as 64bit words in the DataRAM.
|
---|
37 | Assume the Event Start-Address beeing {\tt 0x2000} and each package of ChannelData consists 100 samples.
|
---|
38 | \\ \\
|
---|
39 | \emph{Erklaeren, dass auch wenn nur ein channel kleiner ist, die selbe Anzahl Daten versendet wird.}
|
---|
40 |
|
---|
41 |
|
---|
42 | \begin{table}[htbp]
|
---|
43 |
|
---|
44 | \begin{tabular}{||l||l|l|l|l||l||} %6 linkbuendige spalten
|
---|
45 | \hline
|
---|
46 | address & word 3 & word 2 & word 1 & word 0 & mnemonic \\
|
---|
47 | \hline
|
---|
48 | 0x2000 & 0x0000 & Version & 0xLLLL & 0xFB01 & Header \\
|
---|
49 | 0x2001 & 0x0000 & TRG-ID 4,5 & TRG-ID 1,0 & TRG-ID 3,2 & Externl trigger ID \\
|
---|
50 | 0x2002 & 0x0000 & TRG-ID 4,5 & TRG-ID 1,0 & TRG-ID 3,2 & Internal trigger ID (now just a copy\\
|
---|
51 | 0x2003 & 0x0000 & 0x0000 & 0x0000 & 0x0(cid)8(bid) & Board ID \\
|
---|
52 | 0x2004 & Temp 3 & Temp 2 & Temp 1 & Temp 0 & Temperatures \\
|
---|
53 | 0x2005 & DAC 3 & DAC 2 & DAC 1 & DAC 0 & DAC values part 1 \\
|
---|
54 | 0x2006 & DAC 7 & DAC 6 & DAC 5 & DAC 4 & DAC values part 2 \\
|
---|
55 | \hline
|
---|
56 | 0x2007 & 0x0030 & 0x0020 & 0x0010 & 0x0000 & chip-n-channel ID (channel group 0) \\
|
---|
57 | 0x2008 & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 & DRS stop positions \\
|
---|
58 | 0x2009 & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\
|
---|
59 | 0x200A & data adc3 & data adc2 & data adc1 & data adc0 & ADC Data start of ROI \\
|
---|
60 | 0x20.. &&&&& ... \\
|
---|
61 | 0x206D & data adc3 & data adc2 & data adc1 & data adc0 & ADC Data end of ROI \\
|
---|
62 | \hline
|
---|
63 | 0x206E & 0x0031 & 0x0021 & 0x0011 & 0x0001 & chip-n-channel ID (channel group 1) \\
|
---|
64 | 0x206F & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 & DRS stop positions \\
|
---|
65 | 0x2070 & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\
|
---|
66 | 0x2071 & data adc3 & data adc2 & data adc1 & data adc0 & ADC Data start of ROI \\
|
---|
67 | 0x20.. &&&&& ... \\
|
---|
68 | 0x20D4 & data adc3 & data adc2 & data adc1 & data adc0 & ADC Data end of ROI \\
|
---|
69 | \hline
|
---|
70 | 0x20.. &&&&& ... \\
|
---|
71 | \hline
|
---|
72 | 0x233F & 0x0039 & 0x0029 & 0x0019 & 0x0009 & chip-n-channel ID (channel group 9) \\
|
---|
73 | 0x2340 & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 & DRS stop positions \\
|
---|
74 | 0x2341 & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\
|
---|
75 | 0x2342 & data adc3 & data adc2 & data adc1 & data adc0 & ADC Data start of ROI \\
|
---|
76 | 0x23.. &&&&& ... \\
|
---|
77 | 0x23A5 & data adc3 & data adc2 & data adc1 & data adc0 & ADC Data end of ROI \\
|
---|
78 | \hline
|
---|
79 | 0x23A6 & 0x0000 & 0x0000 & 0x04FE & 0x4242 & FOOTER \\
|
---|
80 | \hline
|
---|
81 | \end {tabular}
|
---|
82 |
|
---|
83 | \caption{word order of event in Data RAM. 64bit addressing. As of 08.02.2011}
|
---|
84 | \label{64bitRAM}
|
---|
85 | \end{table}
|
---|
86 |
|
---|
87 |
|
---|
88 | During DRS readout and data digitzation, the Trigger ID is coming in through RS485 interface from FTM board.
|
---|
89 | The Trigger ID reciption takes about $40 {\mu}$s. Therefor the 2 words containing Trigger information in the EventHeader are
|
---|
90 | left empty in the first place. The digitazed analog data is read in as quickly as possible. Only after finishing the Readout,
|
---|
91 | the Trigger ID is filled into the EventHeader.
|
---|
92 | Then the EventFooter is added and the Readout is finished.
|
---|
93 |
|
---|
94 |
|
---|
95 | \end{document}
|
---|