source: firmware/FSC/usb_src/ad7719_adc.c@ 16322

Last change on this file since 16322 was 10109, checked in by lutz, 15 years ago
niculin & dom debugged quite some stuff
File size: 4.6 KB
Line 
1//-----------------------------------------------------------------------------
2
3#include "ad7719_adc.h"
4#include "spi_master.h"
5
6//-----------------------------------------------------------------------------
7
8void ad7719_init(void)
9{
10
11 // ADC communiaction works like this:
12 // a write operation to the COM register takes place - telling the device what up next.
13 // a write or read operation to another register takes place
14 // COM register bits have the following meaning:
15 //
16 // | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
17 // |#WEN |R/#W | zero| zero| A3 | A2 | A1 | A0 |
18 //
19 // #WEN (inversed write enable) must be zero inorder to clock more bits into the SPI interface.
20 // R/#W (read / not write) must be zero if the next operation will be a WRITE. one if the next is READ.
21 // A3-A0 denote the address of the next register.
22
23
24 CLR_BIT(ADC_PRT,ADC_RST); // Reset ADC (active low)
25 SET_BIT(ADC_PRT,ADC_RST); // Stop Reset ADC
26
27
28 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
29 spi_transfer_byte(FILTER_RD); // Next Operation is write to IOCON
30 SET_BIT(PORTD,SPI_AD_CS);
31
32_delay_us(50);
33
34 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
35 spi_transfer_byte(0); // Next Operation is write to IOCON
36 SET_BIT(PORTD,SPI_AD_CS);
37
38_delay_us(50);
39
40 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
41 spi_transfer_byte(IOCON_WR); // Next Operation is write to IOCON
42 SET_BIT(PORTD,SPI_AD_CS);
43
44 _delay_us(50);
45
46 CLR_BIT(PORTD,SPI_AD_CS);
47 spi_transfer_byte(IOCON_INIT_HIGH); // Write to IOCON1
48 SET_BIT(PORTD,SPI_AD_CS);
49_delay_us(50);
50 CLR_BIT(PORTD,SPI_AD_CS);
51 spi_transfer_byte(IOCON_INIT_LOWBYTE); // Write to IOCON2
52 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
53
54_delay_us(50);
55
56 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
57 spi_transfer_byte(FILTER_WR); // Next Operation is write to FILTER Start SPI
58 SET_BIT(PORTD,SPI_AD_CS);
59
60_delay_us(50);
61 CLR_BIT(PORTD,SPI_AD_CS);
62
63 spi_transfer_byte(FILTER_INIT); // Write to FILTER
64 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
65_delay_us(50);
66 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
67 spi_transfer_byte(AD1CON_WR); // Next Operation is write to AD1CON Start SPI
68 SET_BIT(PORTD,SPI_AD_CS);
69
70_delay_us(50);
71
72 CLR_BIT(PORTD,SPI_AD_CS);
73 spi_transfer_byte(AD1CON_INIT); // Write to AD1CON
74 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
75
76_delay_us(50);
77
78 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
79 spi_transfer_byte(AD0CON_WR); // Next Operation is write to AD0CON Start SPI
80 SET_BIT(PORTD,SPI_AD_CS);
81
82_delay_us(50);
83
84 CLR_BIT(PORTD,SPI_AD_CS);
85 spi_transfer_byte(AD0CON_INIT); // Write to AD0CON
86 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
87
88_delay_us(50);
89
90 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
91 spi_transfer_byte(MODE_WR); // Next Operation is write to MODE Start SPI
92 SET_BIT(PORTD,SPI_AD_CS);
93
94_delay_us(50);
95
96 CLR_BIT(PORTD,SPI_AD_CS);
97 spi_transfer_byte(MODE_CONT); // Write to MODE
98 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
99
100_delay_us(50);
101
102 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
103 spi_transfer_byte(FILTER_RD); // Next Operation is write to IOCON
104 SET_BIT(PORTD,SPI_AD_CS);
105
106_delay_us(50);
107
108 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
109 spi_transfer_byte(0); // Next Operation is write to IOCON
110 SET_BIT(PORTD,SPI_AD_CS);
111
112_delay_us(50);
113
114
115}
116
117void startconv(U08 continuous)
118{
119 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
120 spi_transfer_byte(MODE_WR); // Next Operation is write to Mode Register
121 SET_BIT(PORTD,SPI_AD_CS);
122 CLR_BIT(PORTD,SPI_AD_CS);
123 if (continuous) spi_transfer_byte(MODE_SINGLE); // Start new A/D conversion
124 else spi_transfer_byte(MODE_CONT); // Start continous conversion mode
125 SET_BIT(PORTD,SPI_AD_CS);
126}
127
128void stopconv(void)
129{
130 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
131 spi_transfer_byte(MODE_WR); // Next Operation is write to Mode Register
132 SET_BIT(PORTD,SPI_AD_CS);
133 CLR_BIT(PORTD,SPI_AD_CS);
134 spi_transfer_byte(MODE_IDLE);
135 SET_BIT(PORTD,SPI_AD_CS);
136}
137
138
139U32 read_adc(void)
140{
141 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
142 spi_transfer_byte(AD0DAT_RD); // Next Operation is read from Main ADC Data Register
143 SET_BIT(PORTD,SPI_AD_CS);
144 _delay_us(50);
145
146 CLR_BIT(PORTD,SPI_AD_CS);
147 U32 value=0; // actually a 24bit value is returned
148 value |= spi_transfer_byte(0) ;
149 value =value<<8;
150 value |= spi_transfer_byte(0) ;
151 value =value<<8;
152 value |= spi_transfer_byte(0) ;
153 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
154 return value;
155}
156
157
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