| 1 | //-----------------------------------------------------------------------------
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| 2 |
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| 3 | #include "w5100_spi_interface.h"
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| 4 | #include "spi_master.h"
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| 5 | volatile BOOL sock0_connection_established = false;
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| 6 | volatile U08 eth_read_buffer[ETH_READ_BUFFER_SIZE];
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| 7 | volatile U08 eth_write_buffer[ETH_WRITE_BUFFER_SIZE];
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| 8 |
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| 9 | //-----------------------------------------------------------------------------
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| 10 |
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| 11 | void w5100_write( U16 addr, U08 data)
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| 12 | {
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| 13 | spi_write_buffer[0]=0xF0;
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| 14 | spi_write_buffer[1]=(U08)(addr>>8);
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| 15 | spi_write_buffer[2]=(U08)(addr);
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| 16 | spi_write_buffer[3]=data;
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| 17 |
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| 18 | spi_transfer(4, 0);
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| 19 | // spi_read_buffer should contain 0x00 0x01 0x02 and 0x03 ... nice check!
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| 20 | }
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| 21 |
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| 22 | U08 w5100_read( U16 addr)
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| 23 | {
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| 24 | spi_write_buffer[0]=0x0F;
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| 25 | spi_write_buffer[1]=(U08)(addr>>8);
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| 26 | spi_write_buffer[2]=(U08)(addr);
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| 27 | spi_write_buffer[3]=0x00;
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| 28 |
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| 29 | spi_transfer(4, 0);
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| 30 | return spi_read_buffer[3];
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| 31 | // spi_read_buffer should contain 0x00 0x01 0x02 and data ... nice check!
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| 32 | }
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| 33 |
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| 34 | U08 w5100_init (void)
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| 35 | {
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| 36 | U08 sock0_status;
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| 37 |
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| 38 | // set FSCs MAC Address to value defined in w5100_spi_interface.h
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| 39 | w5100_write( CM_SHAR0, FSC_MAC_ADDRESS0 );
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| 40 | w5100_write( CM_SHAR1, FSC_MAC_ADDRESS1 );
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| 41 | w5100_write( CM_SHAR2, FSC_MAC_ADDRESS2 );
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| 42 | w5100_write( CM_SHAR3, FSC_MAC_ADDRESS3 );
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| 43 | w5100_write( CM_SHAR4, FSC_MAC_ADDRESS4 );
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| 44 | w5100_write( CM_SHAR5, FSC_MAC_ADDRESS5 );
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| 45 |
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| 46 | //set IP
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| 47 | w5100_write( CM_SIPR0, FSC_IP_ADDRESS0 );
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| 48 | w5100_write( CM_SIPR1, FSC_IP_ADDRESS1 );
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| 49 | w5100_write( CM_SIPR2, FSC_IP_ADDRESS2 );
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| 50 | w5100_write( CM_SIPR3, FSC_IP_ADDRESS3 );
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| 51 |
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| 52 | // set subnet mask
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| 53 | w5100_write( CM_SUBR0, FSC_SUBNET_MASK0 );
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| 54 | w5100_write( CM_SUBR1, FSC_SUBNET_MASK1 );
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| 55 | w5100_write( CM_SUBR2, FSC_SUBNET_MASK2 );
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| 56 | w5100_write( CM_SUBR3, FSC_SUBNET_MASK3 );
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| 57 |
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| 58 | // set IP of Gateway used by FSC
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| 59 | w5100_write( CM_GAR0, FSC_GATEWAY_ADDRESS0 );
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| 60 | w5100_write( CM_GAR1, FSC_GATEWAY_ADDRESS1 );
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| 61 | w5100_write( CM_GAR2, FSC_GATEWAY_ADDRESS2 );
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| 62 | w5100_write( CM_GAR3, FSC_GATEWAY_ADDRESS3 );
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| 63 |
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| 64 | //set socket read and write fifo sizes
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| 65 | w5100_write( CM_RMSR, 0x0A); // --> 4k for socket 0 and 1
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| 66 | w5100_write( CM_TMSR, 0x0A); // --> 4k for socket 0 and 1
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| 67 |
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| 68 |
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| 69 | w5100_write ( S0_MR, 0x01); // set Socket 0 as TCP
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| 70 | w5100_write ( S0_PORT0, 0x13 ); // Port 5000 -> 0x1388
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| 71 | w5100_write ( S0_PORT1, 0x88 );
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| 72 | w5100_write ( S0_CR, CR_OPEN ); // issue Socket open command
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| 73 | sock0_status = w5100_read(S0_SR); // request socket 0 status
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| 74 | if ( sock0_status != SR_SOCK_INIT)
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| 75 | {
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| 76 | return sock0_status;
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| 77 | }
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| 78 |
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| 79 | w5100_write ( S0_CR, CR_LISTEN ); // issue Socket listen command
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| 80 | sock0_status = w5100_read(S0_SR); // request socket 0 status
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| 81 | if ( sock0_status != SR_SOCK_LISTEN)
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| 82 | {
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| 83 | return sock0_status;
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| 84 | }
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| 85 |
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| 86 | return sock0_status;
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| 87 | }
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| 88 |
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| 89 |
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| 90 | BOOL w5100_is_established()
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| 91 | {
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| 92 | if ( w5100_read(S0_SR) == SR_SOCK_ESTABLISHED )
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| 93 | {
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| 94 | sock0_connection_established = true;
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| 95 | }
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| 96 | else
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| 97 | {
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| 98 | sock0_connection_established = false;
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| 99 | }
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| 100 | return sock0_connection_established;
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| 101 |
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| 102 | }
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| 103 |
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| 104 | U08 w5100_sock_status()
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| 105 | {
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| 106 | return w5100_read(S0_SR);
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| 107 | }
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| 108 |
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| 109 |
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| 110 | // getters of TX and RX registers
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| 111 | // S0_TX_FSR
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| 112 | U16 get_S0_TX_FSR()
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| 113 | {
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| 114 | U16 freesize;
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| 115 | freesize=w5100_read(S0_TX_FSR1);
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| 116 | freesize = freesize << 8;
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| 117 | freesize += w5100_read(S0_TX_FSR0);
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| 118 | return freesize;
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| 119 | }
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| 120 |
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| 121 | // S0_TX_RD
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| 122 | U16 get_S0_TX_RD()
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| 123 | {
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| 124 | U16 readpointer;
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| 125 | readpointer=w5100_read(S0_TX_RD1);
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| 126 | readpointer = readpointer << 8;
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| 127 | readpointer += w5100_read(S0_TX_RD0);
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| 128 | return readpointer;
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| 129 | }
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| 130 |
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| 131 | // S0_TX_WR
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| 132 | U16 get_S0_TX_WR()
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| 133 | {
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| 134 | U16 writepointer;
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| 135 | writepointer=w5100_read(S0_TX_WR1);
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| 136 | writepointer = writepointer << 8;
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| 137 | writepointer += w5100_read(S0_TX_WR0);
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| 138 | return writepointer;
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| 139 | }
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| 140 |
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| 141 | // S0_RX_RSR
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| 142 | U16 get_S0_RX_RSR()
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| 143 | {
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| 144 | U16 received_size;
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| 145 | received_size=w5100_read(S0_RX_RSR1);
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| 146 | received_size = received_size << 8;
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| 147 | received_size += w5100_read(S0_RX_RSR0);
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| 148 | return received_size;
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| 149 | }
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| 150 |
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| 151 | // S0_RX_RD
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| 152 | U16 get_S0_RX_RD()
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| 153 | {
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| 154 | U16 readpointer;
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| 155 | readpointer=w5100_read(S0_RX_RD1);
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| 156 | readpointer = readpointer << 8;
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| 157 | readpointer += w5100_read(S0_RX_RD0);
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| 158 | return readpointer;
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| 159 | }
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| 160 |
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| 161 | // setters for some RX and TX registers
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| 162 | // S0_TX_WR
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| 163 | void set_S0_TX_WR(U16 value)
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| 164 | {
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| 165 | U08 high_byte = (value>>8);
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| 166 | U08 low_byte = (value<<8)>>8;
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| 167 | w5100_write(S0_TX_WR1, high_byte);
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| 168 | w5100_write(S0_TX_WR0, low_byte);
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| 169 | }
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| 170 |
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| 171 | // S0_TX_RD
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| 172 | void set_S0_RX_RD(U16 value)
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| 173 | {
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| 174 | U08 high_byte = (value>>8);
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| 175 | U08 low_byte = (value<<8)>>8;
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| 176 | w5100_write(S0_TX_RD1, high_byte);
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| 177 | w5100_write(S0_TX_RD0, low_byte);
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| 178 | }
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| 179 |
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| 180 | U08 w5100_get_RX(U08 NumBytes, BOOL send_ACK)
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| 181 | {
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| 182 | U16 size = get_S0_RX_RSR();
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| 183 | U16 upper_size, lower_size;
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| 184 | if (NumBytes > ETH_READ_BUFFER_SIZE)
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| 185 | {
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| 186 | NumBytes = ETH_READ_BUFFER_SIZE;
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| 187 | }
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| 188 | if (size == 0)
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| 189 | {
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| 190 | return 0;
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| 191 | }
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| 192 | else if ( size < NumBytes )
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| 193 | {
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| 194 | NumBytes = size;
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| 195 | }
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| 196 |
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| 197 | // now calculate the offset address
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| 198 | // calculated according to W5100 datasheet page: 43
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| 199 | U16 last_RX_read_pointer = get_S0_RX_RD();
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| 200 | U16 offset = last_RX_read_pointer & S0_RX_MASK;
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| 201 | U16 start_address = S0_RX_BASE + offset;
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| 202 |
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| 203 | if ((offset + NumBytes) > (S0_RX_MASK + 1) ) // if data is turned over in RX-mem
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| 204 | {
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| 205 | upper_size = (S0_RX_MASK + 1) - offset;
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| 206 | lower_size = NumBytes - upper_size;
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| 207 | for (U08 i = 0; i < upper_size; ++i)
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| 208 | {
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| 209 | eth_read_buffer[i] = w5100_read(start_address + i);
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| 210 | }
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| 211 | for (U08 i = 0; i < lower_size; ++i)
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| 212 | {
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| 213 | eth_read_buffer[upper_size + i] = w5100_read(S0_RX_BASE + i);
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| 214 | }
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| 215 | }
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| 216 | else // if not data turn over in RX-mem
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| 217 | {
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| 218 | for (U08 i = 0; i < NumBytes; ++i)
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| 219 | {
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| 220 | eth_read_buffer[i] = w5100_read(start_address + i);
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| 221 | }
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| 222 | }
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| 223 |
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| 224 | // inform W5100 about how much data was read out.
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| 225 | set_S0_RX_RD(last_RX_read_pointer + NumBytes);
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| 226 |
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| 227 | // if user wishes, W5100 may inform peer about receiption.
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| 228 | // this should be done quickly, otherwise timeout may occur on
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| 229 | // peer side, and peer retransmitts or so ...
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| 230 | //
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| 231 | // maybe it is necessary to acknowledge receiption very early.
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| 232 | // I think there is an option in Socket mode register for this.
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| 233 | if (send_ACK)
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| 234 | {
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| 235 | w5100_write ( S0_CR, CR_RECV );
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| 236 | }
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| 237 |
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| 238 | return NumBytes;
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| 239 | }
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| 240 |
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| 241 | // returns number of words, transmitted into TX - buffer.
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| 242 | U08 w5100_set_TX(U08 NumBytes)
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| 243 | {
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| 244 | U16 freesize = get_S0_TX_FSR();
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| 245 | if (freesize == 0)
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| 246 | {
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| 247 | return 0;
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| 248 | }
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| 249 | if (freesize < NumBytes)
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| 250 | {
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| 251 | NumBytes = freesize;
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| 252 | }
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| 253 |
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| 254 | U16 last_TX_write_pointer = get_S0_TX_WR();
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| 255 | U16 offset = last_TX_write_pointer & S0_TX_MASK;
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| 256 | U16 start_address = S0_TX_BASE + offset;
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| 257 |
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| 258 |
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| 259 | U16 upper_size, lower_size;
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| 260 | if (NumBytes > ETH_READ_BUFFER_SIZE)
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| 261 | {
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| 262 | NumBytes = ETH_READ_BUFFER_SIZE;
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| 263 | }
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| 264 | if (freesize == 0)
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| 265 | {
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| 266 | return 0;
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| 267 | }
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| 268 | else if ( freesize < NumBytes )
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| 269 | {
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| 270 | NumBytes = freesize;
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| 271 | }
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| 272 |
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| 273 | // now calculate the offset address
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| 274 | // calculated according to W5100 datasheet page: 43
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| 275 |
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| 276 | if ((offset + NumBytes) > (S0_RX_MASK + 1) ) // if data is turned over in RX-mem
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| 277 | {
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| 278 | upper_size = (S0_RX_MASK + 1) - offset;
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| 279 | lower_size = NumBytes - upper_size;
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| 280 | for (U08 i = 0; i < upper_size; ++i)
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| 281 | {
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| 282 | eth_read_buffer[i] = w5100_read(start_address + i);
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| 283 | }
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| 284 | for (U08 i = 0; i < lower_size; ++i)
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| 285 | {
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| 286 | eth_read_buffer[upper_size + i] = w5100_read(S0_RX_BASE + i);
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| 287 | }
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| 288 | }
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| 289 | else // if not data turn over in RX-mem
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| 290 | {
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| 291 | for (U08 i = 0; i < NumBytes; ++i)
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| 292 | {
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| 293 | eth_read_buffer[i] = w5100_read(start_address + i);
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| 294 | }
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| 295 | }
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| 296 |
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| 297 | // inform W5100 about how much data was read out.
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| 298 | set_S0_RX_RD(last_TX_write_pointer + NumBytes);
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| 299 |
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| 300 |
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| 301 | return NumBytes;
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| 302 | } |
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