source: firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd@ 10523

Last change on this file since 10523 was 10260, checked in by vogler, 15 years ago
ftm_definitions clock constants and array for conditioner interface updated
File size: 8.2 KB
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1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Patrick Vogler
4--
5-- Create Date: 14 February 2010
6-- Design Name:
7-- Module Name: FTM Clock conditioner Interface
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Interface to the LMK03000 Clock conditioner
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19--
20-- modifications: February 21 2011 by Patrick Vogler
21-- March 23 2011 by Patrick Vogler
22----------------------------------------------------------------------------------
23
24library IEEE;
25use IEEE.STD_LOGIC_1164.ALL;
26use IEEE.STD_LOGIC_ARITH.ALL;
27use IEEE.STD_LOGIC_UNSIGNED.ALL;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34library ftm_definitions;
35USE ftm_definitions.ftm_array_types.all;
36USE ftm_definitions.ftm_constants.all;
37
38
39
40entity Clock_cond_interface is
41 port(
42
43
44-- Clock
45-------------------------------------------------------------------------------
46 clk : IN STD_LOGIC; -- 50 MHz system clock
47
48
49-- Clock conditioner LMK03000
50-------------------------------------------------------------------------------
51 CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock
52 LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable
53 DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data
54
55 SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization
56 LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect
57
58
59-- Time Marker
60-------------------------------------------------------------------------------
61 TIM_Sel : out STD_LOGIC; -- Time Marker selector
62 -- 1 = time marker from Clock conditioner
63 -- for DRS timing calibration
64 --
65 -- 0 = time marker from FPGA for normal
66 -- operation / physics run
67
68
69
70-- FPGA intern clock conditioner configuration data
71-------------------------------------------------------------------------------
72 cc_R0 : in std_logic_vector (31 downto 0) := (others => '0');
73 cc_R1 : in std_logic_vector (31 downto 0) := (others => '0');
74 cc_R8 : in std_logic_vector (31 downto 0) := (others => '0');
75 cc_R9 : in std_logic_vector (31 downto 0) := (others => '0');
76 cc_R11 : in std_logic_vector (31 downto 0) := (others => '0');
77 cc_R13 : in std_logic_vector (31 downto 0) := (others => '0');
78 cc_R14 : in std_logic_vector (31 downto 0) := (others => '0');
79 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0');
80
81
82
83
84-- FPGA intern control signals
85-------------------------------------------------------------------------------
86 start_config : in STD_LOGIC; -- load new configuration into the clock
87 -- conditioner
88
89 config_started : out STD_LOGIC; -- indicates that the new configuration
90 -- is currently loaded into the clock conditioner
91
92 config_done : out STD_LOGIC; -- indicates that the configuration has
93 -- been loaded and the clock conditioners
94 -- PLL is locked
95
96 timemarker_select: in STD_LOGIC -- selects time marker source
97 --
98 -- 1 = time marker from Clock conditioner
99 -- for DRS timing calibration
100 --
101 -- 0 = time marker from FPGA for normal
102 -- operation / physics run
103
104 );
105end Clock_cond_interface;
106
107
108
109
110architecture Behavioral of Clock_cond_interface is
111
112
113component microwire_interface IS
114 PORT(
115 clk : IN std_logic;
116 clk_uwire : OUT std_logic; --- IN or OUT ?
117 data_uwire : OUT std_logic;
118 le_uwire : OUT std_logic;
119 clk_cond_array : IN clk_cond_array_type;
120 config_start : IN std_logic;
121 config_ready : OUT std_logic;
122 config_started : OUT std_logic
123 );
124end component;
125
126
127
128
129 signal clk_50M_sig : STD_LOGIC; -- system clock
130-- signal start_config_sig : STD_LOGIC;
131
132 signal config_ready_sig : STD_LOGIC;
133 signal clk_uwire_sig : STD_LOGIC;
134
135 signal config_started_sig : STD_LOGIC;
136
137 signal clk_cond_array_sig : clk_cond_array_type;
138
139 signal cc_R0_sig : std_logic_vector (31 downto 0);
140 signal cc_R1_sig : std_logic_vector (31 downto 0);
141
142 signal cc_R2_sig : std_logic_vector (31 downto 0);
143 signal cc_R3_sig : std_logic_vector (31 downto 0);
144 signal cc_R4_sig : std_logic_vector (31 downto 0);
145 signal cc_R5_sig : std_logic_vector (31 downto 0);
146 signal cc_R6_sig : std_logic_vector (31 downto 0);
147 signal cc_R7_sig : std_logic_vector (31 downto 0);
148
149 signal cc_R8_sig : std_logic_vector (31 downto 0);
150 signal cc_R9_sig : std_logic_vector (31 downto 0);
151 signal cc_R11_sig : std_logic_vector (31 downto 0);
152 signal cc_R13_sig : std_logic_vector (31 downto 0);
153 signal cc_R14_sig : std_logic_vector (31 downto 0);
154 signal cc_R15_sig : std_logic_vector (31 downto 0);
155
156
157
158
159begin
160
161 Inst_microwire_interface:microwire_interface
162 port map (
163 clk => clk_50M_sig,
164 clk_uwire => clk_uwire_sig,
165 data_uwire => DATA_Clk_Cond,
166 le_uwire => LE_Clk_Cond,
167 clk_cond_array => clk_cond_array_sig,
168 config_start => start_config,
169
170 -- config_start => start_config_sig,
171 -- config_start <= start_config_sig,
172
173 config_ready => config_ready_sig,
174 config_started => config_started_sig
175 );
176
177
178
179 config_done <= config_ready_sig; -- indicates that the configuration
180 -- has been loaded
181
182
183
184 -- config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration
185 -- has been loaded and
186 -- the PLL is locked again
187
188
189
190 TIM_Sel <= timemarker_select;
191 CLK_Clk_Cond <= clk_uwire_sig;
192
193 clk_50M_sig <= clk;
194 -- start_config_sig <= start_config;
195
196 -- start_config <= start_config_sig;
197
198
199 config_started <= config_started_sig;
200
201 cc_R0_sig <= cc_R0;
202 cc_R1_sig <= cc_R1;
203 cc_R2_sig <= cc_R2_const;
204 cc_R3_sig <= cc_R3_const;
205 cc_R4_sig <= cc_R4_const;
206 cc_R5_sig <= cc_R5_const;
207 cc_R6_sig <= cc_R6_const;
208 cc_R7_sig <= cc_R7_const;
209 cc_R8_sig <= cc_R8;
210 cc_R9_sig <= cc_R9;
211 cc_R11_sig <= cc_R11;
212 cc_R13_sig <= cc_R13;
213 cc_R14_sig <= cc_R14;
214 cc_R15_sig <= cc_R15;
215
216 clk_cond_array_sig(0) <= LMK03000_Reset; -- reset LKM03000 by setting
217 -- bit 31 of register 0
218 clk_cond_array_sig(1) <= cc_R0_sig;
219 clk_cond_array_sig(2) <= cc_R1_sig;
220
221 clk_cond_array_sig(3) <= cc_R2_sig; -- unused channels
222 clk_cond_array_sig(4) <= cc_R3_sig;
223 clk_cond_array_sig(5) <= cc_R4_sig;
224 clk_cond_array_sig(6) <= cc_R5_sig;
225 clk_cond_array_sig(7) <= cc_R6_sig;
226 clk_cond_array_sig(8) <= cc_R7_sig;
227
228 clk_cond_array_sig(9) <= cc_R8_sig;
229 clk_cond_array_sig(10) <= cc_R9_sig;
230 clk_cond_array_sig(11) <= cc_R11_sig;
231 clk_cond_array_sig(12) <= cc_R13_sig;
232 clk_cond_array_sig(13) <= cc_R14_sig;
233 clk_cond_array_sig(14) <= cc_R15_sig;
234
235
236end Behavioral;
237
238
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