Changeset 10260 for firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd

Timestamp:

03/24/11 16:38:45 (14 years ago)

Author:

vogler

Message:

ftm_definitions clock constants and array for conditioner interface updated

File:

• firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd (modified) (3 diffs)

firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd

@@ -153 +153 @@
   signal cc_R14_sig            : std_logic_vector (31 downto 0); 
   signal cc_R15_sig            : std_logic_vector (31 downto 0); 
-  
+
+
+
+
 begin
   
@@ -198 +201 @@
   cc_R0_sig  <= cc_R0;             
   cc_R1_sig  <= cc_R1;
-  
-  cc_R2_sig  <= cc_R2;             
-  cc_R3_sig  <= cc_R3;
-  cc_R4_sig  <= cc_R4;             
-  cc_R5_sig  <= cc_R5;
-  cc_R6_sig  <= cc_R6;             
-  cc_R7_sig  <= cc_R7;  
+  cc_R2_sig  <= cc_R2_const;                 
+  cc_R3_sig  <= cc_R3_const;   
+  cc_R4_sig  <= cc_R4_const;           
+  cc_R5_sig  <= cc_R5_const;    
+  cc_R6_sig  <= cc_R6_const;       
+  cc_R7_sig  <= cc_R7_const;      
   cc_R8_sig  <= cc_R8;
-  
   cc_R9_sig  <= cc_R9;      
   cc_R11_sig <= cc_R11;       
@@ -216 +217 @@
                                                 -- bit 31 of register 0
   clk_cond_array_sig(1) <= cc_R0_sig;
-  clk_cond_array_sig(2) <= cc_R1_sig;  
-  clk_cond_array_sig(3) <= cc_R8_sig; 
-  clk_cond_array_sig(4) <= cc_R9_sig; 
-  clk_cond_array_sig(5) <= cc_R11_sig;
-  clk_cond_array_sig(6) <= cc_R13_sig;
-  clk_cond_array_sig(7) <= cc_R14_sig;
-  clk_cond_array_sig(8) <= cc_R15_sig;
+  clk_cond_array_sig(2) <= cc_R1_sig;
+  
+  clk_cond_array_sig(3) <= cc_R2_sig; -- unused channels
+  clk_cond_array_sig(4) <= cc_R3_sig; 
+  clk_cond_array_sig(5) <= cc_R4_sig; 
+  clk_cond_array_sig(6) <= cc_R5_sig; 
+  clk_cond_array_sig(7) <= cc_R6_sig; 
+  clk_cond_array_sig(8) <= cc_R7_sig;
+  
+  clk_cond_array_sig(9)  <= cc_R8_sig; 
+  clk_cond_array_sig(10) <= cc_R9_sig; 
+  clk_cond_array_sig(11) <= cc_R11_sig;
+  clk_cond_array_sig(12) <= cc_R13_sig;
+  clk_cond_array_sig(13) <= cc_R14_sig;
+  clk_cond_array_sig(14) <= cc_R15_sig;