source: firmware/FTM/FTM_central_control.vhd@ 10426

Last change on this file since 10426 was 10418, checked in by weitzel, 15 years ago
New FTM firmare: dna, fad_broadcast, FTU error messages, rates readout
File size: 10.6 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 15:56:13 02/28/2011
6-- Design Name:
7-- Module Name: FTM_central_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Central FSM for FTM firmware
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTM_central_control is
35 port(
36 clk : IN std_logic;
37 clk_ready : in std_logic;
38 clk_scaler : IN std_logic;
39 new_config : IN std_logic;
40 config_started : OUT std_logic := '0';
41 config_started_ack : IN std_logic;
42 config_start_eth : OUT std_logic := '0';
43 config_started_eth : IN std_logic;
44 config_ready_eth : IN std_logic;
45 config_start_ftu : OUT std_logic := '0';
46 config_started_ftu : IN std_logic ;
47 config_ready_ftu : IN std_logic ;
48 ping_ftu_start : IN std_logic;
49 ping_ftu_started : OUT std_logic := '0';
50 ping_ftu_ready : OUT std_logic := '0';
51 ping_ftu_start_ftu : OUT std_logic := '0';
52 ping_ftu_started_ftu : IN std_logic;
53 ping_ftu_ready_ftu : IN std_logic;
54 rates_ftu : OUT std_logic := '0';
55 rates_started_ftu : IN std_logic;
56 rates_ready_ftu : IN std_logic;
57 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
58 dd_send : OUT std_logic := '0';
59 dd_send_ack : IN std_logic;
60 dd_send_ready : IN std_logic;
61 dd_block_ready_ftu : out std_logic := '0';
62 dd_block_start_ack_ftu : in std_logic;
63 dd_block_start_ftu : out std_logic := '0';
64 config_start_cc : out std_logic := '0';
65 config_started_cc : in std_logic;
66 config_ready_cc : in std_logic;
67 config_trigger : out std_logic := '0';
68 config_trigger_done : in std_logic;
69 dna_start : out std_logic := '0';
70 dna_ready : in std_logic
71 );
72end FTM_central_control;
73
74architecture Behavioral of FTM_central_control is
75
76 signal reset_scaler_sig : std_logic := '0';
77 signal reset_period_sig : std_logic := '0';
78 signal scaler_counts_sig : integer := 0;
79 signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
80 signal period_finished_sig : std_logic := '0';
81 signal wait_cnt_sig : integer range 0 to 10 := 0;
82 signal new_period_sr_sig : std_logic_vector(1 downto 0) := (others => '0');
83 signal new_period_sig : std_logic := '0';
84 signal new_period_ack_sig : std_logic := '0';
85 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111";
86
87 type state_central_proc_type is (CP_INIT, CP_INIT_DNA,
88 CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01,
89 CP_CONFIG_CC, CP_CONFIG_CC_01,
90 CP_CONFIG_FTU, CP_CONFIG_FTU_01,
91 CP_CONFIG_SCALER, CP_CONFIG_SCALER_01,
92 CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01,
93 CP_IDLE, CP_PING, CP_START_RATES, CP_READ_RATES, CP_READ_RATES_01,
94 CP_SEND_START, CP_SEND_END);
95 signal state_central_proc : state_central_proc_type := CP_INIT;
96
97begin
98
99 central_proc : process (clk, prescaling_FTU01)
100 begin
101 if rising_edge (clk) then
102 case state_central_proc is
103
104 when CP_INIT => -- wait for DCMs to lock
105 if (clk_ready = '1') then
106 state_central_proc <= CP_INIT_DNA;
107 end if;
108
109 when CP_INIT_DNA => -- get FPGA DNA
110 if (dna_ready = '1') then
111 state_central_proc <= CP_CONFIG;
112 dna_start <= '0';
113 else
114 dna_start <= '1';
115 state_central_proc <= CP_INIT_DNA;
116 end if;
117
118 when CP_CONFIG_START =>
119 if (config_started_ack = '1') then
120 config_started <= '0';
121 state_central_proc <= CP_CONFIG;
122 end if;
123
124 when CP_CONFIG =>
125 config_start_eth <= '1';
126 if (config_started_eth = '1') then
127 config_start_eth <= '0';
128 state_central_proc <= CP_CONFIG_01;
129 end if;
130
131 when CP_CONFIG_01 =>
132 if (config_ready_eth = '1') then
133 state_central_proc <= CP_CONFIG_CC;
134 --state_central_proc <= CP_CONFIG_SCALER;
135 --state_central_proc <= CP_IDLE;
136 end if;
137
138 when CP_CONFIG_CC =>
139 config_start_cc <= '1';
140 if (config_started_cc = '1') then
141 config_start_cc <= '0';
142 state_central_proc <= CP_CONFIG_CC_01;
143 end if;
144
145 when CP_CONFIG_CC_01 =>
146 if (config_ready_cc = '1') then
147 state_central_proc <= CP_CONFIG_FTU;
148 end if;
149
150 when CP_CONFIG_FTU =>
151 config_start_ftu <= '1';
152 if (config_started_ftu = '1') then
153 config_start_ftu <= '0';
154 state_central_proc <= CP_CONFIG_FTU_01;
155 end if;
156
157 when CP_CONFIG_FTU_01 =>
158 if (config_ready_ftu = '1') then
159 state_central_proc <= CP_CONFIG_SCALER;
160 end if;
161
162 when CP_CONFIG_SCALER =>
163 prescaling_FTU01_sig <= prescaling_FTU01;
164 --reset_period_sig <= '1';
165 state_central_proc <= CP_CONFIG_SCALER_01;
166
167 when CP_CONFIG_SCALER_01 =>
168 --reset_period_sig <= '0';
169 if wait_cnt_sig < 5 then
170 wait_cnt_sig <= wait_cnt_sig + 1;
171 reset_scaler_sig <= '1';
172 state_central_proc <= CP_CONFIG_SCALER_01;
173 else
174 wait_cnt_sig <= 0;
175 reset_scaler_sig <= '0';
176 state_central_proc <= CP_CONFIG_TRIGGER;
177 end if;
178
179 when CP_CONFIG_TRIGGER =>
180 --config trigger_manager block
181 config_trigger <= '1';
182 state_central_proc <= CP_CONFIG_TRIGGER_01;
183
184 when CP_CONFIG_TRIGGER_01 =>
185 config_trigger <= '0';
186 if (config_trigger_done = '1') then
187 state_central_proc <= CP_IDLE;
188 end if;
189
190 when CP_IDLE =>
191 if (new_config = '1') then
192 config_started <= '1';
193 state_central_proc <= CP_CONFIG_START;
194 elsif (ping_ftu_start = '1') then
195 ping_ftu_start_ftu <= '1';
196 if (ping_ftu_started_ftu = '1') then
197 ping_ftu_start_ftu <= '0';
198 ping_ftu_started <= '1';
199 ping_ftu_ready <= '0';
200 state_central_proc <= CP_PING;
201 end if;
202 --elsif (scaler_counts_sig = scaler_period_sig) then
203 elsif (new_period_sig = '1') then
204 new_period_ack_sig <= '1';
205 --rates_ftu <= '1';
206 --state_central_proc <= CP_READ_RATES;
207 state_central_proc <= CP_START_RATES;
208 end if;
209
210 when CP_PING =>
211 if (ping_ftu_ready_ftu = '1') then
212 if (ping_ftu_start = '0') then
213 ping_ftu_started <= '0';
214 ping_ftu_ready <= '1';
215 state_central_proc <= CP_IDLE;
216 end if;
217 end if;
218
219 when CP_START_RATES =>
220 new_period_ack_sig <= '0';
221 dd_block_start_ftu <= '1';
222 dd_block_ready_ftu <= '0';
223 if (dd_block_start_ack_ftu = '1') then
224 dd_block_start_ftu <= '0';
225 rates_ftu <= '1';
226 state_central_proc <= CP_READ_RATES;
227 end if;
228
229 when CP_READ_RATES =>
230 new_period_ack_sig <= '0';
231 if (rates_started_ftu = '1') then
232 rates_ftu <= '0';
233 state_central_proc <= CP_READ_RATES_01;
234 end if;
235
236 when CP_READ_RATES_01 =>
237 if (rates_ready_ftu = '1') then
238 dd_block_ready_ftu <= '1';
239 state_central_proc <= CP_SEND_START;
240 end if;
241
242 when CP_SEND_START =>
243 dd_send <= '1';
244 if (dd_send_ack = '1') then
245 dd_send <= '0';
246 state_central_proc <= CP_SEND_END;
247 end if;
248
249 when CP_SEND_END =>
250 if (dd_send_ready = '1') then
251 state_central_proc <= CP_IDLE;
252 end if;
253
254 end case;
255 end if;
256 end process central_proc;
257
258 scaler_process: process(reset_scaler_sig, clk_scaler)
259 begin
260 if (reset_scaler_sig = '1') then
261 scaler_counts_sig <= 0;
262 period_finished_sig <= '0';
263 elsif rising_edge(clk_scaler) then
264 if (scaler_counts_sig < scaler_period_sig) then
265 scaler_counts_sig <= scaler_counts_sig + 1;
266 period_finished_sig <= '0';
267 else
268 period_finished_sig <= '1';
269 scaler_counts_sig <= 0;
270 end if;
271 end if;
272 end process scaler_process;
273
274-- process(reset_period_sig)
275-- begin
276-- if rising_edge(reset_period_sig) then
277-- if ((conv_integer(unsigned(prescaling_FTU01))) mod 2 = 0) then
278-- scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
279-- else
280-- scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
281-- end if;
282-- end if;
283-- end process;
284
285 process(prescaling_FTU01_sig)
286 begin
287 if ((conv_integer(unsigned(prescaling_FTU01_sig))) mod 2 = 0) then
288 scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01_sig)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
289 else
290 scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01_sig)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
291 end if;
292 end process;
293
294 detect_period_finished: process(clk)
295 begin
296 if rising_edge(clk) then
297 new_period_sr_sig <= new_period_sr_sig(new_period_sr_sig'left - 1 downto 0) & period_finished_sig;
298 if(new_period_ack_sig = '1') then
299 new_period_sig <= '0';
300 else
301 if (new_period_sr_sig(1 downto 0) = "01") then
302 new_period_sig <= '1';
303 end if;
304 end if;
305 end if;
306 end process detect_period_finished;
307
308end Behavioral;
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