source: firmware/FTM/FTM_central_control.vhd@ 10646

Last change on this file since 10646 was 10639, checked in by weitzel, 15 years ago
FTM: keep-alive of Wiznet actiated, clock conditioner interface updated, trigger ID sending updated
File size: 13.9 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 15:56:13 02/28/2011
6-- Design Name:
7-- Module Name: FTM_central_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Central FSM for FTM firmware
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTM_central_control is
35 port(
36 clk : IN std_logic;
37 clk_ready : in std_logic;
38 clk_scaler : IN std_logic;
39 new_config : IN std_logic;
40 config_started : OUT std_logic := '0';
41 config_started_ack : IN std_logic;
42 config_start_eth : OUT std_logic := '0';
43 config_started_eth : IN std_logic;
44 config_ready_eth : IN std_logic;
45 config_start_ftu : OUT std_logic := '0';
46 config_started_ftu : IN std_logic ;
47 config_ready_ftu : IN std_logic ;
48 ping_ftu_start : IN std_logic;
49 ping_ftu_started : OUT std_logic := '0';
50 ping_ftu_ready : OUT std_logic := '0';
51 ping_ftu_start_ftu : OUT std_logic := '0';
52 ping_ftu_started_ftu : IN std_logic;
53 ping_ftu_ready_ftu : IN std_logic;
54 rates_ftu : OUT std_logic := '0';
55 rates_started_ftu : IN std_logic;
56 rates_ready_ftu : IN std_logic;
57 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
58 dd_send : OUT std_logic := '0';
59 dd_send_ack : IN std_logic;
60 dd_send_ready : IN std_logic;
61 dd_block_ready_ftu : out std_logic := '0';
62 dd_block_start_ack_ftu : in std_logic;
63 dd_block_start_ftu : out std_logic := '0';
64 config_start_cc : out std_logic := '0';
65 config_started_cc : in std_logic;
66 config_ready_cc : in std_logic;
67 config_trigger : out std_logic := '0';
68 config_trigger_done : in std_logic;
69 dna_start : out std_logic := '0';
70 dna_ready : in std_logic;
71 crate_reset : IN std_logic;
72 crate_reset_ack : OUT std_logic := '1';
73 crate_reset_param : IN std_logic_vector (15 DOWNTO 0);
74 start_run : IN std_logic;
75 start_run_ack : OUT std_logic := '0';
76 stop_run : IN std_logic;
77 stop_run_ack : OUT std_logic := '0';
78 current_cc_state : OUT std_logic_vector (15 DOWNTO 0) := X"FFFF";
79 start_run_param : IN std_logic_vector (15 DOWNTO 0);
80 start_run_num_events : IN std_logic_vector (31 DOWNTO 0);
81 trigger_start : out std_logic := '0';
82 trigger_stop : out std_logic := '1';
83 enable_ID_sending : out std_logic := '0'
84 );
85end FTM_central_control;
86
87architecture Behavioral of FTM_central_control is
88
89 signal reset_scaler_sig : std_logic := '0';
90 signal reset_period_sig : std_logic := '0';
91 signal scaler_counts_sig : integer := 0;
92 signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
93 signal period_finished_sig : std_logic := '0';
94 signal wait_cnt_sig : integer range 0 to 10 := 0;
95 signal new_period_sr_sig : std_logic_vector(1 downto 0) := (others => '0');
96 signal new_period_sig : std_logic := '0';
97 signal new_period_ack_sig : std_logic := '0';
98 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111";
99
100 type state_central_proc_type is (CP_INIT, CP_INIT_DNA,
101 CP_RUNNING, CP_RUNNING_01, CP_RUNNING_02, CP_CONFIG_ACK,
102 CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01,
103 CP_CONFIG_CC, CP_CONFIG_CC_01,
104 CP_CONFIG_FTU, CP_CONFIG_FTU_01,
105 CP_CONFIG_SCALER, CP_CONFIG_SCALER_01,
106 CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01,
107 CP_IDLE, CP_PING, CP_START_RATES, CP_READ_RATES, CP_READ_RATES_01,
108 CP_SEND_START, CP_SEND_END);
109 signal state_central_proc : state_central_proc_type := CP_INIT;
110
111 signal after_rates_state : state_central_proc_type := CP_IDLE;
112 signal after_ping_state : state_central_proc_type := CP_IDLE;
113
114begin
115
116 central_proc : process (clk, prescaling_FTU01)
117 begin
118 if rising_edge (clk) then
119 case state_central_proc is
120
121 when CP_INIT => -- wait for DCMs to lock
122 if (clk_ready = '1') then
123 state_central_proc <= CP_INIT_DNA;
124 end if;
125
126 when CP_INIT_DNA => -- get FPGA DNA
127 if (dna_ready = '1') then
128 state_central_proc <= CP_CONFIG;
129 dna_start <= '0';
130 else
131 dna_start <= '1';
132 state_central_proc <= CP_INIT_DNA;
133 end if;
134
135 when CP_CONFIG_START =>
136 if (config_started_ack = '1') then
137 config_started <= '0';
138 state_central_proc <= CP_CONFIG;
139 end if;
140
141 when CP_CONFIG =>
142 config_start_eth <= '1';
143 if (config_started_eth = '1') then
144 config_start_eth <= '0';
145 state_central_proc <= CP_CONFIG_01;
146 end if;
147
148 when CP_CONFIG_01 =>
149 if (config_ready_eth = '1') then
150 state_central_proc <= CP_CONFIG_CC;
151 --state_central_proc <= CP_CONFIG_SCALER;
152 --state_central_proc <= CP_IDLE;
153 end if;
154
155 when CP_CONFIG_CC =>
156 config_start_cc <= '1';
157 if (config_started_cc = '1') then
158 config_start_cc <= '0';
159 state_central_proc <= CP_CONFIG_CC_01;
160 end if;
161
162 when CP_CONFIG_CC_01 =>
163 if (config_ready_cc = '1') then
164 state_central_proc <= CP_CONFIG_FTU;
165 end if;
166
167 when CP_CONFIG_FTU =>
168 config_start_ftu <= '1';
169 if (config_started_ftu = '1') then
170 config_start_ftu <= '0';
171 state_central_proc <= CP_CONFIG_FTU_01;
172 end if;
173
174 when CP_CONFIG_FTU_01 =>
175 if (config_ready_ftu = '1') then
176 state_central_proc <= CP_CONFIG_SCALER;
177 end if;
178
179 when CP_CONFIG_SCALER =>
180 prescaling_FTU01_sig <= prescaling_FTU01;
181 --reset_period_sig <= '1';
182 state_central_proc <= CP_CONFIG_SCALER_01;
183
184 when CP_CONFIG_SCALER_01 =>
185 --reset_period_sig <= '0';
186 if wait_cnt_sig < 5 then
187 wait_cnt_sig <= wait_cnt_sig + 1;
188 reset_scaler_sig <= '1';
189 state_central_proc <= CP_CONFIG_SCALER_01;
190 else
191 wait_cnt_sig <= 0;
192 reset_scaler_sig <= '0';
193 state_central_proc <= CP_CONFIG_TRIGGER;
194 end if;
195
196 when CP_CONFIG_TRIGGER =>
197 --config trigger_manager block
198 config_trigger <= '1';
199 state_central_proc <= CP_CONFIG_TRIGGER_01;
200
201 when CP_CONFIG_TRIGGER_01 =>
202 config_trigger <= '0';
203 if (config_trigger_done = '1') then
204 state_central_proc <= CP_IDLE;
205 end if;
206
207 when CP_IDLE =>
208 current_cc_state <= FTM_STATE_IDLE;
209 stop_run_ack <= '1';
210 start_run_ack <= '0';
211 if (new_config = '1') then
212 config_started <= '1';
213 start_run_ack <= '1';
214 state_central_proc <= CP_CONFIG_START;
215 elsif (ping_ftu_start = '1') then
216 ping_ftu_start_ftu <= '1';
217 if (ping_ftu_started_ftu = '1') then
218 ping_ftu_start_ftu <= '0';
219 ping_ftu_started <= '1';
220 ping_ftu_ready <= '0';
221 after_ping_state <= CP_IDLE;
222 state_central_proc <= CP_PING;
223 end if;
224 --elsif (scaler_counts_sig = scaler_period_sig) then
225 elsif (new_period_sig = '1') then
226 new_period_ack_sig <= '1';
227 --rates_ftu <= '1';
228 --state_central_proc <= CP_READ_RATES;
229 after_rates_state <= CP_IDLE;
230 state_central_proc <= CP_START_RATES;
231 elsif (start_run = '1') then
232 start_run_ack <= '1';
233 if (start_run_param = PAR_START_RUN) then
234 state_central_proc <= CP_RUNNING;
235 end if;
236 end if;
237
238 when CP_RUNNING =>
239 current_cc_state <= FTM_STATE_RUN;
240 if (start_run = '0') then
241 start_run_ack <= '0';
242 stop_run_ack <= '0';
243 state_central_proc <= CP_RUNNING_01;
244 end if;
245
246 when CP_RUNNING_01 =>
247 current_cc_state <= FTM_STATE_RUN;
248 start_run_ack <= '1';
249 trigger_start <= '1';
250 trigger_stop <= '0';
251 enable_Id_sending <= '1';
252 if (new_config = '1') then
253 config_started <= '1';
254 state_central_proc <= CP_CONFIG_ACK;
255 elsif (ping_ftu_start = '1') then
256 ping_ftu_start_ftu <= '1';
257 if (ping_ftu_started_ftu = '1') then
258 ping_ftu_start_ftu <= '0';
259 ping_ftu_started <= '1';
260 ping_ftu_ready <= '0';
261 after_ping_state <= CP_RUNNING_01;
262 state_central_proc <= CP_PING;
263 end if;
264 elsif (new_period_sig = '1') then
265 new_period_ack_sig <= '1';
266 --rates_ftu <= '1';
267 --state_central_proc <= CP_READ_RATES;
268 after_rates_state <= CP_RUNNING_01;
269 state_central_proc <= CP_START_RATES;
270 elsif (stop_run = '1') then
271 stop_run_ack <= '1';
272 trigger_start <= '0';
273 trigger_stop <= '1';
274 enable_Id_sending <= '0';
275 state_central_proc <= CP_RUNNING_02;
276 end if;
277
278 when CP_RUNNING_02 =>
279 if (stop_run = '0') then
280 stop_run_ack <= '0';
281 state_central_proc <= CP_IDLE;
282 end if;
283
284 when CP_CONFIG_ACK =>
285 if (config_started_ack = '1') then
286 config_started <= '0';
287 state_central_proc <= CP_RUNNING_01;
288 end if;
289
290 when CP_PING =>
291 if (ping_ftu_ready_ftu = '1') then
292 if (ping_ftu_start = '0') then
293 ping_ftu_started <= '0';
294 ping_ftu_ready <= '1';
295 --state_central_proc <= CP_IDLE;
296 state_central_proc <= after_ping_state;
297 end if;
298 end if;
299
300 when CP_START_RATES =>
301 new_period_ack_sig <= '0';
302 dd_block_start_ftu <= '1';
303 dd_block_ready_ftu <= '0';
304 if (dd_block_start_ack_ftu = '1') then
305 dd_block_start_ftu <= '0';
306 rates_ftu <= '1';
307 state_central_proc <= CP_READ_RATES;
308 end if;
309
310 when CP_READ_RATES =>
311 new_period_ack_sig <= '0';
312 if (rates_started_ftu = '1') then
313 rates_ftu <= '0';
314 state_central_proc <= CP_READ_RATES_01;
315 end if;
316
317 when CP_READ_RATES_01 =>
318 if (rates_ready_ftu = '1') then
319 dd_block_ready_ftu <= '1';
320 if ( (start_run = '1') or (stop_run = '1') ) then
321 state_central_proc <= after_rates_state;
322 else
323 state_central_proc <= CP_SEND_START;
324 end if;
325 end if;
326
327 when CP_SEND_START =>
328 dd_send <= '1';
329 if (dd_send_ack = '1') then
330 dd_send <= '0';
331 state_central_proc <= CP_SEND_END;
332 end if;
333
334 when CP_SEND_END =>
335 if (dd_send_ready = '1') then
336 --state_central_proc <= CP_IDLE;
337 state_central_proc <= after_rates_state;
338 end if;
339
340 end case;
341 end if;
342 end process central_proc;
343
344 scaler_process: process(reset_scaler_sig, clk_scaler)
345 begin
346 if (reset_scaler_sig = '1') then
347 scaler_counts_sig <= 0;
348 period_finished_sig <= '0';
349 elsif rising_edge(clk_scaler) then
350 if (scaler_counts_sig < scaler_period_sig) then
351 scaler_counts_sig <= scaler_counts_sig + 1;
352 period_finished_sig <= '0';
353 else
354 period_finished_sig <= '1';
355 scaler_counts_sig <= 0;
356 end if;
357 end if;
358 end process scaler_process;
359
360-- process(reset_period_sig)
361-- begin
362-- if rising_edge(reset_period_sig) then
363-- if ((conv_integer(unsigned(prescaling_FTU01))) mod 2 = 0) then
364-- scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
365-- else
366-- scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
367-- end if;
368-- end if;
369-- end process;
370
371 process(prescaling_FTU01_sig)
372 begin
373 if ((conv_integer(unsigned(prescaling_FTU01_sig))) mod 2 = 0) then
374 scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01_sig)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
375 else
376 scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01_sig)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
377 end if;
378 end process;
379
380 detect_period_finished: process(clk)
381 begin
382 if rising_edge(clk) then
383 new_period_sr_sig <= new_period_sr_sig(new_period_sr_sig'left - 1 downto 0) & period_finished_sig;
384 if(new_period_ack_sig = '1') then
385 new_period_sig <= '0';
386 else
387 if (new_period_sr_sig(1 downto 0) = "01") then
388 new_period_sig <= '1';
389 end if;
390 end if;
391 end if;
392 end process detect_period_finished;
393
394end Behavioral;
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