source: firmware/FTM/FTM_central_control.vhd@ 10748

Last change on this file since 10748 was 10740, checked in by weitzel, 13 years ago
several bugfixes for FTM firmware
File size: 15.6 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 15:56:13 02/28/2011
6-- Design Name:
7-- Module Name: FTM_central_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Central FSM for FTM firmware
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTM_central_control is
35 port(
36 clk : IN std_logic;
37 clk_ready : in std_logic;
38 clk_scaler : IN std_logic;
39 new_config : IN std_logic;
40 config_started : OUT std_logic := '0';
41 config_started_ack : IN std_logic;
42 config_start_eth : OUT std_logic := '0';
43 config_started_eth : IN std_logic;
44 config_ready_eth : IN std_logic;
45 config_start_ftu : OUT std_logic := '0';
46 config_started_ftu : IN std_logic ;
47 config_ready_ftu : IN std_logic ;
48 ping_ftu_start : IN std_logic;
49 ping_ftu_started : OUT std_logic := '0';
50 ping_ftu_ready : OUT std_logic := '0';
51 ping_ftu_start_ftu : OUT std_logic := '0';
52 ping_ftu_started_ftu : IN std_logic;
53 ping_ftu_ready_ftu : IN std_logic;
54 rates_ftu : OUT std_logic := '0';
55 rates_started_ftu : IN std_logic;
56 rates_ready_ftu : IN std_logic;
57 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
58 dd_send : OUT std_logic := '0';
59 dd_send_ack : IN std_logic;
60 dd_send_ready : IN std_logic;
61 dd_block_ready_ftu : out std_logic := '0';
62 dd_block_start_ack_ftu : in std_logic;
63 dd_block_start_ftu : out std_logic := '0';
64 config_start_cc : out std_logic := '0';
65 config_started_cc : in std_logic;
66 config_ready_cc : in std_logic;
67 config_trigger : out std_logic := '0';
68 config_trigger_done : in std_logic;
69 dna_start : out std_logic := '0';
70 dna_ready : in std_logic;
71 crate_reset : IN std_logic;
72 crate_reset_ack : OUT std_logic := '1';
73 crate_reset_param : IN std_logic_vector (15 DOWNTO 0);
74 start_run : IN std_logic;
75 start_run_ack : OUT std_logic := '0';
76 stop_run : IN std_logic;
77 stop_run_ack : OUT std_logic := '0';
78 current_cc_state : OUT std_logic_vector (15 DOWNTO 0) := X"FFFF";
79 cc_state_test : OUT std_logic_vector ( 7 downto 0) := X"FF";
80 start_run_param : IN std_logic_vector (15 DOWNTO 0);
81 start_run_num_events : IN std_logic_vector (31 DOWNTO 0);
82 trigger_start : out std_logic := '0';
83 trigger_stop : out std_logic := '1';
84 enable_ID_sending : out std_logic := '0'
85 );
86end FTM_central_control;
87
88architecture Behavioral of FTM_central_control is
89
90 signal reset_scaler_sig : std_logic := '0';
91 signal reset_period_sig : std_logic := '0';
92 signal scaler_counts_sig : integer := 0;
93 signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
94 signal period_finished_sig : std_logic := '0';
95 signal wait_cnt_sig : integer range 0 to 10 := 0;
96 signal new_period_sr_sig : std_logic_vector(1 downto 0) := (others => '0');
97 signal new_period_sig : std_logic := '0';
98 signal new_period_ack_sig : std_logic := '0';
99 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111";
100
101 type state_central_proc_type is (CP_INIT, CP_INIT_DNA,
102 CP_RUNNING, CP_RUNNING_01, CP_RUNNING_02, CP_CONFIG_ACK,
103 CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01,
104 CP_CONFIG_CC, CP_CONFIG_CC_01,
105 CP_CONFIG_FTU, CP_CONFIG_FTU_01,
106 CP_CONFIG_SCALER, CP_CONFIG_SCALER_01,
107 CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01,
108 CP_IDLE, CP_PING, CP_START_RATES, CP_READ_RATES, CP_READ_RATES_01,
109 CP_SEND_START, CP_SEND_END);
110 signal state_central_proc : state_central_proc_type := CP_INIT;
111
112 signal after_rates_state : state_central_proc_type := CP_IDLE;
113 signal after_ping_state : state_central_proc_type := CP_IDLE;
114
115begin
116
117 --central_proc : process (clk, prescaling_FTU01)
118 central_proc : process (clk)
119 begin
120 if rising_edge (clk) then
121 case state_central_proc is
122
123 when CP_INIT => -- wait for DCMs to lock
124 current_cc_state <= X"FFFF";
125 --cc_state_test <= X"00";
126 cc_state_test <= X"19";
127 if (clk_ready = '1') then
128 state_central_proc <= CP_INIT_DNA;
129 end if;
130
131 when CP_INIT_DNA => -- get FPGA DNA
132 current_cc_state <= X"FFFF";
133 cc_state_test <= X"01";
134 if (dna_ready = '1') then
135 state_central_proc <= CP_CONFIG;
136 dna_start <= '0';
137 else
138 dna_start <= '1';
139 state_central_proc <= CP_INIT_DNA;
140 end if;
141
142 when CP_CONFIG_START =>
143 current_cc_state <= FTM_STATE_CFG;
144 cc_state_test <= X"02";
145 if (config_started_ack = '1') then
146 config_started <= '0';
147 state_central_proc <= CP_CONFIG;
148 end if;
149
150 when CP_CONFIG =>
151 current_cc_state <= FTM_STATE_CFG;
152 cc_state_test <= X"03";
153 config_start_eth <= '1';
154 if (config_started_eth = '1') then
155 config_start_eth <= '0';
156 state_central_proc <= CP_CONFIG_01;
157 end if;
158
159 when CP_CONFIG_01 =>
160 current_cc_state <= FTM_STATE_CFG;
161 cc_state_test <= X"04";
162 if (config_ready_eth = '1') then
163 state_central_proc <= CP_CONFIG_CC;
164 --state_central_proc <= CP_CONFIG_SCALER;
165 --state_central_proc <= CP_IDLE;
166 end if;
167
168 when CP_CONFIG_CC =>
169 current_cc_state <= FTM_STATE_CFG;
170 cc_state_test <= X"05";
171 config_start_cc <= '1';
172 if (config_started_cc = '1') then
173 config_start_cc <= '0';
174 state_central_proc <= CP_CONFIG_CC_01;
175 end if;
176
177 when CP_CONFIG_CC_01 =>
178 current_cc_state <= FTM_STATE_CFG;
179 cc_state_test <= X"06";
180 if (config_ready_cc = '1') then
181 state_central_proc <= CP_CONFIG_FTU;
182 end if;
183
184 when CP_CONFIG_FTU =>
185 current_cc_state <= FTM_STATE_CFG;
186 cc_state_test <= X"07";
187 config_start_ftu <= '1';
188 if (config_started_ftu = '1') then
189 config_start_ftu <= '0';
190 state_central_proc <= CP_CONFIG_FTU_01;
191 end if;
192
193 when CP_CONFIG_FTU_01 =>
194 current_cc_state <= FTM_STATE_CFG;
195 cc_state_test <= X"08";
196 if (config_ready_ftu = '1') then
197 state_central_proc <= CP_CONFIG_SCALER;
198 end if;
199
200 when CP_CONFIG_SCALER =>
201 current_cc_state <= FTM_STATE_CFG;
202 cc_state_test <= X"09";
203 prescaling_FTU01_sig <= prescaling_FTU01;
204 --reset_period_sig <= '1';
205 state_central_proc <= CP_CONFIG_SCALER_01;
206
207 when CP_CONFIG_SCALER_01 =>
208 current_cc_state <= FTM_STATE_CFG;
209 cc_state_test <= X"0A";
210 --reset_period_sig <= '0';
211 if wait_cnt_sig < 5 then
212 wait_cnt_sig <= wait_cnt_sig + 1;
213 reset_scaler_sig <= '1';
214 state_central_proc <= CP_CONFIG_SCALER_01;
215 else
216 wait_cnt_sig <= 0;
217 reset_scaler_sig <= '0';
218 state_central_proc <= CP_CONFIG_TRIGGER;
219 end if;
220
221 when CP_CONFIG_TRIGGER =>
222 current_cc_state <= FTM_STATE_CFG;
223 cc_state_test <= X"0B";
224 --config trigger_manager block
225 config_trigger <= '1';
226 state_central_proc <= CP_CONFIG_TRIGGER_01;
227
228 when CP_CONFIG_TRIGGER_01 =>
229 current_cc_state <= FTM_STATE_CFG;
230 cc_state_test <= X"0C";
231 config_trigger <= '0';
232 if (config_trigger_done = '1') then
233 state_central_proc <= CP_IDLE;
234 end if;
235
236 when CP_IDLE =>
237 current_cc_state <= FTM_STATE_IDLE;
238 cc_state_test <= X"0D";
239 stop_run_ack <= '1';
240 start_run_ack <= '0';
241 if (new_config = '1') then
242 config_started <= '1';
243 start_run_ack <= '1';
244 state_central_proc <= CP_CONFIG_START;
245 elsif (ping_ftu_start = '1') then
246 ping_ftu_start_ftu <= '1';
247 if (ping_ftu_started_ftu = '1') then
248 ping_ftu_start_ftu <= '0';
249 ping_ftu_started <= '1';
250 ping_ftu_ready <= '0';
251 after_ping_state <= CP_IDLE;
252 state_central_proc <= CP_PING;
253 end if;
254 --elsif (scaler_counts_sig = scaler_period_sig) then
255 elsif (new_period_sig = '1') then
256 new_period_ack_sig <= '1';
257 --rates_ftu <= '1';
258 --state_central_proc <= CP_READ_RATES;
259 after_rates_state <= CP_IDLE;
260 state_central_proc <= CP_START_RATES;
261 elsif (start_run = '1') then
262 start_run_ack <= '1';
263 if (start_run_param = PAR_START_RUN) then
264 state_central_proc <= CP_RUNNING;
265 end if;
266 end if;
267
268 when CP_RUNNING =>
269 current_cc_state <= FTM_STATE_RUN;
270 cc_state_test <= X"0E";
271 if (start_run = '0') then
272 start_run_ack <= '0';
273 stop_run_ack <= '0';
274 state_central_proc <= CP_RUNNING_01;
275 end if;
276
277 when CP_RUNNING_01 =>
278 current_cc_state <= FTM_STATE_RUN;
279 cc_state_test <= X"0F";
280 start_run_ack <= '1';
281 trigger_start <= '1';
282 trigger_stop <= '0';
283 enable_Id_sending <= '1';
284 if (new_config = '1') then
285 config_started <= '1';
286 state_central_proc <= CP_CONFIG_ACK;
287 elsif (ping_ftu_start = '1') then
288 ping_ftu_start_ftu <= '1';
289 if (ping_ftu_started_ftu = '1') then
290 ping_ftu_start_ftu <= '0';
291 ping_ftu_started <= '1';
292 ping_ftu_ready <= '0';
293 after_ping_state <= CP_RUNNING_01;
294 state_central_proc <= CP_PING;
295 end if;
296 elsif (new_period_sig = '1') then
297 new_period_ack_sig <= '1';
298 --rates_ftu <= '1';
299 --state_central_proc <= CP_READ_RATES;
300 after_rates_state <= CP_RUNNING_01;
301 state_central_proc <= CP_START_RATES;
302 elsif (stop_run = '1') then
303 stop_run_ack <= '1';
304 trigger_start <= '0';
305 trigger_stop <= '1';
306 enable_Id_sending <= '0';
307 state_central_proc <= CP_RUNNING_02;
308 end if;
309
310 when CP_RUNNING_02 =>
311 current_cc_state <= FTM_STATE_RUN;
312 cc_state_test <= X"10";
313 if (stop_run = '0') then
314 stop_run_ack <= '0';
315 state_central_proc <= CP_IDLE;
316 end if;
317
318 when CP_CONFIG_ACK =>
319 current_cc_state <= FTM_STATE_CFG;
320 cc_state_test <= X"11";
321 if (config_started_ack = '1') then
322 config_started <= '0';
323 state_central_proc <= CP_RUNNING_01;
324 end if;
325
326 when CP_PING =>
327 cc_state_test <= X"12";
328 if (ping_ftu_ready_ftu = '1') then
329 if (ping_ftu_start = '0') then
330 ping_ftu_started <= '0';
331 ping_ftu_ready <= '1';
332 --state_central_proc <= CP_IDLE;
333 state_central_proc <= after_ping_state;
334 end if;
335 end if;
336
337 when CP_START_RATES =>
338 cc_state_test <= X"13";
339 new_period_ack_sig <= '0';
340 dd_block_start_ftu <= '1';
341 dd_block_ready_ftu <= '0';
342 if (dd_block_start_ack_ftu = '1') then
343 dd_block_start_ftu <= '0';
344 rates_ftu <= '1';
345 state_central_proc <= CP_READ_RATES;
346 end if;
347
348 when CP_READ_RATES =>
349 cc_state_test <= X"14";
350 new_period_ack_sig <= '0';
351 if (rates_started_ftu = '1') then
352 rates_ftu <= '0';
353 state_central_proc <= CP_READ_RATES_01;
354 end if;
355
356 when CP_READ_RATES_01 =>
357 cc_state_test <= X"15";
358 if (rates_ready_ftu = '1') then
359 dd_block_ready_ftu <= '1';
360 if ( (start_run = '1') or (stop_run = '1') ) then
361 state_central_proc <= after_rates_state;
362 else
363 state_central_proc <= CP_SEND_START;
364 end if;
365 end if;
366
367 when CP_SEND_START =>
368 cc_state_test <= X"16";
369 dd_send <= '1';
370 if (dd_send_ack = '1') then
371 dd_send <= '0';
372 state_central_proc <= CP_SEND_END;
373 end if;
374
375 when CP_SEND_END =>
376 cc_state_test <= X"17";
377 if (dd_send_ready = '1') then
378 --state_central_proc <= CP_IDLE;
379 state_central_proc <= after_rates_state;
380 end if;
381
382 when others =>
383 cc_state_test <= X"18";
384
385 end case;
386 end if;
387 end process central_proc;
388
389 scaler_process: process(reset_scaler_sig, clk_scaler)
390 begin
391 if (reset_scaler_sig = '1') then
392 scaler_counts_sig <= 0;
393 period_finished_sig <= '0';
394 elsif rising_edge(clk_scaler) then
395 if (scaler_counts_sig < scaler_period_sig) then
396 scaler_counts_sig <= scaler_counts_sig + 1;
397 period_finished_sig <= '0';
398 else
399 period_finished_sig <= '1';
400 scaler_counts_sig <= 0;
401 end if;
402 end if;
403 end process scaler_process;
404
405-- process(reset_period_sig)
406-- begin
407-- if rising_edge(reset_period_sig) then
408-- if ((conv_integer(unsigned(prescaling_FTU01))) mod 2 = 0) then
409-- scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
410-- else
411-- scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
412-- end if;
413-- end if;
414-- end process;
415
416 process(prescaling_FTU01_sig)
417 begin
418 if ((conv_integer(unsigned(prescaling_FTU01_sig))) mod 2 = 0) then
419 scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01_sig)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
420 else
421 scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01_sig)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
422 end if;
423 end process;
424
425 detect_period_finished: process(clk)
426 begin
427 if rising_edge(clk) then
428 new_period_sr_sig <= new_period_sr_sig(new_period_sr_sig'left - 1 downto 0) & period_finished_sig;
429 if(new_period_ack_sig = '1') then
430 new_period_sig <= '0';
431 else
432 if (new_period_sr_sig(1 downto 0) = "01") then
433 new_period_sig <= '1';
434 end if;
435 end if;
436 end if;
437 end process detect_period_finished;
438
439end Behavioral;
Note: See TracBrowser for help on using the repository browser.