source: firmware/FTM/FTM_central_control.vhd@ 10761

Last change on this file since 10761 was 10760, checked in by weitzel, 14 years ago
FTM: reset of timing counters implemented
File size: 16.1 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 15:56:13 02/28/2011
6-- Design Name:
7-- Module Name: FTM_central_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Central FSM for FTM firmware
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTM_central_control is
35 port(
36 clk : IN std_logic;
37 clk_ready : in std_logic;
38 clk_scaler : IN std_logic;
39 new_config : IN std_logic;
40 config_started : OUT std_logic := '0';
41 config_started_ack : IN std_logic;
42 config_start_eth : OUT std_logic := '0';
43 config_started_eth : IN std_logic;
44 config_ready_eth : IN std_logic;
45 config_start_ftu : OUT std_logic := '0';
46 config_started_ftu : IN std_logic ;
47 config_ready_ftu : IN std_logic ;
48 ping_ftu_start : IN std_logic;
49 ping_ftu_started : OUT std_logic := '0';
50 ping_ftu_ready : OUT std_logic := '0';
51 ping_ftu_start_ftu : OUT std_logic := '0';
52 ping_ftu_started_ftu : IN std_logic;
53 ping_ftu_ready_ftu : IN std_logic;
54 rates_ftu : OUT std_logic := '0';
55 rates_started_ftu : IN std_logic;
56 rates_ready_ftu : IN std_logic;
57 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
58 dd_send : OUT std_logic := '0';
59 dd_send_ack : IN std_logic;
60 dd_send_ready : IN std_logic;
61 dd_block_ready_ftu : out std_logic := '0';
62 dd_block_start_ack_ftu : in std_logic;
63 dd_block_start_ftu : out std_logic := '0';
64 config_start_cc : out std_logic := '0';
65 config_started_cc : in std_logic;
66 config_ready_cc : in std_logic;
67 config_trigger : out std_logic := '0';
68 config_trigger_done : in std_logic;
69 dna_start : out std_logic := '0';
70 dna_ready : in std_logic;
71 crate_reset : IN std_logic;
72 crate_reset_ack : OUT std_logic := '1';
73 crate_reset_param : IN std_logic_vector (15 DOWNTO 0);
74 start_run : IN std_logic;
75 start_run_ack : OUT std_logic := '0';
76 stop_run : IN std_logic;
77 stop_run_ack : OUT std_logic := '0';
78 current_cc_state : OUT std_logic_vector (15 DOWNTO 0) := X"FFFF";
79 cc_state_test : OUT std_logic_vector ( 7 downto 0) := X"FF";
80 start_run_param : IN std_logic_vector (15 DOWNTO 0);
81 start_run_num_events : IN std_logic_vector (31 DOWNTO 0);
82 trigger_start : out std_logic := '0';
83 trigger_stop : out std_logic := '1';
84 enable_ID_sending : out std_logic := '0';
85 reset_timer : out std_logic := '0'
86 );
87end FTM_central_control;
88
89architecture Behavioral of FTM_central_control is
90
91 signal reset_scaler_sig : std_logic := '0';
92 signal reset_period_sig : std_logic := '0';
93 signal scaler_counts_sig : integer := 0;
94 signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
95 signal period_finished_sig : std_logic := '0';
96 signal wait_cnt_sig : integer range 0 to 10 := 0;
97 signal new_period_sr_sig : std_logic_vector(1 downto 0) := (others => '0');
98 signal new_period_sig : std_logic := '0';
99 signal new_period_ack_sig : std_logic := '0';
100 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111";
101
102 type state_central_proc_type is (CP_INIT, CP_INIT_DNA, CP_INIT_TIMER,
103 CP_RUNNING, CP_RUNNING_01, CP_RUNNING_02, CP_CONFIG_ACK,
104 CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01,
105 CP_CONFIG_CC, CP_CONFIG_CC_01,
106 CP_CONFIG_FTU, CP_CONFIG_FTU_01,
107 CP_CONFIG_SCALER, CP_CONFIG_SCALER_01,
108 CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01,
109 CP_IDLE, CP_PING, CP_START_RATES, CP_READ_RATES, CP_READ_RATES_01,
110 CP_SEND_START, CP_SEND_END);
111 signal state_central_proc : state_central_proc_type := CP_INIT;
112
113 signal after_rates_state : state_central_proc_type := CP_IDLE;
114 signal after_ping_state : state_central_proc_type := CP_IDLE;
115
116begin
117
118 --central_proc : process (clk, prescaling_FTU01)
119 central_proc : process (clk)
120 begin
121 if rising_edge (clk) then
122 case state_central_proc is
123
124 when CP_INIT => -- wait for DCMs to lock
125 current_cc_state <= X"FFFF";
126 --cc_state_test <= X"00";
127 cc_state_test <= X"01";
128 if (clk_ready = '1') then
129 state_central_proc <= CP_INIT_DNA;
130 end if;
131
132 when CP_INIT_DNA => -- get FPGA DNA
133 current_cc_state <= X"FFFF";
134 cc_state_test <= X"01";
135 if (dna_ready = '1') then
136 state_central_proc <= CP_INIT_TIMER;
137 dna_start <= '0';
138 reset_timer <= '1'; -- reset timer after power-up
139 else
140 dna_start <= '1';
141 state_central_proc <= CP_INIT_DNA;
142 end if;
143
144 when CP_INIT_TIMER =>
145 current_cc_state <= X"FFFF";
146 cc_state_test <= X"01";
147 reset_timer <= '0'; -- finish reset timer after power-up
148 state_central_proc <= CP_CONFIG;
149
150 when CP_CONFIG_START =>
151 current_cc_state <= FTM_STATE_CFG;
152 cc_state_test <= X"02";
153 if (config_started_ack = '1') then
154 config_started <= '0';
155 state_central_proc <= CP_CONFIG;
156 end if;
157
158 when CP_CONFIG =>
159 current_cc_state <= FTM_STATE_CFG;
160 cc_state_test <= X"03";
161 config_start_eth <= '1';
162 if (config_started_eth = '1') then
163 config_start_eth <= '0';
164 state_central_proc <= CP_CONFIG_01;
165 end if;
166
167 when CP_CONFIG_01 =>
168 current_cc_state <= FTM_STATE_CFG;
169 cc_state_test <= X"04";
170 if (config_ready_eth = '1') then
171 state_central_proc <= CP_CONFIG_CC;
172 --state_central_proc <= CP_CONFIG_SCALER;
173 --state_central_proc <= CP_IDLE;
174 end if;
175
176 when CP_CONFIG_CC =>
177 current_cc_state <= FTM_STATE_CFG;
178 cc_state_test <= X"05";
179 config_start_cc <= '1';
180 if (config_started_cc = '1') then
181 config_start_cc <= '0';
182 state_central_proc <= CP_CONFIG_CC_01;
183 end if;
184
185 when CP_CONFIG_CC_01 =>
186 current_cc_state <= FTM_STATE_CFG;
187 cc_state_test <= X"06";
188 if (config_ready_cc = '1') then
189 state_central_proc <= CP_CONFIG_FTU;
190 end if;
191
192 when CP_CONFIG_FTU =>
193 current_cc_state <= FTM_STATE_CFG;
194 cc_state_test <= X"07";
195 config_start_ftu <= '1';
196 if (config_started_ftu = '1') then
197 config_start_ftu <= '0';
198 state_central_proc <= CP_CONFIG_FTU_01;
199 end if;
200
201 when CP_CONFIG_FTU_01 =>
202 current_cc_state <= FTM_STATE_CFG;
203 cc_state_test <= X"08";
204 if (config_ready_ftu = '1') then
205 state_central_proc <= CP_CONFIG_SCALER;
206 end if;
207
208 when CP_CONFIG_SCALER =>
209 current_cc_state <= FTM_STATE_CFG;
210 cc_state_test <= X"09";
211 prescaling_FTU01_sig <= prescaling_FTU01;
212 --reset_period_sig <= '1';
213 state_central_proc <= CP_CONFIG_SCALER_01;
214
215 when CP_CONFIG_SCALER_01 =>
216 current_cc_state <= FTM_STATE_CFG;
217 cc_state_test <= X"0A";
218 --reset_period_sig <= '0';
219 if wait_cnt_sig < 5 then
220 wait_cnt_sig <= wait_cnt_sig + 1;
221 reset_scaler_sig <= '1';
222 state_central_proc <= CP_CONFIG_SCALER_01;
223 else
224 wait_cnt_sig <= 0;
225 reset_scaler_sig <= '0';
226 state_central_proc <= CP_CONFIG_TRIGGER;
227 end if;
228
229 when CP_CONFIG_TRIGGER =>
230 current_cc_state <= FTM_STATE_CFG;
231 cc_state_test <= X"0B";
232 --config trigger_manager block
233 config_trigger <= '1';
234 state_central_proc <= CP_CONFIG_TRIGGER_01;
235
236 when CP_CONFIG_TRIGGER_01 =>
237 current_cc_state <= FTM_STATE_CFG;
238 cc_state_test <= X"0C";
239 config_trigger <= '0';
240 if (config_trigger_done = '1') then
241 state_central_proc <= CP_IDLE;
242 end if;
243
244 when CP_IDLE =>
245 current_cc_state <= FTM_STATE_IDLE;
246 reset_timer <= '0';
247 cc_state_test <= X"0D";
248 stop_run_ack <= '1';
249 start_run_ack <= '0';
250 if (new_config = '1') then
251 config_started <= '1';
252 start_run_ack <= '1';
253 state_central_proc <= CP_CONFIG_START;
254 elsif (ping_ftu_start = '1') then
255 ping_ftu_start_ftu <= '1';
256 if (ping_ftu_started_ftu = '1') then
257 ping_ftu_start_ftu <= '0';
258 ping_ftu_started <= '1';
259 ping_ftu_ready <= '0';
260 after_ping_state <= CP_IDLE;
261 state_central_proc <= CP_PING;
262 end if;
263 --elsif (scaler_counts_sig = scaler_period_sig) then
264 elsif (new_period_sig = '1') then
265 new_period_ack_sig <= '1';
266 --rates_ftu <= '1';
267 --state_central_proc <= CP_READ_RATES;
268 after_rates_state <= CP_IDLE;
269 state_central_proc <= CP_START_RATES;
270 elsif (start_run = '1') then
271 start_run_ack <= '1';
272 if (start_run_param = PAR_START_RUN) then
273 reset_timer <= '1';
274 state_central_proc <= CP_RUNNING;
275 end if;
276 end if;
277
278 when CP_RUNNING =>
279 reset_timer <= '0';
280 current_cc_state <= FTM_STATE_RUN;
281 cc_state_test <= X"0E";
282 if (start_run = '0') then
283 start_run_ack <= '0';
284 stop_run_ack <= '0';
285 state_central_proc <= CP_RUNNING_01;
286 end if;
287
288 when CP_RUNNING_01 =>
289 current_cc_state <= FTM_STATE_RUN;
290 cc_state_test <= X"0F";
291 start_run_ack <= '1';
292 trigger_start <= '1';
293 trigger_stop <= '0';
294 enable_Id_sending <= '1';
295 if (new_config = '1') then
296 config_started <= '1';
297 state_central_proc <= CP_CONFIG_ACK;
298 elsif (ping_ftu_start = '1') then
299 ping_ftu_start_ftu <= '1';
300 if (ping_ftu_started_ftu = '1') then
301 ping_ftu_start_ftu <= '0';
302 ping_ftu_started <= '1';
303 ping_ftu_ready <= '0';
304 after_ping_state <= CP_RUNNING_01;
305 state_central_proc <= CP_PING;
306 end if;
307 elsif (new_period_sig = '1') then
308 new_period_ack_sig <= '1';
309 --rates_ftu <= '1';
310 --state_central_proc <= CP_READ_RATES;
311 after_rates_state <= CP_RUNNING_01;
312 state_central_proc <= CP_START_RATES;
313 elsif (stop_run = '1') then
314 stop_run_ack <= '1';
315 trigger_start <= '0';
316 trigger_stop <= '1';
317 enable_Id_sending <= '0';
318 state_central_proc <= CP_RUNNING_02;
319 end if;
320
321 when CP_RUNNING_02 =>
322 current_cc_state <= FTM_STATE_RUN;
323 cc_state_test <= X"10";
324 if (stop_run = '0') then
325 stop_run_ack <= '0';
326 reset_timer <= '1';
327 state_central_proc <= CP_IDLE;
328 end if;
329
330 when CP_CONFIG_ACK =>
331 current_cc_state <= FTM_STATE_CFG;
332 cc_state_test <= X"11";
333 if (config_started_ack = '1') then
334 config_started <= '0';
335 state_central_proc <= CP_RUNNING_01;
336 end if;
337
338 when CP_PING =>
339 cc_state_test <= X"12";
340 if (ping_ftu_ready_ftu = '1') then
341 if (ping_ftu_start = '0') then
342 ping_ftu_started <= '0';
343 ping_ftu_ready <= '1';
344 --state_central_proc <= CP_IDLE;
345 state_central_proc <= after_ping_state;
346 end if;
347 end if;
348
349 when CP_START_RATES =>
350 cc_state_test <= X"13";
351 new_period_ack_sig <= '0';
352 dd_block_start_ftu <= '1';
353 dd_block_ready_ftu <= '0';
354 if (dd_block_start_ack_ftu = '1') then
355 dd_block_start_ftu <= '0';
356 rates_ftu <= '1';
357 state_central_proc <= CP_READ_RATES;
358 end if;
359
360 when CP_READ_RATES =>
361 cc_state_test <= X"14";
362 new_period_ack_sig <= '0';
363 if (rates_started_ftu = '1') then
364 rates_ftu <= '0';
365 state_central_proc <= CP_READ_RATES_01;
366 end if;
367
368 when CP_READ_RATES_01 =>
369 cc_state_test <= X"15";
370 if (rates_ready_ftu = '1') then
371 dd_block_ready_ftu <= '1';
372 if ( (start_run = '1') or (stop_run = '1') ) then
373 state_central_proc <= after_rates_state;
374 else
375 state_central_proc <= CP_SEND_START;
376 end if;
377 end if;
378
379 when CP_SEND_START =>
380 cc_state_test <= X"16";
381 dd_send <= '1';
382 if (dd_send_ack = '1') then
383 dd_send <= '0';
384 state_central_proc <= CP_SEND_END;
385 end if;
386
387 when CP_SEND_END =>
388 cc_state_test <= X"17";
389 if (dd_send_ready = '1') then
390 --state_central_proc <= CP_IDLE;
391 state_central_proc <= after_rates_state;
392 end if;
393
394 when others =>
395 cc_state_test <= X"18";
396
397 end case;
398 end if;
399 end process central_proc;
400
401 scaler_process: process(reset_scaler_sig, clk_scaler)
402 begin
403 if (reset_scaler_sig = '1') then
404 scaler_counts_sig <= 0;
405 period_finished_sig <= '0';
406 elsif rising_edge(clk_scaler) then
407 if (scaler_counts_sig < (scaler_period_sig - 1)) then
408 scaler_counts_sig <= scaler_counts_sig + 1;
409 period_finished_sig <= '0';
410 else
411 period_finished_sig <= '1';
412 scaler_counts_sig <= 0;
413 end if;
414 end if;
415 end process scaler_process;
416
417-- process(reset_period_sig)
418-- begin
419-- if rising_edge(reset_period_sig) then
420-- if ((conv_integer(unsigned(prescaling_FTU01))) mod 2 = 0) then
421-- scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
422-- else
423-- scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
424-- end if;
425-- end if;
426-- end process;
427
428 process(prescaling_FTU01_sig)
429 begin
430 if ((conv_integer(unsigned(prescaling_FTU01_sig))) mod 2 = 0) then
431 scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01_sig)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
432 else
433 scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01_sig)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
434 end if;
435 end process;
436
437 detect_period_finished: process(clk)
438 begin
439 if rising_edge(clk) then
440 new_period_sr_sig <= new_period_sr_sig(new_period_sr_sig'left - 1 downto 0) & period_finished_sig;
441 if(new_period_ack_sig = '1') then
442 new_period_sig <= '0';
443 else
444 if (new_period_sr_sig(1 downto 0) = "01") then
445 new_period_sig <= '1';
446 end if;
447 end if;
448 end if;
449 end process detect_period_finished;
450
451end Behavioral;
Note: See TracBrowser for help on using the repository browser.