1 | ----------------------------------------------------------------------------------
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2 | -- Company: ETH Zurich, Institute for Particle Physics
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3 | -- Engineer: P. Vogler, Q. Weitzel
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4 | --
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5 | -- Create Date: 08 December 2010
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6 | -- Design Name:
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7 | -- Module Name: FTM_top - Behavioral
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8 | -- Project Name:
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9 | -- Target Devices:
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10 | -- Tool versions:
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11 | -- Description: Top level entity for FTM firmware
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12 | --
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13 | --
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14 | -- Dependencies:
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15 | --
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16 | -- Revision:
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17 | -- Revision 0.01 - File Created
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18 | -- Additional Comments:
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19 | --
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20 | ----------------------------------------------------------------------------------
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21 |
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22 | library IEEE;
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23 | use IEEE.STD_LOGIC_1164.ALL;
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24 | use IEEE.STD_LOGIC_ARITH.ALL;
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25 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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26 |
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27 | library ftm_definitions;
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28 | USE ftm_definitions.ftm_array_types.all;
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29 | USE ftm_definitions.ftm_constants.all;
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30 |
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31 | ---- Uncomment the following library declaration if instantiating
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32 | ---- any Xilinx primitives in this code.
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33 | library UNISIM;
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34 | use UNISIM.VComponents.all;
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35 |
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36 |
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37 | entity FTM_top is
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38 | port(
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39 |
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40 | -- Clock
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41 | clk : IN STD_LOGIC; -- external clock from oscillator U47
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42 |
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43 | -- connection to the WIZnet W5300 ethernet controller
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44 | -- on IO-Bank 1
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45 | -------------------------------------------------------------------------------
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46 | -- W5300 data bus
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47 | W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
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48 |
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49 | -- W5300 address bus
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50 | W_A : out STD_LOGIC_VECTOR(9 downto 0); -- there is no real net W_A0 because
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51 | -- the W5300 is operated in the
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52 | -- 16-bit mode
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53 | -- -> W_A<0> assigned to unconnected pin
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54 |
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55 | -- W5300 control signals
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56 | -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
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57 | -- W_CS is also routed to testpoint JP7
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58 | W_CS : out STD_LOGIC := '1'; -- W5300 chip select
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59 | W_INT : IN STD_LOGIC; -- interrupt
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60 | W_RD : out STD_LOGIC := '1'; -- read
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61 | W_WR : out STD_LOGIC := '1'; -- write
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62 | W_RES : out STD_LOGIC := '1'; -- reset W5300 chip
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63 |
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64 | -- W5300 buffer ready indicator
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65 | -- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
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66 |
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67 | -- testpoints (T18) associated with the W5300 on IO-bank 1
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68 | -- W_T : inout STD_LOGIC_VECTOR(3 downto 0);
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69 |
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70 |
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71 | -- SPI Interface
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72 | -- connection to the EEPROM U36 (AL25L016M) and
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73 | -- temperature sensors U45, U46, U48 and U49 (all MAX6662)
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74 | -- on IO-Bank 1
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75 | -------------------------------------------------------------------------------
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76 | -- S_CLK : out STD_LOGIC; -- SPI clock
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77 |
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78 | -- EEPROM
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79 | -- MOSI : out STD_LOGIC; -- master out slave in
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80 | -- MISO : in STD_LOGIC; -- master in slave out
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81 | -- EE_CS : out STD_LOGIC; -- EEPROM chip select
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82 |
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83 | -- temperature sensors U45, U46, U48 and U49
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84 | -- SIO : inout STD_LOGIC; -- serial IO
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85 | -- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
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86 |
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87 |
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88 | -- Trigger primitives inputs
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89 | -- on IO-Bank 2
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90 | -------------------------------------------------------------------------------
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91 | -- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
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92 | -- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
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93 | -- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
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94 | -- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
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95 |
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96 |
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97 | -- NIM inputs
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98 | ------------------------------------------------------------------------------
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99 | -- on IO-Bank 3
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100 | -- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
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101 | -- Veto : in STD_LOGIC; -- trigger veto input
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102 | -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
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103 |
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104 | -- on IO-Bank 0
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105 | -- alternative external clock input for FPGA
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106 | -- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
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107 |
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108 |
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109 | -- LEDs on IO-Banks 0 and 3
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110 | -------------------------------------------------------------------------------
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111 | LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
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112 | LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
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113 | LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
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114 |
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115 |
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116 | -- Clock conditioner LMK03000
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117 | -- on IO-Bank 3
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118 | -------------------------------------------------------------------------------
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119 | CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock
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120 | LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable
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121 | DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data
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122 |
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123 | SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization
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124 | LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for
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125 |
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126 |
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127 | -- various RS-485 Interfaces
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128 | -- on IO-Bank 3
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129 | -------------------------------------------------------------------------------
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130 | -- Bus 1: FTU slow control
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131 | Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
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132 | Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
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133 |
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134 | Bus1_RxD_0 : in STD_LOGIC; -- crate 0
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135 | Bus1_TxD_0 : out STD_LOGIC;
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136 |
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137 | Bus1_RxD_1 : in STD_LOGIC; -- crate 1
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138 | Bus1_TxD_1 : out STD_LOGIC;
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139 |
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140 | Bus1_RxD_2 : in STD_LOGIC; -- crate 2
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141 | Bus1_TxD_2 : out STD_LOGIC;
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142 |
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143 | Bus1_RxD_3 : in STD_LOGIC; -- crate 3
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144 | Bus1_TxD_3 : out STD_LOGIC;
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145 |
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146 |
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147 | -- Bus 2: Trigger-ID to FAD boards
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148 | -- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
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149 | -- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
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150 |
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151 | -- Bus2_RxD_0 : in STD_LOGIC; -- crate 0
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152 | -- Bus2_TxD_0 : out STD_LOGIC;
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153 |
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154 | -- Bus2_RxD_1 : in STD_LOGIC; -- crate 1
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155 | -- Bus2_TxD_1 : out STD_LOGIC;
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156 |
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157 | -- Bus2_RxD_2 : in STD_LOGIC; -- crate 2
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158 | -- Bus2_TxD_2 : out STD_LOGIC;
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159 |
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160 | -- Bus2_RxD_3 : in STD_LOGIC; -- crate 3
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161 | -- Bus2_TxD_3 : out STD_LOGIC;
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162 |
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163 |
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164 | -- auxiliary access
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165 | -- Aux_Rx_D : in STD_LOGIC;
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166 | -- Aux_Tx_D : out STD_LOGIC;
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167 | -- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
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168 | -- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
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169 |
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170 |
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171 | -- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
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172 | -- TrID_Rx_D : in STD_LOGIC;
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173 | -- TrID_Tx_D : out STD_LOGIC;
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174 |
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175 |
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176 | -- Crate-Resets
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177 | -- on IO-Bank 3
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178 | -------------------------------------------------------------------------------
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179 | -- Crate_Res0 : out STD_LOGIC;
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180 | -- Crate_Res1 : out STD_LOGIC;
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181 | -- Crate_Res2 : out STD_LOGIC;
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182 | -- Crate_Res3 : out STD_LOGIC;
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183 |
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184 |
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185 | -- Busy signals from the FAD boards
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186 | -- on IO-Bank 3
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187 | -------------------------------------------------------------------------------
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188 | -- Busy0 : in STD_LOGIC;
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189 | -- Busy1 : in STD_LOGIC;
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190 | -- Busy2 : in STD_LOGIC;
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191 | -- Busy3 : in STD_LOGIC;
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192 |
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193 |
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194 | -- NIM outputs
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195 | -- on IO-Bank 0
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196 | -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
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197 | -------------------------------------------------------------------------------
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198 | -- calibration
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199 | -- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
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200 | -- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
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201 | -- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
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202 | -- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
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203 |
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204 | -- auxiliarry / spare NIM outputs
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205 | -- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
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206 | -- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
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207 | -- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
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208 | -- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
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209 |
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210 |
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211 | -- fast control signal outputs
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212 | -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
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213 | -------------------------------------------------------------------------------
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214 | -- RES_p : out STD_LOGIC; -- RES+ Reset
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215 | -- RES_n : out STD_LOGIC; -- RES- IO-Bank 0
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216 |
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217 | -- TRG_p : out STD_LOGIC; -- TRG+ Trigger
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218 | -- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0
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219 |
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220 | -- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
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221 | -- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2
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222 | TIM_Sel : out STD_LOGIC -- Time Marker selector on IO-Bank 2
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223 |
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224 | -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA
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225 |
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226 |
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227 | -- LVDS calibration outputs
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228 | -- on IO-Bank 0
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229 | -------------------------------------------------------------------------------
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230 | -- to connector J13
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231 | -- for light pulsar in the mirror dish
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232 | -- Cal_0_p : out STD_LOGIC;
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233 | -- Cal_0_n : out STD_LOGIC;
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234 | -- Cal_1_p : out STD_LOGIC;
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235 | -- Cal_1_n : out STD_LOGIC;
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236 | -- Cal_2_p : out STD_LOGIC;
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237 | -- Cal_2_n : out STD_LOGIC;
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238 | -- Cal_3_p : out STD_LOGIC;
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239 | -- Cal_3_n : out STD_LOGIC;
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240 |
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241 | -- to connector J12
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242 | -- for light pulsar inside shutter
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243 | -- Cal_4_p : out STD_LOGIC;
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244 | -- Cal_4_n : out STD_LOGIC;
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245 | -- Cal_5_p : out STD_LOGIC;
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246 | -- Cal_5_n : out STD_LOGIC;
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247 | -- Cal_6_p : out STD_LOGIC;
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248 | -- Cal_6_n : out STD_LOGIC;
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249 | -- Cal_7_p : out STD_LOGIC;
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250 | -- Cal_7_n : out STD_LOGIC
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251 |
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252 |
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253 | -- Testpoints
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254 | -------------------------------------------------------------------------------
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255 | -- TP : inout STD_LOGIC_VECTOR(32 downto 0);
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256 | -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
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257 |
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258 | -- Board ID - inputs
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259 | -- local board-ID "solder programmable"
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260 | -- all on 'input only' pins
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261 | -------------------------------------------------------------------------------
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262 | -- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
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263 |
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264 | );
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265 | end FTM_top;
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266 |
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267 | architecture Behavioral of FTM_top is
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268 |
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269 | signal cc_R0_sig : std_logic_vector(31 DOWNTO 0);
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270 | signal cc_R1_sig : std_logic_vector(31 DOWNTO 0);
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271 | signal cc_R11_sig : std_logic_vector(31 DOWNTO 0);
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272 | signal cc_R13_sig : std_logic_vector(31 DOWNTO 0);
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273 | signal cc_R14_sig : std_logic_vector(31 DOWNTO 0);
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274 | signal cc_R15_sig : std_logic_vector(31 DOWNTO 0);
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275 | signal cc_R8_sig : std_logic_vector(31 DOWNTO 0);
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276 | signal cc_R9_sig : std_logic_vector(31 DOWNTO 0);
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277 | signal coin_n_c_sig : std_logic_vector(15 DOWNTO 0);
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278 | signal coin_n_p_sig : std_logic_vector(15 DOWNTO 0);
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279 | signal dead_time_sig : std_logic_vector(15 DOWNTO 0);
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280 | signal ftu_active_cr0_sig : std_logic_vector(15 DOWNTO 0);
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281 | signal ftu_active_cr1_sig : std_logic_vector(15 DOWNTO 0);
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282 | signal ftu_active_cr2_sig : std_logic_vector(15 DOWNTO 0);
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283 | signal ftu_active_cr3_sig : std_logic_vector(15 DOWNTO 0);
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284 | signal general_settings_sig : std_logic_vector(15 DOWNTO 0);
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285 | signal lp1_amplitude_sig : std_logic_vector(15 DOWNTO 0);
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286 | signal lp1_delay_sig : std_logic_vector(15 DOWNTO 0);
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287 | signal lp2_amplitude_sig : std_logic_vector(15 DOWNTO 0);
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288 | signal lp2_delay_sig : std_logic_vector(15 DOWNTO 0);
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289 | signal lp_pt_freq_sig : std_logic_vector(15 DOWNTO 0);
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290 | signal lp_pt_ratio_sig : std_logic_vector(15 DOWNTO 0);
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291 | signal timemarker_delay_sig : std_logic_vector(15 DOWNTO 0);
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292 | signal trigger_delay_sig : std_logic_vector(15 DOWNTO 0);
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293 | signal sd_addr_ftu_sig : std_logic_vector(11 DOWNTO 0);
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294 | signal sd_busy_sig : std_logic;
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295 | signal sd_data_out_ftu_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
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296 | signal sd_read_ftu_sig : std_logic;
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297 | signal sd_ready_sig : std_logic;
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298 | signal sd_started_ftu_sig : std_logic := '0';
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299 | signal new_config_sig : std_logic := '0';
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300 | signal config_started_sig : std_logic := '0';
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301 | signal config_start_eth_sig : std_logic := '0';
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302 | signal config_started_eth_sig : std_logic := '0';
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303 | signal config_ready_eth_sig : std_logic := '0';
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304 | signal config_started_ack_sig : std_logic := '0';
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305 | signal ping_ftu_start_sig : std_logic := '0';
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306 | signal ping_ftu_started_sig : std_logic := '0';
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307 | signal ping_ftu_ready_sig : std_logic := '0';
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308 | signal config_start_ftu_sig : std_logic := '0';
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309 | signal config_started_ftu_sig : std_logic := '0';
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310 | signal config_ready_ftu_sig : std_logic := '0';
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311 | signal rates_ftu_start_sig : std_logic := '0';
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312 | signal rates_ftu_started_sig : std_logic := '0';
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313 | signal rates_ftu_ready_sig : std_logic := '0';
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314 | signal fl_busy_sig : std_logic;
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315 | signal fl_ready_sig : std_logic;
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316 | signal fl_write_sig : std_logic := '0';
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317 | signal fl_started_ftu_sig : std_logic := '0';
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318 | signal fl_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
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319 | signal fl_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
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320 | signal ping_ftu_start_ftu_sig : std_logic := '0';
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321 | signal ping_ftu_started1_sig : std_logic := '0';
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322 | signal ping_ftu_ready1_sig : std_logic := '0';
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323 | signal coin_win_c_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
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324 | signal coin_win_p_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
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325 | --new or changed stuff
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326 | signal dd_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
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327 | signal dd_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
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328 | signal dd_block_start_sig : std_logic := '0';
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329 | signal dd_block_start_ack_ftu_sig : std_logic := '0';
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330 | signal dd_block_ready_sig : std_logic := '0';
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331 | signal dd_busy_sig : std_logic;
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332 | signal dd_write_sig : std_logic := '0';
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333 | signal dd_started_ftu_sig : std_logic := '0';
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334 | signal dd_ready_sig : std_logic;
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335 | signal dd_send_sig : std_logic := '1';
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336 | signal dd_send_ack_sig : std_logic := '1';
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337 | signal dd_send_ready_sig : std_logic := '1';
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338 | signal config_start_cc_sig : std_logic := '0';
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339 | signal config_started_cc_sig : std_logic := '0';
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340 | signal config_ready_cc_sig : std_logic := '0';
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341 |
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342 | signal clk_buf_sig : std_logic;
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343 | signal clk_1M_sig : STD_LOGIC; -- generated from 50M clock by divider
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344 | signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM
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345 | signal clk_250M_sig : STD_LOGIC; -- generated by internal DCM
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346 | signal clk_250M_ps_sig : STD_LOGIC; -- generated by internal DCM
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347 | signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTM_clk_gen when DCMs have locked
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348 |
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349 | signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up
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350 |
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351 | signal led_sig : std_logic_vector(7 downto 0) := (others => '0');
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352 |
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353 | component FTM_clk_gen
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354 | port(
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355 | clk : IN STD_LOGIC;
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356 | rst : IN STD_LOGIC;
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357 | clk_1 : OUT STD_LOGIC;
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358 | clk_50 : OUT STD_LOGIC;
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359 | clk_250 : OUT STD_LOGIC;
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360 | clk_250_ps : OUT STD_LOGIC;
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361 | ready : OUT STD_LOGIC
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362 | );
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363 | end component;
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364 |
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365 | component Clock_cond_interface is
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366 | port(
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367 | clk : IN STD_LOGIC;
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368 | CLK_Clk_Cond : out STD_LOGIC;
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369 | LE_Clk_Cond : out STD_LOGIC;
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370 | DATA_Clk_Cond : out STD_LOGIC;
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371 | SYNC_Clk_Cond : out STD_LOGIC;
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372 | LD_Clk_Cond : in STD_LOGIC;
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373 | TIM_Sel : out STD_LOGIC;
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374 | cc_R0 : in std_logic_vector (31 downto 0) := (others => '0');
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375 | cc_R1 : in std_logic_vector (31 downto 0) := (others => '0');
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376 | cc_R8 : in std_logic_vector (31 downto 0) := (others => '0');
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377 | cc_R9 : in std_logic_vector (31 downto 0) := (others => '0');
|
---|
378 | cc_R11 : in std_logic_vector (31 downto 0) := (others => '0');
|
---|
379 | cc_R13 : in std_logic_vector (31 downto 0) := (others => '0');
|
---|
380 | cc_R14 : in std_logic_vector (31 downto 0) := (others => '0');
|
---|
381 | cc_R15 : in std_logic_vector (31 downto 0) := (others => '0');
|
---|
382 | start_config : in STD_LOGIC;
|
---|
383 | config_started : out STD_LOGIC;
|
---|
384 | config_done : out STD_LOGIC;
|
---|
385 | timemarker_select: in STD_LOGIC
|
---|
386 | );
|
---|
387 | end component;
|
---|
388 |
|
---|
389 | component FTM_central_control
|
---|
390 | port(
|
---|
391 | clk : IN std_logic;
|
---|
392 | clk_scaler : IN std_logic;
|
---|
393 | new_config : IN std_logic;
|
---|
394 | config_started : OUT std_logic := '0';
|
---|
395 | config_started_ack : IN std_logic;
|
---|
396 | config_start_eth : OUT std_logic := '0';
|
---|
397 | config_started_eth : IN std_logic;
|
---|
398 | config_ready_eth : IN std_logic;
|
---|
399 | config_start_ftu : OUT std_logic := '0';
|
---|
400 | config_started_ftu : IN std_logic;
|
---|
401 | config_ready_ftu : IN std_logic;
|
---|
402 | ping_ftu_start : IN std_logic;
|
---|
403 | ping_ftu_started : OUT std_logic := '0';
|
---|
404 | ping_ftu_ready : OUT std_logic := '0';
|
---|
405 | ping_ftu_start_ftu : OUT std_logic := '0';
|
---|
406 | ping_ftu_started_ftu : IN std_logic;
|
---|
407 | ping_ftu_ready_ftu : IN std_logic;
|
---|
408 | rates_ftu : OUT std_logic := '0';
|
---|
409 | rates_started_ftu : IN std_logic;
|
---|
410 | rates_ready_ftu : IN std_logic;
|
---|
411 | prescaling_FTU01 : IN std_logic_vector(7 downto 0);
|
---|
412 | dd_send : OUT std_logic := '0';
|
---|
413 | dd_send_ack : IN std_logic;
|
---|
414 | dd_send_ready : IN std_logic;
|
---|
415 | config_start_cc : out std_logic := '0';
|
---|
416 | config_started_cc : in std_logic;
|
---|
417 | config_ready_cc : in std_logic
|
---|
418 | );
|
---|
419 | end component;
|
---|
420 |
|
---|
421 | component FTM_ftu_control
|
---|
422 | port(
|
---|
423 | clk_50MHz : in std_logic;
|
---|
424 | rx_en : out STD_LOGIC;
|
---|
425 | tx_en : out STD_LOGIC;
|
---|
426 | rx_d_0 : in STD_LOGIC;
|
---|
427 | tx_d_0 : out STD_LOGIC;
|
---|
428 | rx_d_1 : in STD_LOGIC;
|
---|
429 | tx_d_1 : out STD_LOGIC;
|
---|
430 | rx_d_2 : in STD_LOGIC;
|
---|
431 | tx_d_2 : out STD_LOGIC;
|
---|
432 | rx_d_3 : in STD_LOGIC;
|
---|
433 | tx_d_3 : out STD_LOGIC;
|
---|
434 | new_config : in std_logic;
|
---|
435 | ping_all : in std_logic;
|
---|
436 | read_rates : in std_logic;
|
---|
437 | read_rates_started : out std_logic := '0';
|
---|
438 | read_rates_done : out std_logic := '0';
|
---|
439 | new_config_started : out std_logic := '0';
|
---|
440 | new_config_done : out std_logic := '0';
|
---|
441 | ping_all_started : out std_logic := '0';
|
---|
442 | ping_all_done : out std_logic := '0';
|
---|
443 | ftu_active_cr0 : in std_logic_vector (15 downto 0);
|
---|
444 | ftu_active_cr1 : in std_logic_vector (15 downto 0);
|
---|
445 | ftu_active_cr2 : in std_logic_vector (15 downto 0);
|
---|
446 | ftu_active_cr3 : in std_logic_vector (15 downto 0);
|
---|
447 | static_RAM_busy : in std_logic;
|
---|
448 | static_RAM_started : in std_logic;
|
---|
449 | static_RAM_ready : in std_logic;
|
---|
450 | data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0');
|
---|
451 | read_static_RAM : out std_logic := '0';
|
---|
452 | addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0');
|
---|
453 | dynamic_RAM_busy : in std_logic;
|
---|
454 | dynamic_RAM_started : in std_logic;
|
---|
455 | dynamic_RAM_ready : in std_logic;
|
---|
456 | data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0');
|
---|
457 | write_dynamic_RAM : out std_logic := '0';
|
---|
458 | addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0');
|
---|
459 | FTUlist_RAM_busy : in std_logic;
|
---|
460 | FTUlist_RAM_started : in std_logic;
|
---|
461 | FTUlist_RAM_ready : in std_logic;
|
---|
462 | data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0');
|
---|
463 | write_FTUlist_RAM : out std_logic := '0';
|
---|
464 | addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0')
|
---|
465 | );
|
---|
466 | end component;
|
---|
467 |
|
---|
468 | component ethernet_modul
|
---|
469 | port(
|
---|
470 | wiz_reset : OUT std_logic := '1';
|
---|
471 | wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
|
---|
472 | wiz_data : INOUT std_logic_vector (15 DOWNTO 0);
|
---|
473 | wiz_cs : OUT std_logic := '1';
|
---|
474 | wiz_wr : OUT std_logic := '1';
|
---|
475 | wiz_rd : OUT std_logic := '1';
|
---|
476 | wiz_int : IN std_logic ;
|
---|
477 | clk : IN std_logic ;
|
---|
478 | sd_ready : OUT std_logic ;
|
---|
479 | sd_busy : OUT std_logic ;
|
---|
480 | led : OUT std_logic_vector (7 DOWNTO 0);
|
---|
481 | sd_read_ftu : IN std_logic ;
|
---|
482 | sd_started_ftu : OUT std_logic := '0';
|
---|
483 | cc_R0 : OUT std_logic_vector (31 DOWNTO 0);
|
---|
484 | cc_R1 : OUT std_logic_vector (31 DOWNTO 0);
|
---|
485 | cc_R11 : OUT std_logic_vector (31 DOWNTO 0);
|
---|
486 | cc_R13 : OUT std_logic_vector (31 DOWNTO 0);
|
---|
487 | cc_R14 : OUT std_logic_vector (31 DOWNTO 0);
|
---|
488 | cc_R15 : OUT std_logic_vector (31 DOWNTO 0);
|
---|
489 | cc_R8 : OUT std_logic_vector (31 DOWNTO 0);
|
---|
490 | cc_R9 : OUT std_logic_vector (31 DOWNTO 0);
|
---|
491 | coin_n_c : OUT std_logic_vector (15 DOWNTO 0);
|
---|
492 | coin_n_p : OUT std_logic_vector (15 DOWNTO 0);
|
---|
493 | dead_time : OUT std_logic_vector (15 DOWNTO 0);
|
---|
494 | general_settings : OUT std_logic_vector (15 DOWNTO 0);
|
---|
495 | lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0);
|
---|
496 | lp1_delay : OUT std_logic_vector (15 DOWNTO 0);
|
---|
497 | lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0);
|
---|
498 | lp2_delay : OUT std_logic_vector (15 DOWNTO 0);
|
---|
499 | lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0);
|
---|
500 | lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0);
|
---|
501 | timemarker_delay : OUT std_logic_vector (15 DOWNTO 0);
|
---|
502 | trigger_delay : OUT std_logic_vector (15 DOWNTO 0);
|
---|
503 | sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
|
---|
504 | sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
|
---|
505 | ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0);
|
---|
506 | ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0);
|
---|
507 | ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0);
|
---|
508 | ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0);
|
---|
509 | new_config : OUT std_logic := '0';
|
---|
510 | config_started : IN std_logic ;
|
---|
511 | config_start_eth : IN std_logic ;
|
---|
512 | config_started_eth : OUT std_logic := '0';
|
---|
513 | config_ready_eth : OUT std_logic := '0';
|
---|
514 | config_started_ack : OUT std_logic := '0';
|
---|
515 | fl_busy : OUT std_logic ;
|
---|
516 | fl_ready : OUT std_logic ;
|
---|
517 | fl_write_ftu : IN std_logic ;
|
---|
518 | fl_started_ftu : OUT std_logic := '0';
|
---|
519 | fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
|
---|
520 | fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0');
|
---|
521 | ping_ftu_start : OUT std_logic := '0';
|
---|
522 | ping_ftu_started : IN std_logic ;
|
---|
523 | ping_ftu_ready : IN std_logic ;
|
---|
524 | dd_write_ftu : IN std_logic ;
|
---|
525 | dd_started_ftu : OUT std_logic := '0';
|
---|
526 | dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
|
---|
527 | dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
|
---|
528 | dd_busy : OUT std_logic ;
|
---|
529 | dd_ready : OUT std_logic ;
|
---|
530 | coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
|
---|
531 | coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
|
---|
532 | --new stuff
|
---|
533 | dd_block_ready_ftu : IN std_logic;
|
---|
534 | dd_block_start_ack_ftu : OUT std_logic := '0';
|
---|
535 | dd_block_start_ftu : IN std_logic;
|
---|
536 | dd_send : IN std_logic;
|
---|
537 | dd_send_ack : OUT std_logic := '1';
|
---|
538 | dd_send_ready : OUT std_logic := '1'
|
---|
539 | );
|
---|
540 | end component;
|
---|
541 |
|
---|
542 | begin
|
---|
543 |
|
---|
544 | -- IBUFG: Single-ended global clock input buffer
|
---|
545 | -- Spartan-3A
|
---|
546 | -- Xilinx HDL Language Template, version 11.4
|
---|
547 |
|
---|
548 | IBUFG_inst : IBUFG
|
---|
549 | generic map (
|
---|
550 | IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
|
---|
551 | -- "0"-"16"
|
---|
552 | IOSTANDARD => "DEFAULT")
|
---|
553 | port map (
|
---|
554 | O => clk_buf_sig, -- Clock buffer output
|
---|
555 | I => clk -- Clock buffer input (connect directly to top-level port)
|
---|
556 | );
|
---|
557 |
|
---|
558 | Inst_FTM_clk_gen : FTM_clk_gen
|
---|
559 | port map(
|
---|
560 | clk => clk_buf_sig,
|
---|
561 | rst => reset_sig,
|
---|
562 | clk_1 => clk_1M_sig,
|
---|
563 | clk_50 => clk_50M_sig,
|
---|
564 | clk_250 => clk_250M_sig,
|
---|
565 | clk_250_ps => clk_250M_ps_sig,
|
---|
566 | ready => clk_ready_sig
|
---|
567 | );
|
---|
568 |
|
---|
569 | Inst_Clock_cond_interface : Clock_cond_interface
|
---|
570 | port map(
|
---|
571 | clk => clk_50M_sig,
|
---|
572 | CLK_Clk_Cond => CLK_Clk_Cond,
|
---|
573 | LE_Clk_Cond => LE_Clk_Cond,
|
---|
574 | DATA_Clk_Cond => DATA_Clk_Cond,
|
---|
575 | SYNC_Clk_Cond => SYNC_Clk_Cond,
|
---|
576 | LD_Clk_Cond => LD_Clk_Cond,
|
---|
577 | TIM_Sel => TIM_Sel,
|
---|
578 | cc_R0 => cc_R0_sig,
|
---|
579 | cc_R1 => cc_R1_sig,
|
---|
580 | cc_R8 => cc_R8_sig,
|
---|
581 | cc_R9 => cc_R9_sig,
|
---|
582 | cc_R11 => cc_R11_sig,
|
---|
583 | cc_R13 => cc_R13_sig,
|
---|
584 | cc_R14 => cc_R14_sig,
|
---|
585 | cc_R15 => cc_R15_sig,
|
---|
586 | start_config => config_start_cc_sig,
|
---|
587 | config_started => config_started_cc_sig,
|
---|
588 | config_done => config_ready_cc_sig,
|
---|
589 | timemarker_select => general_settings_sig(0)
|
---|
590 | );
|
---|
591 |
|
---|
592 | Inst_FTM_central_control : FTM_central_control
|
---|
593 | port map(
|
---|
594 | clk => clk_50M_sig,
|
---|
595 | clk_scaler => clk_1M_sig,
|
---|
596 | new_config => new_config_sig,
|
---|
597 | config_started => config_started_sig,
|
---|
598 | config_started_ack => config_started_ack_sig,
|
---|
599 | config_start_eth => config_start_eth_sig,
|
---|
600 | config_started_eth => config_started_eth_sig,
|
---|
601 | config_ready_eth => config_ready_eth_sig,
|
---|
602 | config_start_ftu => config_start_ftu_sig,
|
---|
603 | config_started_ftu => config_started_ftu_sig,
|
---|
604 | config_ready_ftu => config_ready_ftu_sig,
|
---|
605 | ping_ftu_start => ping_ftu_start_sig,
|
---|
606 | ping_ftu_started => ping_ftu_started_sig,
|
---|
607 | ping_ftu_ready => ping_ftu_ready_sig,
|
---|
608 | ping_ftu_start_ftu => ping_ftu_start_ftu_sig,
|
---|
609 | ping_ftu_started_ftu => ping_ftu_started1_sig,
|
---|
610 | ping_ftu_ready_ftu => ping_ftu_ready1_sig,
|
---|
611 | rates_ftu => rates_ftu_start_sig,
|
---|
612 | rates_started_ftu => rates_ftu_started_sig,
|
---|
613 | rates_ready_ftu => rates_ftu_ready_sig,
|
---|
614 | prescaling_FTU01 => "00010011",
|
---|
615 | dd_send => dd_send_sig,
|
---|
616 | dd_send_ack => dd_send_ack_sig,
|
---|
617 | dd_send_ready => dd_send_ready_sig,
|
---|
618 | config_start_cc => config_start_cc_sig,
|
---|
619 | config_started_cc => config_started_cc_sig,
|
---|
620 | config_ready_cc => config_ready_cc_sig
|
---|
621 | );
|
---|
622 |
|
---|
623 | Inst_FTM_ftu_control : FTM_ftu_control
|
---|
624 | port map(
|
---|
625 | clk_50MHz => clk_50M_sig,
|
---|
626 | rx_en => Bus1_Rx_En,
|
---|
627 | tx_en => Bus1_Tx_En,
|
---|
628 | rx_d_0 => Bus1_RxD_0,
|
---|
629 | tx_d_0 => Bus1_TxD_0,
|
---|
630 | rx_d_1 => Bus1_RxD_1,
|
---|
631 | tx_d_1 => Bus1_TxD_1,
|
---|
632 | rx_d_2 => Bus1_RxD_2,
|
---|
633 | tx_d_2 => Bus1_TxD_2,
|
---|
634 | rx_d_3 => Bus1_RxD_3,
|
---|
635 | tx_d_3 => Bus1_TxD_3,
|
---|
636 | new_config => config_start_ftu_sig,
|
---|
637 | ping_all => ping_ftu_start_ftu_sig,
|
---|
638 | read_rates => rates_ftu_start_sig,
|
---|
639 | read_rates_started => rates_ftu_started_sig,
|
---|
640 | read_rates_done => rates_ftu_ready_sig,
|
---|
641 | new_config_started => config_started_ftu_sig,
|
---|
642 | new_config_done => config_ready_ftu_sig,
|
---|
643 | ping_all_started => ping_ftu_started1_sig,
|
---|
644 | ping_all_done => ping_ftu_ready1_sig,
|
---|
645 | ftu_active_cr0 => ftu_active_cr0_sig,
|
---|
646 | ftu_active_cr1 => ftu_active_cr1_sig,
|
---|
647 | ftu_active_cr2 => ftu_active_cr2_sig,
|
---|
648 | ftu_active_cr3 => ftu_active_cr3_sig,
|
---|
649 | static_RAM_busy => sd_busy_sig,
|
---|
650 | static_RAM_started => sd_started_ftu_sig,
|
---|
651 | static_RAM_ready => sd_ready_sig,
|
---|
652 | data_static_RAM => sd_data_out_ftu_sig,
|
---|
653 | read_static_RAM => sd_read_ftu_sig,
|
---|
654 | addr_static_RAM => sd_addr_ftu_sig,
|
---|
655 | dynamic_RAM_busy => dd_busy_sig,
|
---|
656 | dynamic_RAM_started => dd_started_ftu_sig,
|
---|
657 | dynamic_RAM_ready => dd_ready_sig,
|
---|
658 | data_dynamic_RAM => dd_data_sig,
|
---|
659 | write_dynamic_RAM => dd_write_sig,
|
---|
660 | addr_dynamic_RAM => dd_addr_sig,
|
---|
661 | FTUlist_RAM_busy => fl_busy_sig,
|
---|
662 | FTUlist_RAM_started => fl_started_ftu_sig,
|
---|
663 | FTUlist_RAM_ready => fl_ready_sig,
|
---|
664 | data_FTUlist_RAM => fl_data_sig,
|
---|
665 | write_FTUlist_RAM => fl_write_sig,
|
---|
666 | addr_FTUlist_RAM => fl_addr_sig
|
---|
667 | );
|
---|
668 |
|
---|
669 | Inst_ethernet_modul : ethernet_modul
|
---|
670 | port map(
|
---|
671 | wiz_reset => W_RES,
|
---|
672 | wiz_addr => W_A,
|
---|
673 | wiz_data => W_D,
|
---|
674 | wiz_cs => W_CS,
|
---|
675 | wiz_wr => W_WR,
|
---|
676 | wiz_rd => W_RD,
|
---|
677 | wiz_int => W_INT,
|
---|
678 | clk => clk_50M_sig,
|
---|
679 | sd_ready => sd_ready_sig,
|
---|
680 | sd_busy => sd_busy_sig,
|
---|
681 | led => led_sig,
|
---|
682 | sd_read_ftu => sd_read_ftu_sig,
|
---|
683 | sd_started_ftu => sd_started_ftu_sig,
|
---|
684 | cc_R0 => cc_R0_sig,
|
---|
685 | cc_R1 => cc_R1_sig,
|
---|
686 | cc_R11 => cc_R11_sig,
|
---|
687 | cc_R13 => cc_R13_sig,
|
---|
688 | cc_R14 => cc_R14_sig,
|
---|
689 | cc_R15 => cc_R15_sig,
|
---|
690 | cc_R8 => cc_R8_sig,
|
---|
691 | cc_R9 => cc_R9_sig,
|
---|
692 | coin_n_c => coin_n_c_sig,
|
---|
693 | coin_n_p => coin_n_p_sig,
|
---|
694 | dead_time => dead_time_sig,
|
---|
695 | general_settings => general_settings_sig,
|
---|
696 | lp1_amplitude => lp1_amplitude_sig,
|
---|
697 | lp1_delay => lp1_delay_sig,
|
---|
698 | lp2_amplitude => lp2_amplitude_sig,
|
---|
699 | lp2_delay => lp2_delay_sig,
|
---|
700 | lp_pt_freq => lp_pt_freq_sig,
|
---|
701 | lp_pt_ratio => lp_pt_ratio_sig,
|
---|
702 | timemarker_delay => timemarker_delay_sig,
|
---|
703 | trigger_delay => trigger_delay_sig,
|
---|
704 | sd_addr_ftu => sd_addr_ftu_sig,
|
---|
705 | sd_data_out_ftu => sd_data_out_ftu_sig,
|
---|
706 | ftu_active_cr0 => ftu_active_cr0_sig,
|
---|
707 | ftu_active_cr1 => ftu_active_cr1_sig,
|
---|
708 | ftu_active_cr2 => ftu_active_cr2_sig,
|
---|
709 | ftu_active_cr3 => ftu_active_cr3_sig,
|
---|
710 | new_config => new_config_sig,
|
---|
711 | config_started => config_started_sig,
|
---|
712 | config_start_eth => config_start_eth_sig,
|
---|
713 | config_started_eth => config_started_eth_sig,
|
---|
714 | config_ready_eth => config_ready_eth_sig,
|
---|
715 | config_started_ack => config_started_ack_sig,
|
---|
716 | fl_busy => fl_busy_sig,
|
---|
717 | fl_ready => fl_ready_sig,
|
---|
718 | fl_write_ftu => fl_write_sig,
|
---|
719 | fl_started_ftu => fl_started_ftu_sig,
|
---|
720 | fl_addr_ftu => fl_addr_sig,
|
---|
721 | fl_data_in_ftu => fl_data_sig,
|
---|
722 | ping_ftu_start => ping_ftu_start_sig,
|
---|
723 | ping_ftu_started => ping_ftu_started_sig,
|
---|
724 | ping_ftu_ready => ping_ftu_ready_sig,
|
---|
725 | dd_write_ftu => dd_write_sig,
|
---|
726 | dd_started_ftu => dd_started_ftu_sig,
|
---|
727 | dd_data_in_ftu => dd_data_sig,
|
---|
728 | dd_addr_ftu => dd_addr_sig,
|
---|
729 | dd_busy => dd_busy_sig,
|
---|
730 | dd_ready => dd_ready_sig,
|
---|
731 | coin_win_c => coin_win_c_sig,
|
---|
732 | coin_win_p => coin_win_p_sig,
|
---|
733 | --new stuff
|
---|
734 | dd_block_ready_ftu => dd_block_ready_sig,
|
---|
735 | dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig,
|
---|
736 | dd_block_start_ftu => dd_block_start_sig,
|
---|
737 | dd_send => dd_send_sig,
|
---|
738 | dd_send_ack => dd_send_ack_sig,
|
---|
739 | dd_send_ready => dd_send_ready_sig
|
---|
740 | );
|
---|
741 |
|
---|
742 | LED_red <= led_sig(3 downto 0);
|
---|
743 | LED_ye <= led_sig(5 downto 4);
|
---|
744 | LED_gn <= led_sig(7 downto 6);
|
---|
745 |
|
---|
746 | end Behavioral;
|
---|
747 |
|
---|
748 |
|
---|