source: firmware/FTM/FTM_top.vhd@ 10366

Last change on this file since 10366 was 10366, checked in by weitzel, 15 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 39.8 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 08 December 2010
6-- Design Name:
7-- Module Name: FTM_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity for FTM firmware
12--
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27library ftm_definitions;
28USE ftm_definitions.ftm_array_types.all;
29USE ftm_definitions.ftm_constants.all;
30
31---- Uncomment the following library declaration if instantiating
32---- any Xilinx primitives in this code.
33library UNISIM;
34use UNISIM.VComponents.all;
35
36
37entity FTM_top is
38 port(
39
40 -- Clock
41 clk : IN STD_LOGIC; -- external clock from oscillator U47
42
43 -- connection to the WIZnet W5300 ethernet controller
44 -- on IO-Bank 1
45 -------------------------------------------------------------------------------
46 -- W5300 data bus
47 W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
48
49 -- W5300 address bus
50 W_A : out STD_LOGIC_VECTOR(9 downto 0); -- there is no real net W_A0 because
51 -- the W5300 is operated in the
52 -- 16-bit mode
53 -- -> W_A<0> assigned to unconnected pin
54
55 -- W5300 control signals
56 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
57 -- W_CS is also routed to testpoint JP7
58 W_CS : out STD_LOGIC := '1'; -- W5300 chip select
59 W_INT : IN STD_LOGIC; -- interrupt
60 W_RD : out STD_LOGIC := '1'; -- read
61 W_WR : out STD_LOGIC := '1'; -- write
62 W_RES : out STD_LOGIC := '1'; -- reset W5300 chip
63
64 -- W5300 buffer ready indicator
65 -- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
66
67 -- testpoints (T18) associated with the W5300 on IO-bank 1
68 -- W_T : inout STD_LOGIC_VECTOR(3 downto 0);
69
70
71 -- SPI Interface
72 -- connection to the EEPROM U36 (AL25L016M) and
73 -- temperature sensors U45, U46, U48 and U49 (all MAX6662)
74 -- on IO-Bank 1
75 -------------------------------------------------------------------------------
76 -- S_CLK : out STD_LOGIC; -- SPI clock
77
78 -- EEPROM
79 -- MOSI : out STD_LOGIC; -- master out slave in
80 -- MISO : in STD_LOGIC; -- master in slave out
81 -- EE_CS : out STD_LOGIC; -- EEPROM chip select
82
83 -- temperature sensors U45, U46, U48 and U49
84 -- SIO : inout STD_LOGIC; -- serial IO
85 -- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
86
87
88 -- Trigger primitives inputs
89 -- on IO-Bank 2
90 -------------------------------------------------------------------------------
91 Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
92 Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
93 Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
94 Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
95
96
97 -- NIM inputs
98 ------------------------------------------------------------------------------
99 -- on IO-Bank 3
100 ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
101 Veto : in STD_LOGIC; -- trigger veto input
102 -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
103
104 -- on IO-Bank 0
105 -- alternative external clock input for FPGA
106 -- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
107
108
109 -- LEDs on IO-Banks 0 and 3
110 -------------------------------------------------------------------------------
111 LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
112 LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
113 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
114
115
116 -- Clock conditioner LMK03000
117 -- on IO-Bank 3
118 -------------------------------------------------------------------------------
119 CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock
120 LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable
121 DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data
122
123 SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization
124 LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for
125
126
127 -- various RS-485 Interfaces
128 -- on IO-Bank 3
129 -------------------------------------------------------------------------------
130 -- Bus 1: FTU slow control
131 Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
132 Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
133
134 Bus1_RxD_0 : in STD_LOGIC; -- crate 0
135 Bus1_TxD_0 : out STD_LOGIC;
136
137 Bus1_RxD_1 : in STD_LOGIC; -- crate 1
138 Bus1_TxD_1 : out STD_LOGIC;
139
140 Bus1_RxD_2 : in STD_LOGIC; -- crate 2
141 Bus1_TxD_2 : out STD_LOGIC;
142
143 Bus1_RxD_3 : in STD_LOGIC; -- crate 3
144 Bus1_TxD_3 : out STD_LOGIC;
145
146
147 -- Bus 2: Trigger-ID to FAD boards
148 -- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
149 -- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
150
151 -- Bus2_RxD_0 : in STD_LOGIC; -- crate 0
152 -- Bus2_TxD_0 : out STD_LOGIC;
153
154 -- Bus2_RxD_1 : in STD_LOGIC; -- crate 1
155 -- Bus2_TxD_1 : out STD_LOGIC;
156
157 -- Bus2_RxD_2 : in STD_LOGIC; -- crate 2
158 -- Bus2_TxD_2 : out STD_LOGIC;
159
160 -- Bus2_RxD_3 : in STD_LOGIC; -- crate 3
161 -- Bus2_TxD_3 : out STD_LOGIC;
162
163
164 -- auxiliary access
165 -- Aux_Rx_D : in STD_LOGIC;
166 -- Aux_Tx_D : out STD_LOGIC;
167 -- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
168 -- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
169
170
171 -- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
172 -- TrID_Rx_D : in STD_LOGIC;
173 -- TrID_Tx_D : out STD_LOGIC;
174
175
176 -- Crate-Resets
177 -- on IO-Bank 3
178 -------------------------------------------------------------------------------
179 -- Crate_Res0 : out STD_LOGIC;
180 -- Crate_Res1 : out STD_LOGIC;
181 -- Crate_Res2 : out STD_LOGIC;
182 -- Crate_Res3 : out STD_LOGIC;
183
184
185 -- Busy signals from the FAD boards
186 -- on IO-Bank 3
187 -------------------------------------------------------------------------------
188 Busy0 : in STD_LOGIC;
189 Busy1 : in STD_LOGIC;
190 Busy2 : in STD_LOGIC;
191 Busy3 : in STD_LOGIC;
192
193
194 -- NIM outputs
195 -- on IO-Bank 0
196 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
197 -------------------------------------------------------------------------------
198 -- calibration
199 -- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
200 -- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
201 -- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
202 -- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
203
204 -- auxiliarry / spare NIM outputs
205 -- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
206 -- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
207 -- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
208 -- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
209
210
211 -- fast control signal outputs
212 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
213 -------------------------------------------------------------------------------
214 -- RES_p : out STD_LOGIC; -- RES+ Reset
215 -- RES_n : out STD_LOGIC; -- RES- IO-Bank 0
216
217 TRG_p : out STD_LOGIC; -- TRG+ Trigger
218 TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0
219
220 TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
221 TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2
222 TIM_Sel : out STD_LOGIC -- Time Marker selector on IO-Bank 2
223
224 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA
225
226
227 -- LVDS calibration outputs
228 -- on IO-Bank 0
229 -------------------------------------------------------------------------------
230 -- to connector J13
231 -- for light pulsar in the mirror dish
232 -- Cal_0_p : out STD_LOGIC;
233 -- Cal_0_n : out STD_LOGIC;
234 -- Cal_1_p : out STD_LOGIC;
235 -- Cal_1_n : out STD_LOGIC;
236 -- Cal_2_p : out STD_LOGIC;
237 -- Cal_2_n : out STD_LOGIC;
238 -- Cal_3_p : out STD_LOGIC;
239 -- Cal_3_n : out STD_LOGIC;
240
241 -- to connector J12
242 -- for light pulsar inside shutter
243 -- Cal_4_p : out STD_LOGIC;
244 -- Cal_4_n : out STD_LOGIC;
245 -- Cal_5_p : out STD_LOGIC;
246 -- Cal_5_n : out STD_LOGIC;
247 -- Cal_6_p : out STD_LOGIC;
248 -- Cal_6_n : out STD_LOGIC;
249 -- Cal_7_p : out STD_LOGIC;
250 -- Cal_7_n : out STD_LOGIC
251
252
253 -- Testpoints
254 -------------------------------------------------------------------------------
255 -- TP : inout STD_LOGIC_VECTOR(32 downto 0);
256 -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
257
258 -- Board ID - inputs
259 -- local board-ID "solder programmable"
260 -- all on 'input only' pins
261 -------------------------------------------------------------------------------
262 -- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
263
264 );
265end FTM_top;
266
267architecture Behavioral of FTM_top is
268
269 signal cc_R0_sig : std_logic_vector(31 DOWNTO 0);
270 signal cc_R1_sig : std_logic_vector(31 DOWNTO 0);
271 signal cc_R11_sig : std_logic_vector(31 DOWNTO 0);
272 signal cc_R13_sig : std_logic_vector(31 DOWNTO 0);
273 signal cc_R14_sig : std_logic_vector(31 DOWNTO 0);
274 signal cc_R15_sig : std_logic_vector(31 DOWNTO 0);
275 signal cc_R8_sig : std_logic_vector(31 DOWNTO 0);
276 signal cc_R9_sig : std_logic_vector(31 DOWNTO 0);
277 signal coin_n_c_sig : std_logic_vector(15 DOWNTO 0);
278 signal coin_n_p_sig : std_logic_vector(15 DOWNTO 0);
279 signal dead_time_sig : std_logic_vector(15 DOWNTO 0);
280 signal ftu_active_cr0_sig : std_logic_vector(15 DOWNTO 0);
281 signal ftu_active_cr1_sig : std_logic_vector(15 DOWNTO 0);
282 signal ftu_active_cr2_sig : std_logic_vector(15 DOWNTO 0);
283 signal ftu_active_cr3_sig : std_logic_vector(15 DOWNTO 0);
284 signal general_settings_sig : std_logic_vector(15 DOWNTO 0);
285 signal lp1_amplitude_sig : std_logic_vector(15 DOWNTO 0);
286 signal lp1_delay_sig : std_logic_vector(15 DOWNTO 0);
287 signal lp2_amplitude_sig : std_logic_vector(15 DOWNTO 0);
288 signal lp2_delay_sig : std_logic_vector(15 DOWNTO 0);
289 signal lp_pt_freq_sig : std_logic_vector(15 DOWNTO 0);
290 signal lp_pt_ratio_sig : std_logic_vector(15 DOWNTO 0);
291 signal timemarker_delay_sig : std_logic_vector(15 DOWNTO 0);
292 signal trigger_delay_sig : std_logic_vector(15 DOWNTO 0);
293 signal sd_addr_ftu_sig : std_logic_vector(11 DOWNTO 0);
294 signal sd_busy_sig : std_logic;
295 signal sd_data_out_ftu_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
296 signal sd_read_ftu_sig : std_logic;
297 signal sd_ready_sig : std_logic;
298 signal sd_started_ftu_sig : std_logic := '0';
299 signal new_config_sig : std_logic := '0';
300 signal config_started_sig : std_logic := '0';
301 signal config_start_eth_sig : std_logic := '0';
302 signal config_started_eth_sig : std_logic := '0';
303 signal config_ready_eth_sig : std_logic := '0';
304 signal config_started_ack_sig : std_logic := '0';
305 signal ping_ftu_start_sig : std_logic := '0';
306 signal ping_ftu_started_sig : std_logic := '0';
307 signal ping_ftu_ready_sig : std_logic := '0';
308 signal config_start_ftu_sig : std_logic := '0';
309 signal config_started_ftu_sig : std_logic := '0';
310 signal config_ready_ftu_sig : std_logic := '0';
311 signal rates_ftu_start_sig : std_logic := '0';
312 signal rates_ftu_started_sig : std_logic := '0';
313 signal rates_ftu_ready_sig : std_logic := '0';
314 signal fl_busy_sig : std_logic;
315 signal fl_ready_sig : std_logic;
316 signal fl_write_sig : std_logic := '0';
317 signal fl_started_ftu_sig : std_logic := '0';
318 signal fl_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
319 signal fl_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
320 signal ping_ftu_start_ftu_sig : std_logic := '0';
321 signal ping_ftu_started1_sig : std_logic := '0';
322 signal ping_ftu_ready1_sig : std_logic := '0';
323 signal coin_win_c_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
324 signal coin_win_p_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
325 --new or changed stuff
326 signal dd_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
327 signal dd_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
328 signal dd_block_start_sig : std_logic := '0';
329 signal dd_block_start_ack_ftu_sig : std_logic := '0';
330 signal dd_block_ready_sig : std_logic := '0';
331 signal dd_busy_sig : std_logic;
332 signal dd_write_sig : std_logic := '0';
333 signal dd_started_ftu_sig : std_logic := '0';
334 signal dd_ready_sig : std_logic;
335 signal dd_send_sig : std_logic := '1';
336 signal dd_send_ack_sig : std_logic := '1';
337 signal dd_send_ready_sig : std_logic := '1';
338 --very new stuff
339 SIGNAL ftu_error_send_ack_sig : std_logic := '1';
340 SIGNAL ftu_error_send_ready_sig : std_logic := '1';
341 SIGNAL ftu_error_calls_sig : std_logic_vector(15 DOWNTO 0) := X"0000";
342 SIGNAL ftu_error_data_sig : std_logic_vector(223 DOWNTO 0) := (others => '0');
343 SIGNAL ftu_error_send_sig : std_logic := '0';
344 signal prescaling_FTU01_sig : std_logic_vector (15 DOWNTO 0);
345 signal trigger_counter_sig : std_logic_vector (31 DOWNTO 0);
346 signal trigger_counter_read_sig : std_logic;
347 signal trigger_counter_valid_sig : std_logic;
348
349 signal config_start_cc_sig : std_logic := '0';
350 signal config_started_cc_sig : std_logic := '0';
351 signal config_ready_cc_sig : std_logic := '0';
352
353 signal config_trigger_sig : std_logic;
354 signal config_trigger_done_sig : std_logic;
355
356 signal clk_buf_sig : std_logic;
357 signal clk_1M_sig : STD_LOGIC; -- generated from 50M clock by divider
358 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM
359 signal clk_250M_sig : STD_LOGIC; -- generated by internal DCM
360 signal clk_250M_ps_sig : STD_LOGIC; -- generated by internal DCM
361 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTM_clk_gen when DCMs have locked
362
363 signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up
364
365 signal trigger_signal_sig : std_logic := '0';
366 signal TIM_signal_sig : std_logic := '0';
367
368 signal led_sig : std_logic_vector(7 downto 0) := (others => '0');
369
370-- component FTM_clk_gen
371-- port(
372-- clk : IN STD_LOGIC;
373-- rst : IN STD_LOGIC;
374-- clk_1 : OUT STD_LOGIC;
375-- clk_50 : OUT STD_LOGIC;
376-- clk_250 : OUT STD_LOGIC;
377-- clk_250_ps : OUT STD_LOGIC;
378-- ready : OUT STD_LOGIC
379-- );
380-- end component;
381
382 component FTM_clk_gen_2
383 port(
384 clk : IN STD_LOGIC;
385 rst : IN STD_LOGIC;
386 clk_1 : OUT STD_LOGIC;
387 clk_50 : OUT STD_LOGIC;
388 clk_250 : OUT STD_LOGIC;
389 clk_250_ps : OUT STD_LOGIC;
390 ready : OUT STD_LOGIC
391 );
392 end component;
393
394 component trigger_manager
395 port(
396 --clocks
397 clk_50MHz : in std_logic;
398 clk_250MHz : in std_logic;
399 clk_250MHz_180 : in std_logic;
400 --trigger primitives from FTUs
401 trig_prim_0 : in std_logic_vector(9 downto 0); --crate 0
402 trig_prim_1 : in std_logic_vector(9 downto 0); --crate 1
403 trig_prim_2 : in std_logic_vector(9 downto 0); --crate 2
404 trig_prim_3 : in std_logic_vector(9 downto 0); --crate 3
405 --external signals
406 ext_trig_1 : in std_logic;
407 ext_trig_2 : in std_logic;
408 ext_veto : in std_logic;
409 FAD_busy_0 : in std_logic; --crate 0
410 FAD_busy_1 : in std_logic; --crate 1
411 FAD_busy_2 : in std_logic; --crate 2
412 FAD_busy_3 : in std_logic; --crate 3
413 --control signals from e.g. main control
414 start_run : in std_logic; --enable trigger output
415 stop_run : in std_logic; --disable trigger output
416 new_config : in std_logic;
417 --settings register (see FTM Firmware Specifications)
418 general_settings : in std_logic_vector(15 downto 0);
419 LP_and_PED_freq : in std_logic_vector(15 downto 0);
420 LP1_LP2_PED_ratio : in std_logic_vector(15 downto 0);
421 maj_coinc_n_phys : in std_logic_vector(15 downto 0);
422 maj_coinc_n_calib : in std_logic_vector(15 downto 0);
423 trigger_delay : in std_logic_vector(15 downto 0);
424 TIM_delay : in std_logic_vector(15 downto 0);
425 dead_time : in std_logic_vector(15 downto 0);
426 coinc_window_phys : in std_logic_vector(15 downto 0);
427 coinc_window_calib : in std_logic_vector(15 downto 0);
428 active_FTU_list_0 : in std_logic_vector(15 downto 0);
429 active_FTU_list_1 : in std_logic_vector(15 downto 0);
430 active_FTU_list_2 : in std_logic_vector(15 downto 0);
431 active_FTU_list_3 : in std_logic_vector(15 downto 0);
432 --control signals or information for other entities
433 trigger_ID_read : in std_logic;
434 trig_cnt_copy_read : in std_logic;
435 trigger_ID_ready : out std_logic;
436 trigger_ID : out std_logic_vector(55 downto 0);
437 trig_cnt_copy : out std_logic_vector(31 downto 0); --counter reading
438 trig_cnt_copy_valid : out std_logic; --trigger counter reading is valid
439 trigger_active : out std_logic; --phys triggers are enabled/active
440 config_done : out std_logic;
441 LP1_pulse : out std_logic; --send start signal to light pulser 1
442 LP2_pulse : out std_logic; --send start signal to light pulser 2
443 --trigger and time marker output signals to FADs
444 trigger_signal : out std_logic;
445 TIM_signal : out std_logic
446 );
447 end component;
448
449 component Clock_cond_interface is
450 port(
451 clk : IN STD_LOGIC;
452 CLK_Clk_Cond : out STD_LOGIC;
453 LE_Clk_Cond : out STD_LOGIC;
454 DATA_Clk_Cond : out STD_LOGIC;
455 SYNC_Clk_Cond : out STD_LOGIC;
456 LD_Clk_Cond : in STD_LOGIC;
457 TIM_Sel : out STD_LOGIC;
458 cc_R0 : in std_logic_vector (31 downto 0) := (others => '0');
459 cc_R1 : in std_logic_vector (31 downto 0) := (others => '0');
460 cc_R8 : in std_logic_vector (31 downto 0) := (others => '0');
461 cc_R9 : in std_logic_vector (31 downto 0) := (others => '0');
462 cc_R11 : in std_logic_vector (31 downto 0) := (others => '0');
463 cc_R13 : in std_logic_vector (31 downto 0) := (others => '0');
464 cc_R14 : in std_logic_vector (31 downto 0) := (others => '0');
465 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0');
466 start_config : in STD_LOGIC;
467 config_started : out STD_LOGIC;
468 config_done : out STD_LOGIC;
469 timemarker_select: in STD_LOGIC
470 );
471 end component;
472
473 component FTM_central_control
474 port(
475 clk : IN std_logic;
476 clk_ready : in std_logic;
477 clk_scaler : IN std_logic;
478 new_config : IN std_logic;
479 config_started : OUT std_logic := '0';
480 config_started_ack : IN std_logic;
481 config_start_eth : OUT std_logic := '0';
482 config_started_eth : IN std_logic;
483 config_ready_eth : IN std_logic;
484 config_start_ftu : OUT std_logic := '0';
485 config_started_ftu : IN std_logic;
486 config_ready_ftu : IN std_logic;
487 ping_ftu_start : IN std_logic;
488 ping_ftu_started : OUT std_logic := '0';
489 ping_ftu_ready : OUT std_logic := '0';
490 ping_ftu_start_ftu : OUT std_logic := '0';
491 ping_ftu_started_ftu : IN std_logic;
492 ping_ftu_ready_ftu : IN std_logic;
493 rates_ftu : OUT std_logic := '0';
494 rates_started_ftu : IN std_logic;
495 rates_ready_ftu : IN std_logic;
496 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
497 dd_send : OUT std_logic := '0';
498 dd_send_ack : IN std_logic;
499 dd_send_ready : IN std_logic;
500 config_start_cc : out std_logic := '0';
501 config_started_cc : in std_logic;
502 config_ready_cc : in std_logic;
503 config_trigger : out std_logic;
504 config_trigger_done : in std_logic
505 );
506 end component;
507
508 component FTM_ftu_control
509 port(
510 clk_50MHz : in std_logic;
511 rx_en : out STD_LOGIC;
512 tx_en : out STD_LOGIC;
513 rx_d_0 : in STD_LOGIC;
514 tx_d_0 : out STD_LOGIC;
515 rx_d_1 : in STD_LOGIC;
516 tx_d_1 : out STD_LOGIC;
517 rx_d_2 : in STD_LOGIC;
518 tx_d_2 : out STD_LOGIC;
519 rx_d_3 : in STD_LOGIC;
520 tx_d_3 : out STD_LOGIC;
521 new_config : in std_logic;
522 ping_all : in std_logic;
523 read_rates : in std_logic;
524 read_rates_started : out std_logic := '0';
525 read_rates_done : out std_logic := '0';
526 new_config_started : out std_logic := '0';
527 new_config_done : out std_logic := '0';
528 ping_all_started : out std_logic := '0';
529 ping_all_done : out std_logic := '0';
530 ftu_active_cr0 : in std_logic_vector (15 downto 0);
531 ftu_active_cr1 : in std_logic_vector (15 downto 0);
532 ftu_active_cr2 : in std_logic_vector (15 downto 0);
533 ftu_active_cr3 : in std_logic_vector (15 downto 0);
534 static_RAM_busy : in std_logic;
535 static_RAM_started : in std_logic;
536 static_RAM_ready : in std_logic;
537 data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0');
538 read_static_RAM : out std_logic := '0';
539 addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0');
540 dynamic_RAM_busy : in std_logic;
541 dynamic_RAM_started : in std_logic;
542 dynamic_RAM_ready : in std_logic;
543 data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0');
544 write_dynamic_RAM : out std_logic := '0';
545 addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0');
546 FTUlist_RAM_busy : in std_logic;
547 FTUlist_RAM_started : in std_logic;
548 FTUlist_RAM_ready : in std_logic;
549 data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0');
550 write_FTUlist_RAM : out std_logic := '0';
551 addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0')
552 );
553 end component;
554
555 component ethernet_modul
556 port(
557 wiz_reset : OUT std_logic := '1';
558 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
559 wiz_data : INOUT std_logic_vector (15 DOWNTO 0);
560 wiz_cs : OUT std_logic := '1';
561 wiz_wr : OUT std_logic := '1';
562 wiz_rd : OUT std_logic := '1';
563 wiz_int : IN std_logic ;
564 clk : IN std_logic ;
565 sd_ready : OUT std_logic ;
566 sd_busy : OUT std_logic ;
567 led : OUT std_logic_vector (7 DOWNTO 0);
568 sd_read_ftu : IN std_logic ;
569 sd_started_ftu : OUT std_logic := '0';
570 cc_R0 : OUT std_logic_vector (31 DOWNTO 0);
571 cc_R1 : OUT std_logic_vector (31 DOWNTO 0);
572 cc_R11 : OUT std_logic_vector (31 DOWNTO 0);
573 cc_R13 : OUT std_logic_vector (31 DOWNTO 0);
574 cc_R14 : OUT std_logic_vector (31 DOWNTO 0);
575 cc_R15 : OUT std_logic_vector (31 DOWNTO 0);
576 cc_R8 : OUT std_logic_vector (31 DOWNTO 0);
577 cc_R9 : OUT std_logic_vector (31 DOWNTO 0);
578 coin_n_c : OUT std_logic_vector (15 DOWNTO 0);
579 coin_n_p : OUT std_logic_vector (15 DOWNTO 0);
580 dead_time : OUT std_logic_vector (15 DOWNTO 0);
581 general_settings : OUT std_logic_vector (15 DOWNTO 0);
582 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0);
583 lp1_delay : OUT std_logic_vector (15 DOWNTO 0);
584 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0);
585 lp2_delay : OUT std_logic_vector (15 DOWNTO 0);
586 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0);
587 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0);
588 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0);
589 trigger_delay : OUT std_logic_vector (15 DOWNTO 0);
590 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
591 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
592 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0);
593 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0);
594 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0);
595 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0);
596 new_config : OUT std_logic := '0';
597 config_started : IN std_logic ;
598 config_start_eth : IN std_logic ;
599 config_started_eth : OUT std_logic := '0';
600 config_ready_eth : OUT std_logic := '0';
601 config_started_ack : OUT std_logic := '0';
602 fl_busy : OUT std_logic ;
603 fl_ready : OUT std_logic ;
604 fl_write_ftu : IN std_logic ;
605 fl_started_ftu : OUT std_logic := '0';
606 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
607 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0');
608 ping_ftu_start : OUT std_logic := '0';
609 ping_ftu_started : IN std_logic ;
610 ping_ftu_ready : IN std_logic ;
611 dd_write_ftu : IN std_logic ;
612 dd_started_ftu : OUT std_logic := '0';
613 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
614 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
615 dd_busy : OUT std_logic ;
616 dd_ready : OUT std_logic ;
617 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
618 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
619 --new stuff
620 dd_block_ready_ftu : IN std_logic;
621 dd_block_start_ack_ftu : OUT std_logic := '0';
622 dd_block_start_ftu : IN std_logic;
623 dd_send : IN std_logic;
624 dd_send_ack : OUT std_logic := '1';
625 dd_send_ready : OUT std_logic := '1';
626 --very new stuff
627 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
628 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
629 ftu_error_send : IN std_logic;
630 ftu_error_send_ack : OUT std_logic := '1';
631 ftu_error_send_ready : OUT std_logic := '1';
632 prescaling_FTU01 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
633 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0');
634 trigger_counter_read : OUT std_logic := '0';
635 trigger_counter_valid : IN std_logic
636 );
637 end component;
638
639begin
640
641-- -- IBUFG: Single-ended global clock input buffer
642-- -- Spartan-3A
643-- -- Xilinx HDL Language Template, version 11.4
644
645-- IBUFG_inst : IBUFG
646-- generic map (
647-- IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
648-- -- "0"-"16"
649-- IOSTANDARD => "DEFAULT")
650-- port map (
651-- O => clk_buf_sig, -- Clock buffer output
652-- I => clk -- Clock buffer input (connect directly to top-level port)
653-- );
654
655-- Inst_FTM_clk_gen : FTM_clk_gen
656-- port map(
657-- clk => clk_buf_sig,
658-- rst => reset_sig,
659-- clk_1 => clk_1M_sig,
660-- clk_50 => clk_50M_sig,
661-- clk_250 => clk_250M_sig,
662-- clk_250_ps => clk_250M_ps_sig,
663-- ready => clk_ready_sig
664-- );
665
666 Inst_FTM_clk_gen_2 : FTM_clk_gen_2
667 port map(
668 clk => clk,
669 rst => reset_sig,
670 clk_1 => clk_1M_sig,
671 clk_50 => clk_50M_sig,
672 clk_250 => clk_250M_sig,
673 clk_250_ps => clk_250M_ps_sig,
674 ready => clk_ready_sig
675 );
676
677 --differential output buffer for trigger signal
678 OBUFDS_LVDS_33_TRG : OBUFDS_LVDS_33
679 port map(
680 O => TRG_p,
681 OB => TRG_n,
682 I => trigger_signal_sig
683 );
684
685 --differential output buffer for trigger signal
686 OBUFDS_LVDS_33_TIM : OBUFDS_LVDS_33
687 port map(
688 O => TIM_Run_p,
689 OB => TIM_Run_n,
690 I => TIM_signal_sig
691 );
692
693 Inst_trigger_manager : trigger_manager
694 port map(
695 --clocks
696 clk_50MHz => clk_50M_sig,
697 clk_250MHz => clk_250M_sig,
698 clk_250MHz_180 => clk_250M_ps_sig,
699 --trigger primitives from FTUs
700 trig_prim_0 => Trig_Prim_A, --crate 0
701 trig_prim_1 => Trig_Prim_B, --crate 1
702 trig_prim_2 => Trig_Prim_C, --crate 2
703 trig_prim_3 => Trig_Prim_D, --crate 3
704 --external signals
705 ext_trig_1 => ext_Trig(1),
706 ext_trig_2 => ext_Trig(2),
707 ext_veto => Veto,
708 FAD_busy_0 => Busy0, --crate 0
709 FAD_busy_1 => Busy1, --crate 1
710 FAD_busy_2 => Busy2, --crate 2
711 FAD_busy_3 => Busy3, --crate 3
712 --control signals from e.g. main control
713 start_run => '1', --enable trigger output
714 stop_run => '0', --disable trigger output
715 new_config => config_trigger_sig,
716 --settings register (see FTM Firmware Specifications)
717 general_settings => general_settings_sig,
718 LP_and_PED_freq => lp_pt_freq_sig,
719 LP1_LP2_PED_ratio => lp_pt_ratio_sig,
720 maj_coinc_n_phys => coin_n_p_sig,
721 maj_coinc_n_calib => coin_n_c_sig,
722 trigger_delay => trigger_delay_sig,
723 TIM_delay => timemarker_delay_sig,
724 dead_time => dead_time_sig,
725 coinc_window_phys => coin_win_p_sig,
726 coinc_window_calib => coin_win_c_sig,
727 active_FTU_list_0 => ftu_active_cr0_sig,
728 active_FTU_list_1 => ftu_active_cr1_sig,
729 active_FTU_list_2 => ftu_active_cr2_sig,
730 active_FTU_list_3 => ftu_active_cr3_sig,
731 --control signals or information for other entities
732 trigger_ID_read => '0',
733 trig_cnt_copy_read => trigger_counter_read_sig,
734 trigger_ID_ready => open,
735 trigger_ID => open,
736 trig_cnt_copy => trigger_counter_sig, --counter reading
737 trig_cnt_copy_valid => trigger_counter_valid_sig, --trigger counter reading is valid
738 trigger_active => open, --phys triggers are enabled/active
739 config_done => config_trigger_done_sig,
740 LP1_pulse => open, --send start signal to light pulser 1
741 LP2_pulse => open, --send start signal to light pulser 2
742 --trigger and time marker output signals to FADs
743 trigger_signal => trigger_signal_sig,
744 TIM_signal => TIM_signal_sig
745 );
746
747 Inst_Clock_cond_interface : Clock_cond_interface
748 port map(
749 clk => clk_50M_sig,
750 CLK_Clk_Cond => CLK_Clk_Cond,
751 LE_Clk_Cond => LE_Clk_Cond,
752 DATA_Clk_Cond => DATA_Clk_Cond,
753 SYNC_Clk_Cond => SYNC_Clk_Cond,
754 LD_Clk_Cond => LD_Clk_Cond,
755 TIM_Sel => TIM_Sel,
756 cc_R0 => cc_R0_sig,
757 cc_R1 => cc_R1_sig,
758 cc_R8 => cc_R8_sig,
759 cc_R9 => cc_R9_sig,
760 cc_R11 => cc_R11_sig,
761 cc_R13 => cc_R13_sig,
762 cc_R14 => cc_R14_sig,
763 cc_R15 => cc_R15_sig,
764 start_config => config_start_cc_sig,
765 config_started => config_started_cc_sig,
766 config_done => config_ready_cc_sig,
767 timemarker_select => general_settings_sig(0)
768 );
769
770 Inst_FTM_central_control : FTM_central_control
771 port map(
772 clk => clk_50M_sig,
773 clk_ready => clk_ready_sig,
774 clk_scaler => clk_1M_sig,
775 new_config => new_config_sig,
776 config_started => config_started_sig,
777 config_started_ack => config_started_ack_sig,
778 config_start_eth => config_start_eth_sig,
779 config_started_eth => config_started_eth_sig,
780 config_ready_eth => config_ready_eth_sig,
781 config_start_ftu => config_start_ftu_sig,
782 config_started_ftu => config_started_ftu_sig,
783 config_ready_ftu => config_ready_ftu_sig,
784 ping_ftu_start => ping_ftu_start_sig,
785 ping_ftu_started => ping_ftu_started_sig,
786 ping_ftu_ready => ping_ftu_ready_sig,
787 ping_ftu_start_ftu => ping_ftu_start_ftu_sig,
788 ping_ftu_started_ftu => ping_ftu_started1_sig,
789 ping_ftu_ready_ftu => ping_ftu_ready1_sig,
790 rates_ftu => rates_ftu_start_sig,
791 rates_started_ftu => rates_ftu_started_sig,
792 rates_ready_ftu => rates_ftu_ready_sig,
793 prescaling_FTU01 => prescaling_FTU01_sig(7 downto 0),
794 dd_send => dd_send_sig,
795 dd_send_ack => dd_send_ack_sig,
796 dd_send_ready => dd_send_ready_sig,
797 config_start_cc => config_start_cc_sig,
798 config_started_cc => config_started_cc_sig,
799 config_ready_cc => config_ready_cc_sig,
800 config_trigger => config_trigger_sig,
801 config_trigger_done => config_trigger_done_sig
802 );
803
804 Inst_FTM_ftu_control : FTM_ftu_control
805 port map(
806 clk_50MHz => clk_50M_sig,
807 rx_en => Bus1_Rx_En,
808 tx_en => Bus1_Tx_En,
809 rx_d_0 => Bus1_RxD_0,
810 tx_d_0 => Bus1_TxD_0,
811 rx_d_1 => Bus1_RxD_1,
812 tx_d_1 => Bus1_TxD_1,
813 rx_d_2 => Bus1_RxD_2,
814 tx_d_2 => Bus1_TxD_2,
815 rx_d_3 => Bus1_RxD_3,
816 tx_d_3 => Bus1_TxD_3,
817 new_config => config_start_ftu_sig,
818 ping_all => ping_ftu_start_ftu_sig,
819 read_rates => rates_ftu_start_sig,
820 read_rates_started => rates_ftu_started_sig,
821 read_rates_done => rates_ftu_ready_sig,
822 new_config_started => config_started_ftu_sig,
823 new_config_done => config_ready_ftu_sig,
824 ping_all_started => ping_ftu_started1_sig,
825 ping_all_done => ping_ftu_ready1_sig,
826 ftu_active_cr0 => ftu_active_cr0_sig,
827 ftu_active_cr1 => ftu_active_cr1_sig,
828 ftu_active_cr2 => ftu_active_cr2_sig,
829 ftu_active_cr3 => ftu_active_cr3_sig,
830 static_RAM_busy => sd_busy_sig,
831 static_RAM_started => sd_started_ftu_sig,
832 static_RAM_ready => sd_ready_sig,
833 data_static_RAM => sd_data_out_ftu_sig,
834 read_static_RAM => sd_read_ftu_sig,
835 addr_static_RAM => sd_addr_ftu_sig,
836 dynamic_RAM_busy => dd_busy_sig,
837 dynamic_RAM_started => dd_started_ftu_sig,
838 dynamic_RAM_ready => dd_ready_sig,
839 data_dynamic_RAM => dd_data_sig,
840 write_dynamic_RAM => dd_write_sig,
841 addr_dynamic_RAM => dd_addr_sig,
842 FTUlist_RAM_busy => fl_busy_sig,
843 FTUlist_RAM_started => fl_started_ftu_sig,
844 FTUlist_RAM_ready => fl_ready_sig,
845 data_FTUlist_RAM => fl_data_sig,
846 write_FTUlist_RAM => fl_write_sig,
847 addr_FTUlist_RAM => fl_addr_sig
848 );
849
850 Inst_ethernet_modul : ethernet_modul
851 port map(
852 wiz_reset => W_RES,
853 wiz_addr => W_A,
854 wiz_data => W_D,
855 wiz_cs => W_CS,
856 wiz_wr => W_WR,
857 wiz_rd => W_RD,
858 wiz_int => W_INT,
859 clk => clk_50M_sig,
860 sd_ready => sd_ready_sig,
861 sd_busy => sd_busy_sig,
862 led => led_sig,
863 sd_read_ftu => sd_read_ftu_sig,
864 sd_started_ftu => sd_started_ftu_sig,
865 cc_R0 => cc_R0_sig,
866 cc_R1 => cc_R1_sig,
867 cc_R11 => cc_R11_sig,
868 cc_R13 => cc_R13_sig,
869 cc_R14 => cc_R14_sig,
870 cc_R15 => cc_R15_sig,
871 cc_R8 => cc_R8_sig,
872 cc_R9 => cc_R9_sig,
873 coin_n_c => coin_n_c_sig,
874 coin_n_p => coin_n_p_sig,
875 dead_time => dead_time_sig,
876 general_settings => general_settings_sig,
877 lp1_amplitude => lp1_amplitude_sig,
878 lp1_delay => lp1_delay_sig,
879 lp2_amplitude => lp2_amplitude_sig,
880 lp2_delay => lp2_delay_sig,
881 lp_pt_freq => lp_pt_freq_sig,
882 lp_pt_ratio => lp_pt_ratio_sig,
883 timemarker_delay => timemarker_delay_sig,
884 trigger_delay => trigger_delay_sig,
885 sd_addr_ftu => sd_addr_ftu_sig,
886 sd_data_out_ftu => sd_data_out_ftu_sig,
887 ftu_active_cr0 => ftu_active_cr0_sig,
888 ftu_active_cr1 => ftu_active_cr1_sig,
889 ftu_active_cr2 => ftu_active_cr2_sig,
890 ftu_active_cr3 => ftu_active_cr3_sig,
891 new_config => new_config_sig,
892 config_started => config_started_sig,
893 config_start_eth => config_start_eth_sig,
894 config_started_eth => config_started_eth_sig,
895 config_ready_eth => config_ready_eth_sig,
896 config_started_ack => config_started_ack_sig,
897 fl_busy => fl_busy_sig,
898 fl_ready => fl_ready_sig,
899 fl_write_ftu => fl_write_sig,
900 fl_started_ftu => fl_started_ftu_sig,
901 fl_addr_ftu => fl_addr_sig,
902 fl_data_in_ftu => fl_data_sig,
903 ping_ftu_start => ping_ftu_start_sig,
904 ping_ftu_started => ping_ftu_started_sig,
905 ping_ftu_ready => ping_ftu_ready_sig,
906 dd_write_ftu => dd_write_sig,
907 dd_started_ftu => dd_started_ftu_sig,
908 dd_data_in_ftu => dd_data_sig,
909 dd_addr_ftu => dd_addr_sig,
910 dd_busy => dd_busy_sig,
911 dd_ready => dd_ready_sig,
912 coin_win_c => coin_win_c_sig,
913 coin_win_p => coin_win_p_sig,
914 --new stuff
915 dd_block_ready_ftu => dd_block_ready_sig,
916 dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig,
917 dd_block_start_ftu => dd_block_start_sig,
918 dd_send => dd_send_sig,
919 dd_send_ack => dd_send_ack_sig,
920 dd_send_ready => dd_send_ready_sig,
921 --very new stuff
922 ftu_error_calls => ftu_error_calls_sig,
923 ftu_error_data => ftu_error_data_sig,
924 ftu_error_send => ftu_error_send_sig,
925 ftu_error_send_ack => ftu_error_send_ack_sig,
926 ftu_error_send_ready => ftu_error_send_ready_sig,
927 prescaling_FTU01 => prescaling_FTU01_sig,
928 trigger_counter => trigger_counter_sig,
929 trigger_counter_read => trigger_counter_read_sig,
930 trigger_counter_valid => trigger_counter_valid_sig
931 );
932
933 LED_red <= led_sig(3 downto 0);
934 LED_ye <= led_sig(5 downto 4);
935 LED_gn <= led_sig(7 downto 6);
936
937end Behavioral;
938
939
Note: See TracBrowser for help on using the repository browser.