source: firmware/FTM/ethernet/cram_control_beha.vhd@ 11485

Last change on this file since 11485 was 10366, checked in by weitzel, 15 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 14.0 KB
Line 
1--
2-- VHDL Architecture FACT_FTM_lib.cram_control.beha
3--
4-- Created:
5-- by - kai.UNKNOWN (E5PCXX)
6-- at - 14:42:24 01.02.2011
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
9--
10-- updated by Q. Weitzel, March 14, 2011
11--
12
13LIBRARY ieee;
14USE ieee.std_logic_1164.all;
15USE ieee.std_logic_arith.all;
16USE IEEE.STD_LOGIC_UNSIGNED.all;
17-- LIBRARY FACT_FTM_lib;
18-- USE FACT_FTM_lib.ftm_array_types.all;
19-- USE FACT_FTM_lib.ftm_constants.all;
20library ftm_definitions;
21USE ftm_definitions.ftm_array_types.all;
22USE ftm_definitions.ftm_constants.all;
23
24ENTITY cram_control IS
25 PORT(
26 clk : IN std_logic;
27 led : OUT std_logic_vector (7 downto 0) := X"00";
28 cram_data_in : OUT std_logic_vector (15 downto 0) := (others => '0');
29 cram_data_out : IN std_logic_vector (15 downto 0);
30 cram_addr_in, cram_addr_out : OUT std_logic_vector (11 downto 0) := (others => '0');
31 cram_we : OUT std_logic_vector (0 downto 0) := "0";
32 sd_write, sd_read, sd_read_ftu : IN std_logic;
33 sd_busy : OUT std_logic := '1';
34 sd_started, sd_started_ftu : OUT std_logic := '0';
35 sd_ready : OUT std_logic := '0';
36 sd_data_in : IN std_logic_vector (15 downto 0);
37 sd_data_out, sd_data_out_ftu : OUT std_logic_vector (15 downto 0) := (others => '0');
38 sd_addr, sd_addr_ftu : IN std_logic_vector (11 downto 0);
39
40 config_start_cc : IN std_logic;
41 config_started_cc : OUT std_logic := '0';
42 config_ready_cc : OUT std_logic := '0';
43
44 -- data from config ram
45 general_settings : OUT std_logic_vector (15 downto 0) := (others => '0');
46 lp_pt_freq : OUT std_logic_vector (15 downto 0) := (others => '0');
47 lp_pt_ratio : OUT std_logic_vector (15 downto 0) := (others => '0');
48 lp1_amplitude : OUT std_logic_vector (15 downto 0) := (others => '0');
49 lp2_amplitude : OUT std_logic_vector (15 downto 0) := (others => '0');
50 lp1_delay : OUT std_logic_vector (15 downto 0) := (others => '0');
51 lp2_delay : OUT std_logic_vector (15 downto 0) := (others => '0');
52 coin_n_p : OUT std_logic_vector (15 downto 0) := (others => '0');
53 coin_n_c : OUT std_logic_vector (15 downto 0) := (others => '0');
54 trigger_delay : OUT std_logic_vector (15 downto 0) := (others => '0');
55 timemarker_delay : OUT std_logic_vector (15 downto 0) := (others => '0');
56 dead_time : OUT std_logic_vector (15 downto 0) := (others => '0');
57 cc_R0 : OUT std_logic_vector (31 downto 0) := (others => '0');
58 cc_R1 : OUT std_logic_vector (31 downto 0) := (others => '0');
59 cc_R8 : OUT std_logic_vector (31 downto 0) := (others => '0');
60 cc_R9 : OUT std_logic_vector (31 downto 0) := (others => '0');
61 cc_R11 : OUT std_logic_vector (31 downto 0) := (others => '0');
62 cc_R13 : OUT std_logic_vector (31 downto 0) := (others => '0');
63 cc_R14 : OUT std_logic_vector (31 downto 0) := (others => '0');
64 cc_R15 : OUT std_logic_vector (31 downto 0) := (others => '0');
65 coin_win_p : OUT std_logic_vector (15 downto 0) := (others => '0');
66 coin_win_c : OUT std_logic_vector (15 downto 0) := (others => '0');
67 prescaling_FTU01 : OUT std_logic_vector (15 downto 0) := (others => '0');
68 ftu_active_cr0 : OUT std_logic_vector (15 downto 0) := (others => '0');
69 ftu_active_cr1 : OUT std_logic_vector (15 downto 0) := (others => '0');
70 ftu_active_cr2 : OUT std_logic_vector (15 downto 0) := (others => '0');
71 ftu_active_cr3 : OUT std_logic_vector (15 downto 0) := (others => '0')
72 );
73END cram_control ;
74
75ARCHITECTURE beha OF cram_control IS
76
77 type state_cram_proc_type is (CR_INIT, CR_INIT_01, CR_INIT_02, CR_INIT_03,
78 CR_CONFIG, CR_CONFIG_START, CR_CONFIG_01,
79 CR_IDLE, CR_WRITE_START, CR_WRITE_END, CR_READ_START, CR_READ_WAIT, CR_READ_END,
80 CR_DOUT_WIZ_START, CR_DOUT_WIZ_END, CR_DOUT_FTU_START, CR_DOUT_FTU_END);
81 signal state_cram_proc : state_cram_proc_type := CR_INIT;
82 signal next_state : state_cram_proc_type := CR_IDLE;
83
84 signal local_sd_addr : std_logic_vector (11 downto 0) := X"000";
85 signal local_sd_data : std_logic_vector (15 downto 0);
86-- signal addr_cnt : integer range 0 to 4096 := 0;
87 signal addr_cnt : std_logic_vector (11 downto 0) := X"000";
88 signal ftu_cnt : integer range 0 to SD_FTU_NUM := 0;
89 signal ftu_active_cnt : integer range 0 to SD_FTU_ACTIVE_NUM := 0;
90
91BEGIN
92
93 cram_proc : process (clk)
94 begin
95 if rising_edge (clk) then
96 case state_cram_proc is
97
98 when CR_INIT =>
99 addr_cnt <= X"000";
100 state_cram_proc <= CR_INIT_01;
101
102 -- general part of static data block
103 when CR_INIT_01 =>
104 if (addr_cnt < SD_BLOCK_SIZE_GENERAL) then
105 local_sd_addr <= addr_cnt;
106 local_sd_data <= sd_block_default_array (conv_integer (addr_cnt));
107 addr_cnt <= addr_cnt + 1;
108 next_state <= CR_INIT_01;
109 state_cram_proc <= CR_WRITE_START;
110 else
111 addr_cnt <= X"000";
112 ftu_cnt <= 0;
113 state_cram_proc <= CR_INIT_02;
114 end if;
115
116 -- defaults for FTUs
117 when CR_INIT_02 =>
118 if (ftu_cnt < SD_FTU_NUM) then
119 if (addr_cnt < SD_FTU_DATA_SIZE) then
120 local_sd_addr <= SD_FTU_BASE_ADDR + (ftu_cnt * SD_FTU_DATA_SIZE) + addr_cnt;
121 -- only for testing
122 -- local_sd_data <= sd_block_ftu_default_array (conv_integer (addr_cnt)) OR (conv_std_logic_vector (ftu_cnt, 8) & X"00");
123 -- for FTM-Board
124 local_sd_data <= sd_block_ftu_default_array (conv_integer (addr_cnt));
125 -- --
126 addr_cnt <= addr_cnt + 1;
127 next_state <= CR_INIT_02;
128 state_cram_proc <= CR_WRITE_START;
129 else
130 addr_cnt <= X"000";
131 ftu_cnt <= ftu_cnt + 1;
132 end if;
133 else
134 addr_cnt <= X"000";
135 state_cram_proc <= CR_INIT_03;
136 end if;
137
138 -- defaults for active FTU lists
139 when CR_INIT_03 =>
140 if (ftu_active_cnt < SD_FTU_ACTIVE_NUM) then
141 local_sd_addr <= SD_FTU_ACTIVE_BASE_ADDR + conv_std_logic_vector (ftu_active_cnt, 12);
142 -- only for testing
143 -- local_sd_data <= conv_std_logic_vector (ftu_active_cnt, 16);
144 -- for FTM-Board
145 local_sd_data <= sd_block_default_ftu_active_list (ftu_active_cnt);
146 -- --
147 ftu_active_cnt <= ftu_active_cnt + 1;
148 next_state <= CR_INIT_03;
149 state_cram_proc <= CR_WRITE_START;
150 else
151 ftu_active_cnt <= 0;
152 state_cram_proc <= CR_CONFIG;
153 end if;
154
155
156 when CR_CONFIG =>
157 if (config_start_cc = '1') then
158 config_ready_cc <= '0';
159 config_started_cc <= '1';
160 state_cram_proc <= CR_CONFIG_START;
161 end if;
162
163 when CR_CONFIG_START =>
164 if (addr_cnt < SD_BLOCK_SIZE) then
165 if ((addr_cnt < SD_FTU_BASE_ADDR)
166 OR (addr_cnt = SD_ADDR_ftu_prescaling_0)
167 OR (addr_cnt >= SD_FTU_ACTIVE_BASE_ADDR)
168 ) then
169 local_sd_addr <= addr_cnt;
170 next_state <= CR_CONFIG_01;
171 state_cram_proc <= CR_READ_START;
172 elsif (addr_cnt = SD_FTU_BASE_ADDR) then
173 addr_cnt <= SD_ADDR_ftu_prescaling_0;
174 elsif (addr_cnt = (SD_ADDR_ftu_prescaling_0 + 1)) then
175 addr_cnt <= SD_FTU_ACTIVE_BASE_ADDR;
176 end if;
177 else
178 addr_cnt <= X"000";
179 config_started_cc <= '0';
180 config_ready_cc <= '1';
181 state_cram_proc <= CR_IDLE;
182 end if;
183
184 when CR_CONFIG_01 =>
185 state_cram_proc <= CR_CONFIG_START;
186 addr_cnt <= addr_cnt + 1;
187 case addr_cnt is
188 when SD_ADDR_general_settings =>
189 general_settings <= local_sd_data;
190 when SD_ADDR_led =>
191 led <= local_sd_data (7 downto 0);
192 when SD_ADDR_lp_pt_freq =>
193 lp_pt_freq <= local_sd_data;
194 when SD_ADDR_lp_pt_ratio =>
195 lp_pt_ratio <= local_sd_data;
196 when SD_ADDR_lp1_amplitude =>
197 lp1_amplitude <= local_sd_data;
198 when SD_ADDR_lp2_amplitude =>
199 lp2_amplitude <= local_sd_data;
200 when SD_ADDR_lp1_delay =>
201 lp1_delay <= local_sd_data;
202 when SD_ADDR_lp2_delay =>
203 lp2_delay <= local_sd_data;
204 when SD_ADDR_coin_n_p =>
205 coin_n_p <= local_sd_data;
206 when SD_ADDR_coin_n_c =>
207 coin_n_c <= local_sd_data;
208 when SD_ADDR_trigger_delay =>
209 trigger_delay <= local_sd_data;
210 when SD_ADDR_timemarker_delay =>
211 timemarker_delay <= local_sd_data;
212 when SD_ADDR_dead_time =>
213 dead_time <= local_sd_data;
214 when SD_ADDR_cc_R0_HI =>
215 cc_R0 (31 downto 16) <= local_sd_data;
216 when SD_ADDR_cc_R0_LO =>
217 cc_R0 (15 downto 0) <= local_sd_data;
218 when SD_ADDR_cc_R1_HI =>
219 cc_R1 (31 downto 16) <= local_sd_data;
220 when SD_ADDR_cc_R1_LO =>
221 cc_R1 (15 downto 0) <= local_sd_data;
222 when SD_ADDR_cc_R8_HI =>
223 cc_R8 (31 downto 16) <= local_sd_data;
224 when SD_ADDR_cc_R8_LO =>
225 cc_R8 (15 downto 0) <= local_sd_data;
226 when SD_ADDR_cc_R9_HI =>
227 cc_R9 (31 downto 16) <= local_sd_data;
228 when SD_ADDR_cc_R9_LO =>
229 cc_R9 (15 downto 0) <= local_sd_data;
230 when SD_ADDR_cc_R11_HI =>
231 cc_R11 (31 downto 16) <= local_sd_data;
232 when SD_ADDR_cc_R11_LO =>
233 cc_R11 (15 downto 0) <= local_sd_data;
234 when SD_ADDR_cc_R13_HI =>
235 cc_R13 (31 downto 16) <= local_sd_data;
236 when SD_ADDR_cc_R13_LO =>
237 cc_R13 (15 downto 0) <= local_sd_data;
238 when SD_ADDR_cc_R14_HI =>
239 cc_R14 (31 downto 16) <= local_sd_data;
240 when SD_ADDR_cc_R14_LO =>
241 cc_R14 (15 downto 0) <= local_sd_data;
242 when SD_ADDR_cc_R15_HI =>
243 cc_R15 (31 downto 16) <= local_sd_data;
244 when SD_ADDR_cc_R15_LO =>
245 cc_R15 (15 downto 0) <= local_sd_data;
246 when SD_ADDR_coin_win_p =>
247 coin_win_p <= local_sd_data;
248 when SD_ADDR_coin_win_c =>
249 coin_win_c <= local_sd_data;
250 when SD_ADDR_ftu_prescaling_0 =>
251 prescaling_FTU01 <= local_sd_data;
252 when SD_ADDR_ftu_active_cr0 =>
253 ftu_active_cr0 <= local_sd_data;
254 when SD_ADDR_ftu_active_cr1 =>
255 ftu_active_cr1 <= local_sd_data;
256 when SD_ADDR_ftu_active_cr2 =>
257 ftu_active_cr2 <= local_sd_data;
258 when SD_ADDR_ftu_active_cr3 =>
259 ftu_active_cr3 <= local_sd_data;
260 when others =>
261 null;
262 end case;
263
264 when CR_IDLE =>
265 sd_busy <= '0';
266
267 if (config_start_cc = '1') then
268 sd_busy <= '1';
269 state_cram_proc <= CR_CONFIG;
270
271 elsif (sd_write = '1') then
272 sd_busy <= '1';
273 sd_started <= '1';
274 sd_ready <= '0';
275 local_sd_addr <= sd_addr;
276 local_sd_data <= sd_data_in;
277 next_state <= CR_IDLE;
278 state_cram_proc <= CR_WRITE_START;
279
280 elsif (sd_read = '1') then
281 sd_busy <= '1';
282 sd_started <= '1';
283 sd_ready <= '0';
284 local_sd_addr <= sd_addr;
285 next_state <= CR_DOUT_WIZ_START;
286 state_cram_proc <= CR_READ_START;
287
288 elsif (sd_read_ftu = '1') then
289 sd_busy <= '1';
290 sd_started_ftu <= '1';
291 sd_ready <= '0';
292 local_sd_addr <= sd_addr_ftu;
293 next_state <= CR_DOUT_FTU_START;
294 state_cram_proc <= CR_READ_START;
295 end if;
296
297
298 when CR_DOUT_FTU_START =>
299 sd_data_out_ftu <= local_sd_data;
300 sd_ready <= '1';
301 state_cram_proc <= CR_DOUT_FTU_END;
302
303 when CR_DOUT_FTU_END =>
304 if (sd_read_ftu <= '0') then
305 sd_started_ftu <= '0';
306 state_cram_proc <= CR_IDLE;
307 end if;
308
309 when CR_DOUT_WIZ_START =>
310 sd_data_out <= local_sd_data;
311 sd_ready <= '1';
312 state_cram_proc <= CR_DOUT_WIZ_END;
313
314 when CR_DOUT_WIZ_END =>
315 if (sd_read <= '0') then
316 sd_started <= '0';
317 state_cram_proc <= CR_IDLE;
318 end if;
319
320
321 -- --
322 -- write to config ram
323 -- --
324 when CR_WRITE_START =>
325 cram_addr_in <= local_sd_addr;
326 cram_data_in <= local_sd_data;
327 cram_we <= "1";
328 state_cram_proc <= CR_WRITE_END;
329
330 when CR_WRITE_END =>
331 cram_we <= "0";
332 if (sd_write = '0') then
333 sd_started <= '0';
334 sd_ready <= '1';
335 state_cram_proc <= next_state;
336 end if;
337
338 -- --
339 -- read from config ram
340 -- --
341 when CR_READ_START =>
342 cram_addr_out <= local_sd_addr;
343 state_cram_proc <= CR_READ_WAIT;
344
345 when CR_READ_WAIT =>
346 state_cram_proc <= CR_READ_END;
347
348 when CR_READ_END =>
349 local_sd_data <= cram_data_out;
350 state_cram_proc <= next_state;
351
352
353 end case;
354 end if; -- rising edge
355 end process cram_proc;
356
357END ARCHITECTURE beha;
358
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