source: firmware/FTM/ethernet/ethernet_modul_beha.vhd@ 10306

Last change on this file since 10306 was 10256, checked in by weitzel, 15 years ago
new version of FTM ethernet module; first version of clock conditioner
File size: 31.7 KB
Line 
1-- VHDL Entity FACT_FTM_lib.ethernet_modul.symbol
2--
3-- Created:
4-- by - kai.UNKNOWN (E5PCXX)
5-- at - 11:52:19 03.03.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9
10LIBRARY ieee;
11USE ieee.std_logic_1164.all;
12USE ieee.std_logic_arith.all;
13--LIBRARY FACT_FTM_lib;
14library ftm_definitions;
15USE ftm_definitions.ftm_array_types.all;
16USE ftm_definitions.ftm_constants.all;
17
18ENTITY ethernet_modul IS
19 PORT(
20 wiz_reset : OUT std_logic := '1';
21 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
22 wiz_data : INOUT std_logic_vector (15 DOWNTO 0);
23 wiz_cs : OUT std_logic := '1';
24 wiz_wr : OUT std_logic := '1';
25 wiz_rd : OUT std_logic := '1';
26 wiz_int : IN std_logic;
27 clk : IN std_logic;
28 sd_ready : OUT std_logic;
29 sd_busy : OUT std_logic;
30 led : OUT std_logic_vector (7 DOWNTO 0);
31 sd_read_ftu : IN std_logic;
32 sd_started_ftu : OUT std_logic := '0';
33 cc_R0 : OUT std_logic_vector (31 DOWNTO 0);
34 cc_R1 : OUT std_logic_vector (31 DOWNTO 0);
35 cc_R11 : OUT std_logic_vector (31 DOWNTO 0);
36 cc_R13 : OUT std_logic_vector (31 DOWNTO 0);
37 cc_R14 : OUT std_logic_vector (31 DOWNTO 0);
38 cc_R15 : OUT std_logic_vector (31 DOWNTO 0);
39 cc_R8 : OUT std_logic_vector (31 DOWNTO 0);
40 cc_R9 : OUT std_logic_vector (31 DOWNTO 0);
41 coin_n_c : OUT std_logic_vector (15 DOWNTO 0);
42 coin_n_p : OUT std_logic_vector (15 DOWNTO 0);
43 dead_time : OUT std_logic_vector (15 DOWNTO 0);
44 -- data from config ram
45 general_settings : OUT std_logic_vector (15 DOWNTO 0);
46 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0);
47 lp1_delay : OUT std_logic_vector (15 DOWNTO 0);
48 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0);
49 lp2_delay : OUT std_logic_vector (15 DOWNTO 0);
50 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0);
51 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0);
52 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0);
53 trigger_delay : OUT std_logic_vector (15 DOWNTO 0);
54 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
55 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
56 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0);
57 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0);
58 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0);
59 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0);
60 new_config : OUT std_logic := '0';
61 config_started : IN std_logic;
62 config_start_eth : IN std_logic;
63 config_started_eth : OUT std_logic := '0';
64 config_ready_eth : OUT std_logic := '0';
65 config_started_ack : OUT std_logic := '0';
66 fl_busy : OUT std_logic;
67 fl_ready : OUT std_logic;
68 fl_write_ftu : IN std_logic;
69 fl_started_ftu : OUT std_logic := '0';
70 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
71 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0');
72 --
73 ping_ftu_start : OUT std_logic := '0';
74 ping_ftu_started : IN std_logic;
75 ping_ftu_ready : IN std_logic;
76 dd_write_ftu : IN std_logic;
77 dd_started_ftu : OUT std_logic := '0';
78 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
79 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
80 dd_busy : OUT std_logic;
81 dd_ready : OUT std_logic;
82 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
83 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
84 dd_block_ready_ftu : IN std_logic;
85 dd_block_start_ack_ftu : OUT std_logic := '0';
86 dd_block_start_ftu : IN std_logic;
87 dd_send : IN std_logic;
88 dd_send_ack : OUT std_logic := '1';
89 dd_send_ready : OUT std_logic := '1'
90 );
91END ethernet_modul ;
92
93ARCHITECTURE beha OF ethernet_modul IS
94
95 -- Architecture declarations
96
97 -- Internal signal declarations
98 SIGNAL busy : std_logic := '1';
99 SIGNAL cram_data_out : std_logic_vector(15 DOWNTO 0);
100 SIGNAL cram_data_in : std_logic_vector(15 DOWNTO 0);
101 SIGNAL cram_we : std_logic_vector(0 DOWNTO 0) := "0";
102 SIGNAL sd_write : std_logic := '0';
103 SIGNAL sd_read : std_logic;
104 SIGNAL led1 : std_logic_vector(7 DOWNTO 0) := (others => '0');
105 SIGNAL sd_started : std_logic;
106 SIGNAL sd_addr : std_logic_vector(11 DOWNTO 0);
107 SIGNAL cram_addr_out : std_logic_vector(11 DOWNTO 0);
108 SIGNAL cram_addr_in : std_logic_vector(11 DOWNTO 0);
109 SIGNAL sd_data_in : std_logic_vector(15 DOWNTO 0) := (others => '0');
110 SIGNAL sd_data_out : std_logic_vector(15 DOWNTO 0);
111 SIGNAL config_ready_cc : std_logic := '0';
112 SIGNAL config_started_cc : std_logic := '0';
113 SIGNAL config_start_cc : std_logic;
114 SIGNAL fl_started : std_logic;
115 SIGNAL fl_read : std_logic := '0';
116 --
117 SIGNAL fl_addr : std_logic_vector(11 DOWNTO 0);
118 SIGNAL fl_data_out : std_logic_vector(15 DOWNTO 0);
119 SIGNAL fram_addr_out : std_logic_vector(11 DOWNTO 0);
120 SIGNAL doutb : std_logic_VECTOR(15 DOWNTO 0);
121 SIGNAL fram_we : std_logic_vector(0 DOWNTO 0) := "0";
122 SIGNAL fram_addr_in : std_logic_vector(11 DOWNTO 0);
123 SIGNAL fram_data_in : std_logic_vector(15 DOWNTO 0);
124 SIGNAL dram_addr_out : std_logic_vector(11 DOWNTO 0);
125 SIGNAL doutb1 : std_logic_VECTOR(15 DOWNTO 0);
126 SIGNAL dram_we : std_logic_vector(0 DOWNTO 0) := "0";
127 SIGNAL dram_addr_in : std_logic_vector(11 DOWNTO 0);
128 SIGNAL dram_data_in : std_logic_vector(15 DOWNTO 0);
129 SIGNAL dd_read : std_logic;
130 SIGNAL dd_started : std_logic := '0';
131 SIGNAL dd_data_out : std_logic_vector(15 DOWNTO 0) := (others => '0');
132 SIGNAL dd_addr : std_logic_vector(11 DOWNTO 0);
133 SIGNAL dd_block_ready : std_logic := '0';
134 --
135 SIGNAL dd_block_start : std_logic := '0';
136 SIGNAL dd_block_start_ack : std_logic;
137 SIGNAL dd_write_general : std_logic := '0';
138 SIGNAL dd_write_general_ready : std_logic;
139 SIGNAL dd_write_general_started : std_logic;
140 SIGNAL dd_write : std_logic := '0';
141 SIGNAL dd_started_general : std_logic := '0';
142 SIGNAL dd_addr1 : std_logic_vector(11 DOWNTO 0) := (others => '0');
143 SIGNAL dd_data : std_logic_vector(15 DOWNTO 0) := (others => '0');
144 SIGNAL get_header : std_logic;
145 SIGNAL get_header_started : std_logic := '0';
146 SIGNAL get_header_ready : std_logic := '0';
147 SIGNAL led2 : std_logic_vector(7 DOWNTO 0);
148 SIGNAL header_board_id : std_logic_vector(63 DOWNTO 0);
149 SIGNAL header_firmware_id : std_logic_vector(15 DOWNTO 0);
150 SIGNAL header_timestamp_counter : std_logic_vector(47 DOWNTO 0);
151 SIGNAL header_trigger_counter : std_logic_vector(31 DOWNTO 0);
152
153 -- Implicit buffer signal declarations
154 SIGNAL dd_busy_internal : std_logic;
155 SIGNAL dd_ready_internal : std_logic;
156 SIGNAL fl_busy_internal : std_logic;
157 SIGNAL fl_ready_internal : std_logic;
158 SIGNAL sd_busy_internal : std_logic;
159 SIGNAL sd_ready_internal : std_logic;
160
161
162 -- Component Declarations
163 COMPONENT CRAM_4096_16b
164 PORT (
165 clka : IN std_logic ;
166 dina : IN std_logic_VECTOR (15 DOWNTO 0);
167 addra : IN std_logic_VECTOR (11 DOWNTO 0);
168 wea : IN std_logic_VECTOR (0 DOWNTO 0);
169 clkb : IN std_logic ;
170 addrb : IN std_logic_VECTOR (11 DOWNTO 0);
171 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
172 );
173 END COMPONENT;
174 COMPONENT DRAM_4096_16b
175 PORT (
176 clka : IN std_logic ;
177 dina : IN std_logic_VECTOR (15 DOWNTO 0);
178 addra : IN std_logic_VECTOR (11 DOWNTO 0);
179 wea : IN std_logic_VECTOR (0 DOWNTO 0);
180 clkb : IN std_logic ;
181 addrb : IN std_logic_VECTOR (11 DOWNTO 0);
182 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
183 );
184 END COMPONENT;
185 COMPONENT FRAM_4096_16b
186 PORT (
187 clka : IN std_logic ;
188 dina : IN std_logic_VECTOR (15 DOWNTO 0);
189 addra : IN std_logic_VECTOR (11 DOWNTO 0);
190 wea : IN std_logic_VECTOR (0 DOWNTO 0);
191 clkb : IN std_logic ;
192 addrb : IN std_logic_VECTOR (11 DOWNTO 0);
193 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
194 );
195 END COMPONENT;
196 COMPONENT cram_control
197 PORT (
198 clk : IN std_logic ;
199 led : OUT std_logic_vector (7 DOWNTO 0) := X"00";
200 cram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
201 cram_data_out : IN std_logic_vector (15 DOWNTO 0);
202 cram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
203 cram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
204 cram_we : OUT std_logic_vector (0 DOWNTO 0) := "0";
205 sd_write : IN std_logic ;
206 sd_read : IN std_logic ;
207 sd_read_ftu : IN std_logic ;
208 sd_busy : OUT std_logic := '1';
209 sd_started : OUT std_logic := '0';
210 sd_started_ftu : OUT std_logic := '0';
211 sd_ready : OUT std_logic := '0';
212 sd_data_in : IN std_logic_vector (15 DOWNTO 0);
213 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
214 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
215 sd_addr : IN std_logic_vector (11 DOWNTO 0);
216 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
217 config_start_cc : IN std_logic ;
218 config_started_cc : OUT std_logic := '0';
219 config_ready_cc : OUT std_logic := '0';
220 -- data from config ram
221 general_settings : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
222 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
223 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
224 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
225 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
226 lp1_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
227 lp2_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
228 coin_n_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
229 coin_n_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
230 trigger_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
231 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
232 dead_time : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
233 cc_R0 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
234 cc_R1 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
235 cc_R8 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
236 cc_R9 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
237 cc_R11 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
238 cc_R13 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
239 cc_R14 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
240 cc_R15 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
241 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
242 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
243 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
244 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
245 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
246 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
247 );
248 END COMPONENT;
249 COMPONENT dd_write_general_modul
250 PORT (
251 clk : IN std_logic ;
252 dd_write_general : IN std_logic ;
253 dd_write_general_started : OUT std_logic := '0';
254 dd_write_general_ready : OUT std_logic := '0';
255 dd_busy : IN std_logic ;
256 dd_write : OUT std_logic := '0';
257 dd_started : IN std_logic ;
258 dd_ready : IN std_logic ;
259 dd_addr : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
260 dd_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
261 );
262 END COMPONENT;
263 COMPONENT dram_control
264 PORT (
265 clk : IN std_logic ;
266 dram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
267 dram_data_out : IN std_logic_vector (15 DOWNTO 0);
268 dram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
269 dram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
270 dram_we : OUT std_logic_vector (0 DOWNTO 0) := "0";
271 dd_block_start : IN std_logic ;
272 dd_block_start_ftu : IN std_logic ;
273 dd_block_start_ack : OUT std_logic := '0';
274 dd_block_start_ack_ftu : OUT std_logic := '0';
275 dd_block_ready : IN std_logic ;
276 dd_block_ready_ftu : IN std_logic ;
277 dd_read : IN std_logic ;
278 dd_write_ftu : IN std_logic ;
279 dd_write_general : IN std_logic ;
280 dd_busy : OUT std_logic := '1';
281 dd_started : OUT std_logic := '0';
282 dd_started_ftu : OUT std_logic := '0';
283 dd_started_general : OUT std_logic := '0';
284 dd_ready : OUT std_logic := '0';
285 dd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
286 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
287 dd_data_in_general : IN std_logic_vector (15 DOWNTO 0);
288 dd_addr : IN std_logic_vector (11 DOWNTO 0);
289 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
290 dd_addr_general : IN std_logic_vector (11 DOWNTO 0)
291 );
292 END COMPONENT;
293 COMPONENT eth_config_modul
294 PORT (
295 clk : IN std_logic ;
296 config_start_eth : IN std_logic ;
297 config_started_eth : OUT std_logic := '0';
298 config_ready_eth : OUT std_logic := '0';
299 config_start_cc : OUT std_logic := '0';
300 config_started_cc : IN std_logic ;
301 config_ready_cc : IN std_logic
302 );
303 END COMPONENT;
304 COMPONENT fram_control
305 PORT (
306 clk : IN std_logic ;
307 fram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
308 fram_data_out : IN std_logic_vector (15 DOWNTO 0);
309 fram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
310 fram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
311 fram_we : OUT std_logic_vector (0 DOWNTO 0) := "0";
312 fl_read : IN std_logic ;
313 fl_write_ftu : IN std_logic ;
314 fl_busy : OUT std_logic := '1';
315 fl_started : OUT std_logic := '0';
316 fl_started_ftu : OUT std_logic := '0';
317 fl_ready : OUT std_logic := '0';
318 fl_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
319 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
320 fl_addr : IN std_logic_vector (11 DOWNTO 0);
321 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0)
322 );
323 END COMPONENT;
324 COMPONENT header_modul
325 PORT (
326 clk : IN std_logic ;
327 get_header : IN std_logic ;
328 get_header_started : OUT std_logic := '0';
329 get_header_ready : OUT std_logic := '0';
330 header_board_id : OUT std_logic_vector (63 DOWNTO 0) := (others => '0');
331 header_firmware_id : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
332 header_trigger_counter : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
333 header_timestamp_counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0')
334 );
335 END COMPONENT;
336 COMPONENT w5300_modul
337 PORT (
338 clk : IN std_logic ;
339 wiz_reset : OUT std_logic := '1';
340 addr : OUT std_logic_vector (9 DOWNTO 0);
341 data : INOUT std_logic_vector (15 DOWNTO 0);
342 cs : OUT std_logic := '1';
343 wr : OUT std_logic := '1';
344 led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
345 rd : OUT std_logic := '1';
346 int : IN std_logic ;
347 busy : OUT std_logic := '1';
348 new_config : OUT std_logic := '0';
349 config_started : IN std_logic ;
350 config_started_ack : OUT std_logic := '0';
351 --
352 ping_ftu_start : OUT std_logic := '0';
353 ping_ftu_started : IN std_logic ;
354 ping_ftu_ready : IN std_logic ;
355 --
356 sd_addr : OUT std_logic_vector (11 DOWNTO 0);
357 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
358 sd_data_in : IN std_logic_vector (15 DOWNTO 0);
359 sd_write : OUT std_logic := '0';
360 sd_read : OUT std_logic := '0';
361 sd_started : IN std_logic ;
362 sd_ready : IN std_logic ;
363 sd_busy : IN std_logic ;
364 --
365 dd_block_start : OUT std_logic := '0';
366 dd_block_start_ack : IN std_logic ;
367 dd_block_ready : OUT std_logic := '1';
368 dd_send : IN std_logic ;
369 dd_send_ack : OUT std_logic := '1';
370 dd_send_ready : OUT std_logic := '1';
371 dd_addr : OUT std_logic_vector (11 DOWNTO 0);
372 dd_data_in : IN std_logic_vector (15 DOWNTO 0);
373 dd_read : OUT std_logic := '0';
374 dd_started : IN std_logic ;
375 dd_ready : IN std_logic ;
376 dd_busy : IN std_logic ;
377 dd_write_general : OUT std_logic := '0';
378 dd_write_general_started : IN std_logic ;
379 dd_write_general_ready : IN std_logic ;
380 --
381 fl_addr : OUT std_logic_vector (11 DOWNTO 0);
382 fl_data_in : IN std_logic_vector (15 DOWNTO 0);
383 fl_read : OUT std_logic := '0';
384 fl_started : IN std_logic ;
385 fl_ready : IN std_logic ;
386 fl_busy : IN std_logic ;
387 --
388 get_header : OUT std_logic := '0';
389 get_header_started : IN std_logic ;
390 get_header_ready : IN std_logic ;
391 header_board_id : IN std_logic_vector (63 DOWNTO 0);
392 header_firmware_id : IN std_logic_vector (15 DOWNTO 0);
393 header_trigger_counter : IN std_logic_vector (31 DOWNTO 0);
394 header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0)
395 );
396 END COMPONENT;
397
398 -- Optional embedded configurations
399 -- pragma synthesis_off
400 -- FOR ALL : CRAM_4096_16b USE ENTITY FACT_FTM_lib.CRAM_4096_16b;
401 -- FOR ALL : DRAM_4096_16b USE ENTITY FACT_FTM_lib.DRAM_4096_16b;
402 -- FOR ALL : FRAM_4096_16b USE ENTITY FACT_FTM_lib.FRAM_4096_16b;
403 -- FOR ALL : cram_control USE ENTITY FACT_FTM_lib.cram_control;
404 -- FOR ALL : dd_write_general_modul USE ENTITY FACT_FTM_lib.dd_write_general_modul;
405 -- FOR ALL : dram_control USE ENTITY FACT_FTM_lib.dram_control;
406 -- FOR ALL : eth_config_modul USE ENTITY FACT_FTM_lib.eth_config_modul;
407 -- FOR ALL : fram_control USE ENTITY FACT_FTM_lib.fram_control;
408 -- FOR ALL : header_modul USE ENTITY FACT_FTM_lib.header_modul;
409 -- FOR ALL : w5300_modul USE ENTITY FACT_FTM_lib.w5300_modul;
410 -- pragma synthesis_on
411
412BEGIN
413
414 -- ModuleWare code(v1.9) for instance 'U_3' of 'or'
415 led <= led1 OR led2;
416
417 -- Instance port mappings.
418 U_1 : CRAM_4096_16b
419 PORT MAP (
420 clka => clk,
421 dina => cram_data_in,
422 addra => cram_addr_in,
423 wea => cram_we,
424 clkb => clk,
425 addrb => cram_addr_out,
426 doutb => cram_data_out
427 );
428 U_7 : DRAM_4096_16b
429 PORT MAP (
430 clka => clk,
431 dina => dram_data_in,
432 addra => dram_addr_in,
433 wea => dram_we,
434 clkb => clk,
435 addrb => dram_addr_out,
436 doutb => doutb1
437 );
438 U_5 : FRAM_4096_16b
439 PORT MAP (
440 clka => clk,
441 dina => fram_data_in,
442 addra => fram_addr_in,
443 wea => fram_we,
444 clkb => clk,
445 addrb => fram_addr_out,
446 doutb => doutb
447 );
448 U_2 : cram_control
449 PORT MAP (
450 clk => clk,
451 led => led2,
452 cram_data_in => cram_data_in,
453 cram_data_out => cram_data_out,
454 cram_addr_in => cram_addr_in,
455 cram_addr_out => cram_addr_out,
456 cram_we => cram_we,
457 sd_write => sd_write,
458 sd_read => sd_read,
459 sd_read_ftu => sd_read_ftu,
460 sd_busy => sd_busy_internal,
461 sd_started => sd_started,
462 sd_started_ftu => sd_started_ftu,
463 sd_ready => sd_ready_internal,
464 sd_data_in => sd_data_in,
465 sd_data_out => sd_data_out,
466 sd_data_out_ftu => sd_data_out_ftu,
467 sd_addr => sd_addr,
468 sd_addr_ftu => sd_addr_ftu,
469 config_start_cc => config_start_cc,
470 config_started_cc => config_started_cc,
471 config_ready_cc => config_ready_cc,
472 general_settings => general_settings,
473 lp_pt_freq => lp_pt_freq,
474 lp_pt_ratio => lp_pt_ratio,
475 lp1_amplitude => lp1_amplitude,
476 lp2_amplitude => lp2_amplitude,
477 lp1_delay => lp1_delay,
478 lp2_delay => lp2_delay,
479 coin_n_p => coin_n_p,
480 coin_n_c => coin_n_c,
481 trigger_delay => trigger_delay,
482 timemarker_delay => timemarker_delay,
483 dead_time => dead_time,
484 cc_R0 => cc_R0,
485 cc_R1 => cc_R1,
486 cc_R8 => cc_R8,
487 cc_R9 => cc_R9,
488 cc_R11 => cc_R11,
489 cc_R13 => cc_R13,
490 cc_R14 => cc_R14,
491 cc_R15 => cc_R15,
492 coin_win_p => coin_win_p,
493 coin_win_c => coin_win_c,
494 ftu_active_cr0 => ftu_active_cr0,
495 ftu_active_cr1 => ftu_active_cr1,
496 ftu_active_cr2 => ftu_active_cr2,
497 ftu_active_cr3 => ftu_active_cr3
498 );
499 U_9 : dd_write_general_modul
500 PORT MAP (
501 clk => clk,
502 dd_write_general => dd_write_general,
503 dd_write_general_started => dd_write_general_started,
504 dd_write_general_ready => dd_write_general_ready,
505 dd_busy => dd_busy_internal,
506 dd_write => dd_write,
507 dd_started => dd_started_general,
508 dd_ready => dd_ready_internal,
509 dd_addr => dd_addr1,
510 dd_data => dd_data
511 );
512 U_8 : dram_control
513 PORT MAP (
514 clk => clk,
515 dram_data_in => dram_data_in,
516 dram_data_out => doutb1,
517 dram_addr_in => dram_addr_in,
518 dram_addr_out => dram_addr_out,
519 dram_we => dram_we,
520 dd_block_start => dd_block_start,
521 dd_block_start_ftu => dd_block_start_ftu,
522 dd_block_start_ack => dd_block_start_ack,
523 dd_block_start_ack_ftu => dd_block_start_ack_ftu,
524 dd_block_ready => dd_block_ready,
525 dd_block_ready_ftu => dd_block_ready_ftu,
526 dd_read => dd_read,
527 dd_write_ftu => dd_write_ftu,
528 dd_write_general => dd_write,
529 dd_busy => dd_busy_internal,
530 dd_started => dd_started,
531 dd_started_ftu => dd_started_ftu,
532 dd_started_general => dd_started_general,
533 dd_ready => dd_ready_internal,
534 dd_data_out => dd_data_out,
535 dd_data_in_ftu => dd_data_in_ftu,
536 dd_data_in_general => dd_data,
537 dd_addr => dd_addr,
538 dd_addr_ftu => dd_addr_ftu,
539 dd_addr_general => dd_addr1
540 );
541 U_4 : eth_config_modul
542 PORT MAP (
543 clk => clk,
544 config_start_eth => config_start_eth,
545 config_started_eth => config_started_eth,
546 config_ready_eth => config_ready_eth,
547 config_start_cc => config_start_cc,
548 config_started_cc => config_started_cc,
549 config_ready_cc => config_ready_cc
550 );
551 U_6 : fram_control
552 PORT MAP (
553 clk => clk,
554 fram_data_in => fram_data_in,
555 fram_data_out => doutb,
556 fram_addr_in => fram_addr_in,
557 fram_addr_out => fram_addr_out,
558 fram_we => fram_we,
559 fl_read => fl_read,
560 fl_write_ftu => fl_write_ftu,
561 fl_busy => fl_busy_internal,
562 fl_started => fl_started,
563 fl_started_ftu => fl_started_ftu,
564 fl_ready => fl_ready_internal,
565 fl_data_out => fl_data_out,
566 fl_data_in_ftu => fl_data_in_ftu,
567 fl_addr => fl_addr,
568 fl_addr_ftu => fl_addr_ftu
569 );
570 U_10 : header_modul
571 PORT MAP (
572 clk => clk,
573 get_header => get_header,
574 get_header_started => get_header_started,
575 get_header_ready => get_header_ready,
576 header_board_id => header_board_id,
577 header_firmware_id => header_firmware_id,
578 header_trigger_counter => header_trigger_counter,
579 header_timestamp_counter => header_timestamp_counter
580 );
581 U_0 : w5300_modul
582 PORT MAP (
583 clk => clk,
584 wiz_reset => wiz_reset,
585 addr => wiz_addr,
586 data => wiz_data,
587 cs => wiz_cs,
588 wr => wiz_wr,
589 led => led1,
590 rd => wiz_rd,
591 int => wiz_int,
592 busy => busy,
593 new_config => new_config,
594 config_started => config_started,
595 config_started_ack => config_started_ack,
596 ping_ftu_start => ping_ftu_start,
597 ping_ftu_started => ping_ftu_started,
598 ping_ftu_ready => ping_ftu_ready,
599 sd_addr => sd_addr,
600 sd_data_out => sd_data_in,
601 sd_data_in => sd_data_out,
602 sd_write => sd_write,
603 sd_read => sd_read,
604 sd_started => sd_started,
605 sd_ready => sd_ready_internal,
606 sd_busy => sd_busy_internal,
607 dd_block_start => dd_block_start,
608 dd_block_start_ack => dd_block_start_ack,
609 dd_block_ready => dd_block_ready,
610 dd_send => dd_send,
611 dd_send_ack => dd_send_ack,
612 dd_send_ready => dd_send_ready,
613 dd_addr => dd_addr,
614 dd_data_in => dd_data_out,
615 dd_read => dd_read,
616 dd_started => dd_started,
617 dd_ready => dd_ready_internal,
618 dd_busy => dd_busy_internal,
619 dd_write_general => dd_write_general,
620 dd_write_general_started => dd_write_general_started,
621 dd_write_general_ready => dd_write_general_ready,
622 fl_addr => fl_addr,
623 fl_data_in => fl_data_out,
624 fl_read => fl_read,
625 fl_started => fl_started,
626 fl_ready => fl_ready_internal,
627 fl_busy => fl_busy_internal,
628 get_header => get_header,
629 get_header_started => get_header_started,
630 get_header_ready => get_header_ready,
631 header_board_id => header_board_id,
632 header_firmware_id => header_firmware_id,
633 header_trigger_counter => header_trigger_counter,
634 header_timestamp_counter => header_timestamp_counter
635 );
636
637 -- Implicit buffered output assignments
638 dd_busy <= dd_busy_internal;
639 dd_ready <= dd_ready_internal;
640 fl_busy <= fl_busy_internal;
641 fl_ready <= fl_ready_internal;
642 sd_busy <= sd_busy_internal;
643 sd_ready <= sd_ready_internal;
644
645END beha;
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