source: firmware/FTM/ethernet/ethernet_modul_beha.vhd@ 10639

Last change on this file since 10639 was 10441, checked in by weitzel, 15 years ago
new FTM firmware featuring e.g. start/stop run commands and new header
File size: 37.1 KB
Line 
1-- VHDL Entity FACT_FTM_lib.ethernet_modul.symbol
2--
3-- Created:
4-- by - kai.users (tpkw.local.priv)
5-- at - 11:20:56 04/20/11
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12
13library ftm_definitions;
14USE ftm_definitions.ftm_array_types.all;
15USE ftm_definitions.ftm_constants.all;
16
17ENTITY ethernet_modul IS
18 PORT(
19 wiz_reset : OUT std_logic := '1';
20 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
21 wiz_data : INOUT std_logic_vector (15 DOWNTO 0);
22 wiz_cs : OUT std_logic := '1';
23 wiz_wr : OUT std_logic := '1';
24 wiz_rd : OUT std_logic := '1';
25 wiz_int : IN std_logic;
26 clk : IN std_logic;
27 sd_ready : OUT std_logic;
28 sd_busy : OUT std_logic;
29 led : OUT std_logic_vector (7 DOWNTO 0);
30 sd_read_ftu : IN std_logic;
31 sd_started_ftu : OUT std_logic := '0';
32 cc_R0 : OUT std_logic_vector (31 DOWNTO 0);
33 cc_R1 : OUT std_logic_vector (31 DOWNTO 0);
34 cc_R11 : OUT std_logic_vector (31 DOWNTO 0);
35 cc_R13 : OUT std_logic_vector (31 DOWNTO 0);
36 cc_R14 : OUT std_logic_vector (31 DOWNTO 0);
37 cc_R15 : OUT std_logic_vector (31 DOWNTO 0);
38 cc_R8 : OUT std_logic_vector (31 DOWNTO 0);
39 cc_R9 : OUT std_logic_vector (31 DOWNTO 0);
40 coin_n_c : OUT std_logic_vector (15 DOWNTO 0);
41 coin_n_p : OUT std_logic_vector (15 DOWNTO 0);
42 dead_time : OUT std_logic_vector (15 DOWNTO 0);
43 -- data from config ram
44 general_settings : OUT std_logic_vector (15 DOWNTO 0);
45 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0);
46 lp1_delay : OUT std_logic_vector (15 DOWNTO 0);
47 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0);
48 lp2_delay : OUT std_logic_vector (15 DOWNTO 0);
49 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0);
50 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0);
51 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0);
52 trigger_delay : OUT std_logic_vector (15 DOWNTO 0);
53 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
54 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
55 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0);
56 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0);
57 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0);
58 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0);
59 new_config : OUT std_logic := '0';
60 config_started : IN std_logic;
61 config_start_eth : IN std_logic;
62 config_started_eth : OUT std_logic := '0';
63 config_ready_eth : OUT std_logic := '0';
64 config_started_ack : OUT std_logic := '0';
65 fl_busy : OUT std_logic;
66 fl_ready : OUT std_logic;
67 fl_write_ftu : IN std_logic;
68 fl_started_ftu : OUT std_logic := '0';
69 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
70 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0');
71 --
72 ping_ftu_start : OUT std_logic := '0';
73 ping_ftu_started : IN std_logic;
74 ping_ftu_ready : IN std_logic;
75 dd_write_ftu : IN std_logic;
76 dd_started_ftu : OUT std_logic := '0';
77 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
78 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
79 dd_busy : OUT std_logic;
80 dd_ready : OUT std_logic;
81 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
82 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
83 dd_block_ready_ftu : IN std_logic;
84 dd_block_start_ack_ftu : OUT std_logic := '0';
85 dd_block_start_ftu : IN std_logic;
86 dd_send : IN std_logic;
87 dd_send_ack : OUT std_logic := '1';
88 dd_send_ready : OUT std_logic := '1';
89 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
90 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
91 --
92 ftu_error_send : IN std_logic;
93 ftu_error_send_ack : OUT std_logic := '1';
94 ftu_error_send_ready : OUT std_logic := '1';
95 prescaling_FTU01 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
96 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0');
97 trigger_counter_read : OUT std_logic := '0';
98 trigger_counter_valid : IN std_logic;
99 board_id : IN std_logic_vector (63 DOWNTO 0);
100 get_ts_counter : OUT std_logic := '0';
101 get_ts_counter_ready : IN std_logic;
102 get_ts_counter_started : IN std_logic;
103 timestamp_counter : IN std_logic_vector (47 DOWNTO 0);
104 get_ot_counter : OUT std_logic := '0';
105 get_ot_counter_ready : IN std_logic;
106 get_ot_counter_started : IN std_logic;
107 on_time_counter : IN std_logic_vector (47 DOWNTO 0);
108 temp_sensor_array : IN sensor_array_type;
109 temp_sensor_ready : IN std_logic;
110 crate_reset : OUT std_logic := '0';
111 crate_reset_ack : IN std_logic;
112 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
113 --
114 start_run : OUT std_logic := '0';
115 start_run_ack : IN std_logic;
116 stop_run : OUT std_logic := '0';
117 stop_run_ack : IN std_logic;
118 current_cc_state : IN std_logic_vector (15 DOWNTO 0);
119 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
120 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0')
121 );
122
123END ethernet_modul ;
124
125ARCHITECTURE beha OF ethernet_modul IS
126
127 -- Architecture declarations
128
129 -- Internal signal declarations
130 SIGNAL busy : std_logic := '1';
131 SIGNAL cram_data_out : std_logic_vector(15 DOWNTO 0);
132 SIGNAL cram_data_in : std_logic_vector(15 DOWNTO 0);
133 SIGNAL cram_we : std_logic_vector(0 DOWNTO 0) := "0";
134 SIGNAL sd_write : std_logic := '0';
135 SIGNAL sd_read : std_logic;
136 SIGNAL led1 : std_logic_vector(7 DOWNTO 0) := (others => '0');
137 SIGNAL sd_started : std_logic;
138 SIGNAL sd_addr : std_logic_vector(11 DOWNTO 0);
139 SIGNAL cram_addr_out : std_logic_vector(11 DOWNTO 0);
140 SIGNAL cram_addr_in : std_logic_vector(11 DOWNTO 0);
141 SIGNAL sd_data_in : std_logic_vector(15 DOWNTO 0) := (others => '0');
142 SIGNAL sd_data_out : std_logic_vector(15 DOWNTO 0);
143 SIGNAL config_ready_cc : std_logic := '0';
144 SIGNAL config_started_cc : std_logic := '0';
145 SIGNAL config_start_cc : std_logic;
146 SIGNAL fl_started : std_logic;
147 SIGNAL fl_read : std_logic := '0';
148 --
149 SIGNAL fl_addr : std_logic_vector(11 DOWNTO 0);
150 SIGNAL fl_data_out : std_logic_vector(15 DOWNTO 0);
151 SIGNAL fram_addr_out : std_logic_vector(11 DOWNTO 0);
152 SIGNAL doutb : std_logic_VECTOR(15 DOWNTO 0);
153 SIGNAL fram_we : std_logic_vector(0 DOWNTO 0) := "0";
154 SIGNAL fram_addr_in : std_logic_vector(11 DOWNTO 0);
155 SIGNAL fram_data_in : std_logic_vector(15 DOWNTO 0);
156 SIGNAL dram_addr_out : std_logic_vector(11 DOWNTO 0);
157 SIGNAL doutb1 : std_logic_VECTOR(15 DOWNTO 0);
158 SIGNAL dram_we : std_logic_vector(0 DOWNTO 0) := "0";
159 SIGNAL dram_addr_in : std_logic_vector(11 DOWNTO 0);
160 SIGNAL dram_data_in : std_logic_vector(15 DOWNTO 0);
161 SIGNAL dd_read : std_logic;
162 SIGNAL dd_started : std_logic := '0';
163 SIGNAL dd_data_out : std_logic_vector(15 DOWNTO 0) := (others => '0');
164 SIGNAL dd_addr : std_logic_vector(11 DOWNTO 0);
165 SIGNAL dd_block_ready : std_logic := '0';
166 --
167 SIGNAL dd_block_start : std_logic := '0';
168 SIGNAL dd_block_start_ack : std_logic;
169 SIGNAL dd_write_general : std_logic := '0';
170 SIGNAL dd_write_general_ready : std_logic;
171 SIGNAL dd_write_general_started : std_logic;
172 SIGNAL dd_write : std_logic := '0';
173 SIGNAL dd_started_general : std_logic := '0';
174 SIGNAL dd_addr1 : std_logic_vector(11 DOWNTO 0) := (others => '0');
175 SIGNAL dd_data : std_logic_vector(15 DOWNTO 0) := (others => '0');
176 SIGNAL get_header : std_logic;
177 SIGNAL get_header_started : std_logic := '0';
178 SIGNAL get_header_ready : std_logic := '0';
179 SIGNAL led2 : std_logic_vector(7 DOWNTO 0);
180 SIGNAL header_board_id : std_logic_vector(63 DOWNTO 0);
181 SIGNAL header_firmware_id : std_logic_vector(15 DOWNTO 0);
182 SIGNAL header_timestamp_counter : std_logic_vector(47 DOWNTO 0);
183 SIGNAL header_trigger_counter : std_logic_vector(31 DOWNTO 0);
184 SIGNAL header_current_state : std_logic_vector(15 DOWNTO 0) := (others => '0');
185
186 -- Implicit buffer signal declarations
187 SIGNAL dd_busy_internal : std_logic;
188 SIGNAL dd_ready_internal : std_logic;
189 SIGNAL fl_busy_internal : std_logic;
190 SIGNAL fl_ready_internal : std_logic;
191 SIGNAL sd_busy_internal : std_logic;
192 SIGNAL sd_ready_internal : std_logic;
193
194
195 -- Component Declarations
196 COMPONENT CRAM_4096_16b
197 PORT (
198 clka : IN std_logic ;
199 dina : IN std_logic_VECTOR (15 DOWNTO 0);
200 addra : IN std_logic_VECTOR (11 DOWNTO 0);
201 wea : IN std_logic_VECTOR (0 DOWNTO 0);
202 clkb : IN std_logic ;
203 addrb : IN std_logic_VECTOR (11 DOWNTO 0);
204 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
205 );
206 END COMPONENT;
207 COMPONENT DRAM_4096_16b
208 PORT (
209 clka : IN std_logic ;
210 dina : IN std_logic_VECTOR (15 DOWNTO 0);
211 addra : IN std_logic_VECTOR (11 DOWNTO 0);
212 wea : IN std_logic_VECTOR (0 DOWNTO 0);
213 clkb : IN std_logic ;
214 addrb : IN std_logic_VECTOR (11 DOWNTO 0);
215 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
216 );
217 END COMPONENT;
218 COMPONENT FRAM_4096_16b
219 PORT (
220 clka : IN std_logic ;
221 dina : IN std_logic_VECTOR (15 DOWNTO 0);
222 addra : IN std_logic_VECTOR (11 DOWNTO 0);
223 wea : IN std_logic_VECTOR (0 DOWNTO 0);
224 clkb : IN std_logic ;
225 addrb : IN std_logic_VECTOR (11 DOWNTO 0);
226 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
227 );
228 END COMPONENT;
229 COMPONENT cram_control
230 PORT (
231 clk : IN std_logic ;
232 led : OUT std_logic_vector (7 DOWNTO 0) := X"00";
233 cram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
234 cram_data_out : IN std_logic_vector (15 DOWNTO 0);
235 cram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
236 cram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
237 cram_we : OUT std_logic_vector (0 DOWNTO 0) := "0";
238 sd_write : IN std_logic ;
239 sd_read : IN std_logic ;
240 sd_read_ftu : IN std_logic ;
241 sd_busy : OUT std_logic := '1';
242 sd_started : OUT std_logic := '0';
243 sd_started_ftu : OUT std_logic := '0';
244 sd_ready : OUT std_logic := '0';
245 sd_data_in : IN std_logic_vector (15 DOWNTO 0);
246 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
247 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
248 sd_addr : IN std_logic_vector (11 DOWNTO 0);
249 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
250 config_start_cc : IN std_logic ;
251 config_started_cc : OUT std_logic := '0';
252 config_ready_cc : OUT std_logic := '0';
253 -- data from config ram
254 general_settings : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
255 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
256 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
257 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
258 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
259 lp1_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
260 lp2_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
261 coin_n_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
262 coin_n_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
263 trigger_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
264 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
265 dead_time : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
266 cc_R0 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
267 cc_R1 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
268 cc_R8 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
269 cc_R9 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
270 cc_R11 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
271 cc_R13 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
272 cc_R14 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
273 cc_R15 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
274 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
275 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
276 prescaling_FTU01 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
277 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
278 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
279 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
280 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
281 );
282 END COMPONENT;
283 COMPONENT dd_write_general_modul
284 PORT (
285 clk : IN std_logic ;
286 dd_write_general : IN std_logic ;
287 dd_write_general_started : OUT std_logic := '0';
288 dd_write_general_ready : OUT std_logic := '0';
289 dd_busy : IN std_logic ;
290 dd_write : OUT std_logic := '0';
291 dd_started : IN std_logic ;
292 dd_ready : IN std_logic ;
293 dd_addr : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
294 dd_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
295 get_ot_counter : OUT std_logic := '0';
296 get_ot_counter_started : IN std_logic ;
297 get_ot_counter_ready : IN std_logic ;
298 on_time_counter : IN std_logic_vector (47 DOWNTO 0);
299 temp_sensor_ready : IN std_logic ;
300 temp_sensor_array : IN sensor_array_type
301 );
302 END COMPONENT;
303 COMPONENT dram_control
304 PORT (
305 clk : IN std_logic ;
306 dram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
307 dram_data_out : IN std_logic_vector (15 DOWNTO 0);
308 dram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
309 dram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
310 dram_we : OUT std_logic_vector (0 DOWNTO 0) := "0";
311 dd_block_start : IN std_logic ;
312 dd_block_start_ftu : IN std_logic ;
313 dd_block_start_ack : OUT std_logic := '0';
314 dd_block_start_ack_ftu : OUT std_logic := '0';
315 dd_block_ready : IN std_logic ;
316 dd_block_ready_ftu : IN std_logic ;
317 dd_read : IN std_logic ;
318 dd_write_ftu : IN std_logic ;
319 dd_write_general : IN std_logic ;
320 dd_busy : OUT std_logic := '1';
321 dd_started : OUT std_logic := '0';
322 dd_started_ftu : OUT std_logic := '0';
323 dd_started_general : OUT std_logic := '0';
324 dd_ready : OUT std_logic := '0';
325 dd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
326 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
327 dd_data_in_general : IN std_logic_vector (15 DOWNTO 0);
328 dd_addr : IN std_logic_vector (11 DOWNTO 0);
329 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
330 dd_addr_general : IN std_logic_vector (11 DOWNTO 0)
331 );
332 END COMPONENT;
333 COMPONENT eth_config_modul
334 PORT (
335 clk : IN std_logic ;
336 config_start_eth : IN std_logic ;
337 config_started_eth : OUT std_logic := '0';
338 config_ready_eth : OUT std_logic := '0';
339 config_start_cc : OUT std_logic := '0';
340 config_started_cc : IN std_logic ;
341 config_ready_cc : IN std_logic
342 );
343 END COMPONENT;
344 COMPONENT fram_control
345 PORT (
346 clk : IN std_logic ;
347 fram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
348 fram_data_out : IN std_logic_vector (15 DOWNTO 0);
349 fram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
350 fram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
351 fram_we : OUT std_logic_vector (0 DOWNTO 0) := "0";
352 fl_read : IN std_logic ;
353 fl_write_ftu : IN std_logic ;
354 fl_busy : OUT std_logic := '1';
355 fl_started : OUT std_logic := '0';
356 fl_started_ftu : OUT std_logic := '0';
357 fl_ready : OUT std_logic := '0';
358 fl_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
359 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
360 fl_addr : IN std_logic_vector (11 DOWNTO 0);
361 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0)
362 );
363 END COMPONENT;
364 COMPONENT header_modul
365 PORT (
366 clk : IN std_logic ;
367 get_header : IN std_logic ;
368 get_header_started : OUT std_logic := '0';
369 get_header_ready : OUT std_logic := '0';
370 board_id : IN std_logic_vector (63 DOWNTO 0);
371 trigger_counter_read : OUT std_logic := '0';
372 trigger_counter_valid : IN std_logic ;
373 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0');
374 get_ts_counter : OUT std_logic := '0';
375 get_ts_counter_started : IN std_logic ;
376 get_ts_counter_ready : IN std_logic ;
377 timestamp_counter : IN std_logic_vector (47 DOWNTO 0);
378 header_board_id : OUT std_logic_vector (63 DOWNTO 0) := (others => '0');
379 header_firmware_id : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
380 header_trigger_counter : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
381 header_timestamp_counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0');
382 header_current_state : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
383 current_cc_state : IN std_logic_vector (15 DOWNTO 0)
384 );
385 END COMPONENT;
386 COMPONENT w5300_modul
387 PORT (
388 clk : IN std_logic ;
389 wiz_reset : OUT std_logic := '1';
390 addr : OUT std_logic_vector (9 DOWNTO 0);
391 data : INOUT std_logic_vector (15 DOWNTO 0);
392 cs : OUT std_logic := '1';
393 wr : OUT std_logic := '1';
394 led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
395 rd : OUT std_logic := '1';
396 int : IN std_logic ;
397 busy : OUT std_logic := '1';
398 new_config : OUT std_logic := '0';
399 config_started : IN std_logic ;
400 config_started_ack : OUT std_logic := '0';
401 --
402 ping_ftu_start : OUT std_logic := '0';
403 ping_ftu_started : IN std_logic ;
404 ping_ftu_ready : IN std_logic ;
405 --
406 sd_addr : OUT std_logic_vector (11 DOWNTO 0);
407 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
408 sd_data_in : IN std_logic_vector (15 DOWNTO 0);
409 sd_write : OUT std_logic := '0';
410 sd_read : OUT std_logic := '0';
411 sd_started : IN std_logic ;
412 sd_ready : IN std_logic ;
413 sd_busy : IN std_logic ;
414 --
415 dd_block_start : OUT std_logic := '0';
416 dd_block_start_ack : IN std_logic ;
417 dd_block_ready : OUT std_logic := '1';
418 dd_send : IN std_logic ;
419 dd_send_ack : OUT std_logic := '1';
420 dd_send_ready : OUT std_logic := '1';
421 dd_addr : OUT std_logic_vector (11 DOWNTO 0);
422 dd_data_in : IN std_logic_vector (15 DOWNTO 0);
423 dd_read : OUT std_logic := '0';
424 dd_started : IN std_logic ;
425 dd_ready : IN std_logic ;
426 dd_busy : IN std_logic ;
427 dd_write_general : OUT std_logic := '0';
428 dd_write_general_started : IN std_logic ;
429 dd_write_general_ready : IN std_logic ;
430 --
431 fl_addr : OUT std_logic_vector (11 DOWNTO 0);
432 fl_data_in : IN std_logic_vector (15 DOWNTO 0);
433 fl_read : OUT std_logic := '0';
434 fl_started : IN std_logic ;
435 fl_ready : IN std_logic ;
436 fl_busy : IN std_logic ;
437 --
438 ftu_error_send : IN std_logic ;
439 ftu_error_send_ack : OUT std_logic := '1';
440 ftu_error_send_ready : OUT std_logic := '1';
441 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
442 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
443 --
444 get_header : OUT std_logic := '0';
445 get_header_started : IN std_logic ;
446 get_header_ready : IN std_logic ;
447 header_board_id : IN std_logic_vector (63 DOWNTO 0);
448 header_firmware_id : IN std_logic_vector (15 DOWNTO 0);
449 header_trigger_counter : IN std_logic_vector (31 DOWNTO 0);
450 header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0);
451 header_current_state : IN std_logic_vector (15 DOWNTO 0);
452 --
453 start_run : OUT std_logic := '0';
454 start_run_ack : IN std_logic ;
455 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
456 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
457 stop_run : OUT std_logic := '0';
458 stop_run_ack : IN std_logic ;
459 crate_reset : OUT std_logic := '0';
460 crate_reset_ack : IN std_logic ;
461 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
462 );
463 END COMPONENT;
464
465BEGIN
466
467 -- ModuleWare code(v1.9) for instance 'U_3' of 'or'
468 led <= led1 OR led2;
469
470 -- Instance port mappings.
471 U_1 : CRAM_4096_16b
472 PORT MAP (
473 clka => clk,
474 dina => cram_data_in,
475 addra => cram_addr_in,
476 wea => cram_we,
477 clkb => clk,
478 addrb => cram_addr_out,
479 doutb => cram_data_out
480 );
481 U_7 : DRAM_4096_16b
482 PORT MAP (
483 clka => clk,
484 dina => dram_data_in,
485 addra => dram_addr_in,
486 wea => dram_we,
487 clkb => clk,
488 addrb => dram_addr_out,
489 doutb => doutb1
490 );
491 U_5 : FRAM_4096_16b
492 PORT MAP (
493 clka => clk,
494 dina => fram_data_in,
495 addra => fram_addr_in,
496 wea => fram_we,
497 clkb => clk,
498 addrb => fram_addr_out,
499 doutb => doutb
500 );
501 U_2 : cram_control
502 PORT MAP (
503 clk => clk,
504 led => led2,
505 cram_data_in => cram_data_in,
506 cram_data_out => cram_data_out,
507 cram_addr_in => cram_addr_in,
508 cram_addr_out => cram_addr_out,
509 cram_we => cram_we,
510 sd_write => sd_write,
511 sd_read => sd_read,
512 sd_read_ftu => sd_read_ftu,
513 sd_busy => sd_busy_internal,
514 sd_started => sd_started,
515 sd_started_ftu => sd_started_ftu,
516 sd_ready => sd_ready_internal,
517 sd_data_in => sd_data_in,
518 sd_data_out => sd_data_out,
519 sd_data_out_ftu => sd_data_out_ftu,
520 sd_addr => sd_addr,
521 sd_addr_ftu => sd_addr_ftu,
522 config_start_cc => config_start_cc,
523 config_started_cc => config_started_cc,
524 config_ready_cc => config_ready_cc,
525 general_settings => general_settings,
526 lp_pt_freq => lp_pt_freq,
527 lp_pt_ratio => lp_pt_ratio,
528 lp1_amplitude => lp1_amplitude,
529 lp2_amplitude => lp2_amplitude,
530 lp1_delay => lp1_delay,
531 lp2_delay => lp2_delay,
532 coin_n_p => coin_n_p,
533 coin_n_c => coin_n_c,
534 trigger_delay => trigger_delay,
535 timemarker_delay => timemarker_delay,
536 dead_time => dead_time,
537 cc_R0 => cc_R0,
538 cc_R1 => cc_R1,
539 cc_R8 => cc_R8,
540 cc_R9 => cc_R9,
541 cc_R11 => cc_R11,
542 cc_R13 => cc_R13,
543 cc_R14 => cc_R14,
544 cc_R15 => cc_R15,
545 coin_win_p => coin_win_p,
546 coin_win_c => coin_win_c,
547 prescaling_FTU01 => prescaling_FTU01,
548 ftu_active_cr0 => ftu_active_cr0,
549 ftu_active_cr1 => ftu_active_cr1,
550 ftu_active_cr2 => ftu_active_cr2,
551 ftu_active_cr3 => ftu_active_cr3
552 );
553 U_9 : dd_write_general_modul
554 PORT MAP (
555 clk => clk,
556 dd_write_general => dd_write_general,
557 dd_write_general_started => dd_write_general_started,
558 dd_write_general_ready => dd_write_general_ready,
559 dd_busy => dd_busy_internal,
560 dd_write => dd_write,
561 dd_started => dd_started_general,
562 dd_ready => dd_ready_internal,
563 dd_addr => dd_addr1,
564 dd_data => dd_data,
565 get_ot_counter => get_ot_counter,
566 get_ot_counter_started => get_ot_counter_started,
567 get_ot_counter_ready => get_ot_counter_ready,
568 on_time_counter => on_time_counter,
569 temp_sensor_ready => temp_sensor_ready,
570 temp_sensor_array => temp_sensor_array
571 );
572 U_8 : dram_control
573 PORT MAP (
574 clk => clk,
575 dram_data_in => dram_data_in,
576 dram_data_out => doutb1,
577 dram_addr_in => dram_addr_in,
578 dram_addr_out => dram_addr_out,
579 dram_we => dram_we,
580 dd_block_start => dd_block_start,
581 dd_block_start_ftu => dd_block_start_ftu,
582 dd_block_start_ack => dd_block_start_ack,
583 dd_block_start_ack_ftu => dd_block_start_ack_ftu,
584 dd_block_ready => dd_block_ready,
585 dd_block_ready_ftu => dd_block_ready_ftu,
586 dd_read => dd_read,
587 dd_write_ftu => dd_write_ftu,
588 dd_write_general => dd_write,
589 dd_busy => dd_busy_internal,
590 dd_started => dd_started,
591 dd_started_ftu => dd_started_ftu,
592 dd_started_general => dd_started_general,
593 dd_ready => dd_ready_internal,
594 dd_data_out => dd_data_out,
595 dd_data_in_ftu => dd_data_in_ftu,
596 dd_data_in_general => dd_data,
597 dd_addr => dd_addr,
598 dd_addr_ftu => dd_addr_ftu,
599 dd_addr_general => dd_addr1
600 );
601 U_4 : eth_config_modul
602 PORT MAP (
603 clk => clk,
604 config_start_eth => config_start_eth,
605 config_started_eth => config_started_eth,
606 config_ready_eth => config_ready_eth,
607 config_start_cc => config_start_cc,
608 config_started_cc => config_started_cc,
609 config_ready_cc => config_ready_cc
610 );
611 U_6 : fram_control
612 PORT MAP (
613 clk => clk,
614 fram_data_in => fram_data_in,
615 fram_data_out => doutb,
616 fram_addr_in => fram_addr_in,
617 fram_addr_out => fram_addr_out,
618 fram_we => fram_we,
619 fl_read => fl_read,
620 fl_write_ftu => fl_write_ftu,
621 fl_busy => fl_busy_internal,
622 fl_started => fl_started,
623 fl_started_ftu => fl_started_ftu,
624 fl_ready => fl_ready_internal,
625 fl_data_out => fl_data_out,
626 fl_data_in_ftu => fl_data_in_ftu,
627 fl_addr => fl_addr,
628 fl_addr_ftu => fl_addr_ftu
629 );
630 U_10 : header_modul
631 PORT MAP (
632 clk => clk,
633 get_header => get_header,
634 get_header_started => get_header_started,
635 get_header_ready => get_header_ready,
636 board_id => board_id,
637 trigger_counter_read => trigger_counter_read,
638 trigger_counter_valid => trigger_counter_valid,
639 trigger_counter => trigger_counter,
640 get_ts_counter => get_ts_counter,
641 get_ts_counter_started => get_ts_counter_started,
642 get_ts_counter_ready => get_ts_counter_ready,
643 timestamp_counter => timestamp_counter,
644 header_board_id => header_board_id,
645 header_firmware_id => header_firmware_id,
646 header_trigger_counter => header_trigger_counter,
647 header_timestamp_counter => header_timestamp_counter,
648 header_current_state => header_current_state,
649 current_cc_state => current_cc_state
650 );
651 U_0 : w5300_modul
652 PORT MAP (
653 clk => clk,
654 wiz_reset => wiz_reset,
655 addr => wiz_addr,
656 data => wiz_data,
657 cs => wiz_cs,
658 wr => wiz_wr,
659 led => led1,
660 rd => wiz_rd,
661 int => wiz_int,
662 busy => busy,
663 new_config => new_config,
664 config_started => config_started,
665 config_started_ack => config_started_ack,
666 ping_ftu_start => ping_ftu_start,
667 ping_ftu_started => ping_ftu_started,
668 ping_ftu_ready => ping_ftu_ready,
669 sd_addr => sd_addr,
670 sd_data_out => sd_data_in,
671 sd_data_in => sd_data_out,
672 sd_write => sd_write,
673 sd_read => sd_read,
674 sd_started => sd_started,
675 sd_ready => sd_ready_internal,
676 sd_busy => sd_busy_internal,
677 dd_block_start => dd_block_start,
678 dd_block_start_ack => dd_block_start_ack,
679 dd_block_ready => dd_block_ready,
680 dd_send => dd_send,
681 dd_send_ack => dd_send_ack,
682 dd_send_ready => dd_send_ready,
683 dd_addr => dd_addr,
684 dd_data_in => dd_data_out,
685 dd_read => dd_read,
686 dd_started => dd_started,
687 dd_ready => dd_ready_internal,
688 dd_busy => dd_busy_internal,
689 dd_write_general => dd_write_general,
690 dd_write_general_started => dd_write_general_started,
691 dd_write_general_ready => dd_write_general_ready,
692 fl_addr => fl_addr,
693 fl_data_in => fl_data_out,
694 fl_read => fl_read,
695 fl_started => fl_started,
696 fl_ready => fl_ready_internal,
697 fl_busy => fl_busy_internal,
698 ftu_error_send => ftu_error_send,
699 ftu_error_send_ack => ftu_error_send_ack,
700 ftu_error_send_ready => ftu_error_send_ready,
701 ftu_error_calls => ftu_error_calls,
702 ftu_error_data => ftu_error_data,
703 get_header => get_header,
704 get_header_started => get_header_started,
705 get_header_ready => get_header_ready,
706 header_board_id => header_board_id,
707 header_firmware_id => header_firmware_id,
708 header_trigger_counter => header_trigger_counter,
709 header_timestamp_counter => header_timestamp_counter,
710 header_current_state => header_current_state,
711 start_run => start_run,
712 start_run_ack => start_run_ack,
713 start_run_param => start_run_param,
714 start_run_num_events => start_run_num_events,
715 stop_run => stop_run,
716 stop_run_ack => stop_run_ack,
717 crate_reset => crate_reset,
718 crate_reset_ack => crate_reset_ack,
719 crate_reset_param => crate_reset_param
720 );
721
722 -- Implicit buffered output assignments
723 dd_busy <= dd_busy_internal;
724 dd_ready <= dd_ready_internal;
725 fl_busy <= fl_busy_internal;
726 fl_ready <= fl_ready_internal;
727 sd_busy <= sd_busy_internal;
728 sd_ready <= sd_ready_internal;
729
730END beha;
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