source: firmware/FTM/ethernet/w5300_modul.vhd@ 10697

Last change on this file since 10697 was 10639, checked in by weitzel, 14 years ago
FTM: keep-alive of Wiznet actiated, clock conditioner interface updated, trigger ID sending updated
File size: 50.8 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 11:48:48 11/10/2009
6-- Design Name:
7-- Module Name: w5300_modul - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21LIBRARY IEEE;
22USE IEEE.STD_LOGIC_1164.all;
23USE IEEE.STD_LOGIC_ARITH.all;
24USE IEEE.STD_LOGIC_UNSIGNED.all;
25
26library ftm_definitions;
27USE ftm_definitions.ftm_array_types.all;
28USE ftm_definitions.ftm_constants.all;
29
30-- Uncomment the following library declaration if instantiating
31-- any Xilinx primitives in this code.
32library UNISIM;
33use UNISIM.VComponents.all;
34
35ENTITY w5300_modul IS
36 PORT(
37 clk : IN std_logic;
38 wiz_reset : OUT std_logic := '1';
39 addr : OUT std_logic_vector (9 DOWNTO 0);
40 data : INOUT std_logic_vector (15 DOWNTO 0);
41 cs : OUT std_logic := '1';
42 wr : OUT std_logic := '1';
43 led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
44 rd : OUT std_logic := '1';
45 int : IN std_logic;
46 busy : OUT std_logic := '1';
47 new_config : OUT std_logic := '0';
48 config_started : IN std_logic;
49 config_started_ack : OUT std_logic := '0';
50 --
51 ping_ftu_start : OUT std_logic := '0';
52 ping_ftu_started : IN std_logic;
53 ping_ftu_ready : IN std_logic;
54 --
55 sd_addr : OUT std_logic_vector (11 DOWNTO 0);
56 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
57 sd_data_in : IN std_logic_vector (15 DOWNTO 0);
58 sd_write : OUT std_logic := '0';
59 sd_read : OUT std_logic := '0';
60 sd_started : IN std_logic;
61 sd_ready : IN std_logic;
62 sd_busy : IN std_logic;
63 --
64 dd_block_start : OUT std_logic := '0';
65 dd_block_start_ack : IN std_logic;
66 dd_block_ready : OUT std_logic := '1';
67 dd_send : IN std_logic;
68 dd_send_ack : OUT std_logic := '1';
69 dd_send_ready : OUT std_logic := '1';
70 dd_addr : OUT std_logic_vector (11 DOWNTO 0);
71 dd_data_in : IN std_logic_vector (15 DOWNTO 0);
72 dd_read : OUT std_logic := '0';
73 dd_started : IN std_logic;
74 dd_ready : IN std_logic;
75 dd_busy : IN std_logic;
76 dd_write_general : OUT std_logic := '0';
77 dd_write_general_started : IN std_logic;
78 dd_write_general_ready : IN std_logic;
79 --
80 fl_addr : OUT std_logic_vector (11 DOWNTO 0);
81 fl_data_in : IN std_logic_vector (15 DOWNTO 0);
82 fl_read : OUT std_logic := '0';
83 fl_started : IN std_logic;
84 fl_ready : IN std_logic;
85 fl_busy : IN std_logic;
86 --
87 ftu_error_send : IN std_logic;
88 ftu_error_send_ack : OUT std_logic := '1';
89 ftu_error_send_ready : OUT std_logic := '1';
90 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
91 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
92 --
93 get_header : OUT std_logic := '0';
94 get_header_started : IN std_logic;
95 get_header_ready : IN std_logic;
96 header_board_id : IN std_logic_vector (63 DOWNTO 0);
97 header_firmware_id : IN std_logic_vector (15 DOWNTO 0);
98 header_trigger_counter : IN std_logic_vector (31 DOWNTO 0);
99 header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0);
100 header_current_state : IN std_logic_vector (15 DOWNTO 0);
101 --
102 start_run : OUT std_logic := '0';
103 start_run_ack : IN std_logic;
104 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
105 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
106 stop_run : OUT std_logic := '0';
107 stop_run_ack : IN std_logic;
108 crate_reset : OUT std_logic := '0';
109 crate_reset_ack : IN std_logic;
110 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
111 );
112
113END w5300_modul ;
114
115architecture Behavioral of w5300_modul is
116
117 type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
118 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
119 SI, SI0, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR,
120 READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL);
121 type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08,
122 WR_WRITE_START_DEL, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_SD_ADDR, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01, WR_WRITE_END_DEL);
123 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
124 type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
125 type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_CMD, RD_CMD_PARSE, RD_PING, RD_WRITE_SD_ADDR, RD_READ_SD_ADDR, RD_READ_SD_BLOCK, RD_READ_DD_BLOCK, RD_WRITE_SD_BLOCK, RD_X_EVNTS,RD_END);
126 type state_write_sd_type is (WRITE_SD_START, WRITE_SD_WAIT, WRITE_SD_END);
127 type state_read_sd_type is (READ_SD_START, READ_SD_WAIT, READ_SD_END);
128 type state_read_fl_type is (READ_FL_START, READ_FL_WAIT, READ_FL_END);
129 type state_ping_type is (PING_START, PING_WAIT, PING_WRITE_LIST);
130 type state_read_dd_type is (READ_DD_START, READ_DD_WAIT, READ_DD_END);
131 type state_read_dd_block_type is (READ_DD_BLOCK_START, READ_DD_BLOCK_WRITE_GENERAL, READ_DD_BLOCK_WRITE, READ_DD_BLOCK_END, READ_DD_BLOCK_INTERN);
132 type state_send_ftu_error_type is (SFE_START, SFE_END);
133
134 signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
135
136 signal par_addr : std_logic_vector (9 downto 0) := (others => '0');
137 signal par_data : std_logic_vector (15 downto 0) := (others => '0');
138 signal data_read : std_logic_vector (15 downto 0) := (others => '0');
139
140 signal state_init, next_state , next_state_tmp : state_init_type := RESET;
141 signal read_addr_state : state_init_type := RESET;
142 signal count : std_logic_vector (2 downto 0) := "000";
143 signal state_write : state_write_type := WR_START;
144 signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
145 signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
146 signal state_read_data : state_read_data_type := RD_1;
147 signal next_state_read_data : state_read_data_type := RD_CMD;
148 signal state_write_sd : state_write_sd_type := WRITE_SD_START;
149 signal state_read_sd : state_read_sd_type := READ_SD_START;
150 signal state_read_fl : state_read_fl_type := READ_FL_START;
151 signal state_ping : state_ping_type := PING_START;
152 signal state_read_dd : state_read_dd_type := READ_DD_START;
153 signal state_read_dd_block : state_read_dd_block_type := READ_DD_BLOCK_START;
154 signal state_send_ftu_error : state_send_ftu_error_type := SFE_START;
155
156
157 signal interrupt_ignore : std_logic := '1';
158 signal int_flag : std_logic := '0';
159
160 signal zaehler : std_logic_vector (19 downto 0) := (others => '0');
161 signal data_cnt : integer := 0;
162 signal header_cnt : std_logic_vector (7 DOWNTO 0) := X"00";
163 signal socket_cnt : std_logic_vector (2 downto 0) := "000";
164
165 signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
166 signal write_length_bytes : std_logic_vector (16 downto 0);
167
168 signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
169 signal chk_recv_cntr : integer range 0 to 10000 := 0;
170
171 signal next_packet_data_cnt : integer range 0 to 4095 := 0;
172 signal rx_packets_cnt : std_logic_vector (15 downto 0) := X"0000";
173 signal new_config_flag : std_logic := '0';
174
175 signal local_write_length : std_logic_vector (16 downto 0);
176 signal local_socket_nr : std_logic_vector (2 downto 0);
177
178 type cmd_array_type is array (0 to 4) of std_logic_vector (15 downto 0);
179 signal cmd_array : cmd_array_type;
180 signal internal_cmd : std_logic := '0';
181 signal wait_for_data_flag : std_logic := '0';
182
183 signal autosend_flag : std_logic := '1';
184
185 -- -- --
186 signal led_int : std_logic_vector (7 downto 0) := X"00";
187 signal led_cnt : integer range 0 to 2**22 := 0;
188 -- -- --
189
190 signal local_sd_addr : std_logic_vector (11 downto 0);
191 signal local_sd_data : std_logic_vector (15 downto 0);
192
193 signal data_package_type : std_logic_vector (15 downto 0) := X"0000";
194 signal data_package_length : std_logic_vector (15 downto 0) := X"0000";
195
196
197begin
198
199 --synthesis translate_off
200 RST_TIME <= X"00120";
201 --synthesis translate_on
202
203
204 w5300_init_proc : process (clk, int)
205 begin
206
207 if rising_edge (clk) then
208
209 -- -- --
210 led <= led_int;
211 -- -- --
212
213 -- Interrupt low
214 if (int = '0') and (interrupt_ignore = '0') then
215 case state_interrupt_1 is
216 when IR1_01 =>
217 int_flag <= '1';
218 busy <= '1';
219 state_interrupt_1 <= IR1_02;
220 when IR1_02 =>
221 state_interrupt_1 <= IR1_03;
222 when IR1_03 =>
223 state_init <= INTERRUPT;
224 socket_cnt <= "000";
225 zaehler <= X"00000";
226 count <= "000";
227 int_flag <= '0';
228 interrupt_ignore <= '1';
229 state_interrupt_1 <= IR1_04;
230 when others =>
231 null;
232 end case;
233 end if; -- int = '0'
234
235 if int_flag = '0' then
236 case state_init is
237 -- Interrupt
238 when INTERRUPT =>
239 case state_interrupt_2 is
240 when IR2_01 =>
241 par_addr <= W5300_IR;
242 state_init <= READ_REG;
243 next_state <= INTERRUPT;
244 state_interrupt_2 <= IR2_02;
245 when IR2_02 =>
246 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
247 state_interrupt_2 <= IR2_03;
248 else
249 socket_cnt <= socket_cnt + 1;
250 if (socket_cnt = W5300_LAST_SOCKET) then
251 state_interrupt_2 <= IR2_06;
252 else
253 state_interrupt_2 <= IR2_02;
254 end if;
255 end if;
256 when IR2_03 =>
257 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
258 state_init <= READ_REG;
259 next_state <= INTERRUPT;
260 state_interrupt_2 <= IR2_04;
261 when IR2_04 =>
262 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
263 par_data <= data_read; -- clear Interrupts
264 state_init <= WRITE_REG;
265 next_state <= INTERRUPT;
266 state_interrupt_2 <= IR2_05;
267 when IR2_05 =>
268 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
269 par_data <= X"0010"; -- CLOSE
270 state_init <= WRITE_REG;
271 next_state <= INTERRUPT;
272 socket_cnt <= socket_cnt + 1;
273 if (socket_cnt = W5300_LAST_SOCKET) then
274 state_interrupt_2 <= IR2_06;
275 else
276 state_interrupt_2 <= IR2_01;
277 end if;
278
279 when IR2_06 =>
280 state_interrupt_1 <= IR1_01;
281 state_interrupt_2 <= IR2_01;
282 socket_cnt <= "000";
283 state_init <= RESET;
284 end case;
285
286 -- reset W5300
287 when RESET =>
288 busy <= '1';
289 zaehler <= zaehler + 1;
290 wiz_reset <= '0';
291 if (zaehler >= X"00064") then -- wait 2µs
292 wiz_reset <= '1';
293 end if;
294 if (zaehler = RST_TIME) then -- wait 10ms
295 zaehler <= X"00000";
296 socket_cnt <= "000";
297 count <= "000";
298 interrupt_ignore <= '0';
299 rd <= '1';
300 wr <= '1';
301 cs <= '1';
302 -- reset states
303 state_write <= WR_START;
304 state_init <= INIT;
305 state_read_data <= RD_1;
306 next_state_read_data <= RD_CMD;
307 state_write_sd <= WRITE_SD_START;
308 state_read_sd <= READ_SD_START;
309 state_read_fl <= READ_FL_START;
310 state_ping <= PING_START;
311 state_read_dd <= READ_DD_START;
312 state_read_dd_block <= READ_DD_BLOCK_START;
313 state_send_ftu_error <= SFE_START;
314 -- reset output signals
315 new_config <= '0';
316 config_started_ack <= '1';
317 ping_ftu_start <= '0';
318 sd_write <= '0';
319 sd_read <= '0';
320 dd_block_start <= '0';
321 dd_block_ready <= '1';
322 dd_send_ack <= '1';
323 dd_send_ready <= '1';
324 dd_read <= '0';
325 dd_write_general <= '0';
326 fl_read <= '0';
327 ftu_error_send_ack <= '1';
328 ftu_error_send_ready <= '1';
329 -- set internal signals
330 new_config_flag <= '0';
331 chk_recv_cntr <= 0;
332 next_packet_data_cnt <= 0;
333 internal_cmd <= '0';
334 -- -- --
335 led_int <= X"00";
336 -- -- --
337 end if;
338
339 -- Init
340 when INIT =>
341 par_addr <= W5300_MR;
342 par_data <= X"0000";
343 state_init <= WRITE_REG;
344 next_state <= IM;
345
346 -- Interrupt Mask
347 when IM =>
348 par_addr <= W5300_IMR;
349 par_data <= X"00FF"; -- S0-S7 Interrupts
350 state_init <= WRITE_REG;
351 next_state <= MT;
352
353 -- Memory Type
354 when MT =>
355 par_addr <= W5300_MTYPER;
356 par_data <= X"00FF"; -- 64K RX, 64K TX-Buffer
357 state_init <= WRITE_REG;
358 next_state <= STX;
359
360 -- Socket TX Memory Size
361 when STX =>
362 par_data <= X"4000"; -- 64K TX for socket 0, others 0
363
364 par_addr <= W5300_TMS01R;
365 state_init <= WRITE_REG;
366 next_state <= STX1;
367 when STX1 =>
368 par_data <= X"0000";
369 par_addr <= W5300_TMS23R;
370 state_init <= WRITE_REG;
371 next_state <= STX2;
372 when STX2 =>
373 par_addr <= W5300_TMS45R;
374 state_init <= WRITE_REG;
375 next_state <= STX3;
376 when STX3 =>
377 par_addr <= W5300_TMS67R;
378 state_init <= WRITE_REG;
379 next_state <= SRX;
380
381 -- Socket RX Memory Size
382 when SRX =>
383 par_data <= X"4000"; -- 64K RX for socket 0, others 0
384
385 par_addr <= W5300_RMS01R;
386 state_init <= WRITE_REG;
387 next_state <= SRX1;
388 when SRX1 =>
389 par_data <= X"0000";
390 par_addr <= W5300_RMS23R;
391 state_init <= WRITE_REG;
392 next_state <= SRX2;
393 when SRX2 =>
394 par_addr <= W5300_RMS45R;
395 state_init <= WRITE_REG;
396 next_state <= SRX3;
397 when SRX3 =>
398 par_addr <= W5300_RMS67R;
399 state_init <= WRITE_REG;
400 next_state <= MAC;
401
402 -- MAC
403 when MAC =>
404 par_addr <= W5300_SHAR;
405 par_data <= MAC_ADDRESS (0);
406 state_init <= WRITE_REG;
407 next_state <= MAC1;
408 when MAC1 =>
409 par_addr <= W5300_SHAR + 2;
410 par_data <= MAC_ADDRESS (1);
411 state_init <= WRITE_REG;
412 next_state <= MAC2;
413 when MAC2 =>
414 par_addr <= W5300_SHAR + 4;
415 par_data <= MAC_ADDRESS (2);
416 state_init <= WRITE_REG;
417 next_state <= GW;
418
419 -- Gateway
420 when GW =>
421 par_addr <= W5300_GAR;
422 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0), 8);
423 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1), 8);
424 state_init <= WRITE_REG;
425 next_state <= GW1;
426 when GW1 =>
427 par_addr <= W5300_GAR + 2;
428 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2), 8);
429 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3), 8);
430 state_init <= WRITE_REG;
431 next_state <= SNM;
432
433 -- Subnet Mask
434 when SNM =>
435 par_addr <= W5300_SUBR;
436 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0), 8);
437 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1), 8);
438 state_init <= WRITE_REG;
439 next_state <= SNM1;
440 when SNM1 =>
441 par_addr <= W5300_SUBR + 2;
442 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2), 8);
443 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3), 8);
444 state_init <= WRITE_REG;
445 next_state <= IP;
446 -- Own IP-Address
447 when IP =>
448 par_addr <= W5300_SIPR;
449 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0), 8);
450 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1), 8);
451 state_init <= WRITE_REG;
452 next_state <= IP1;
453 when IP1 =>
454 par_addr <= W5300_SIPR + 2;
455 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2), 8);
456 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3), 8);
457 state_init <= WRITE_REG;
458 next_state <= SI;
459 -- Socket Init
460 when SI =>
461 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
462 par_data <= X"0101"; -- ALIGN, TCP
463 state_init <= WRITE_REG;
464 next_state <= SI0;
465 -- keep alive
466 when SI0 =>
467 par_addr <= W5300_S0_KPALVTR + socket_cnt * W5300_S_INC;
468 par_data <= X"0C00"; -- 12 * 5s = 60s
469 state_init <= WRITE_REG;
470 next_state <= SI1;
471 -- Sx Interrupt Mask
472 when SI1 =>
473 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
474 par_data <= X"000A"; -- TIMEOUT, DISCON
475 state_init <= WRITE_REG;
476 next_state <= SI2;
477 when SI2 =>
478 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
479 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
480 state_init <= WRITE_REG;
481 next_state <= SI3;
482 when SI3 =>
483 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
484 par_data <= X"0001"; -- OPEN
485 state_init <= WRITE_REG;
486 next_state <= SI4;
487 when SI4 =>
488 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
489 state_init <= READ_REG;
490 next_state <= SI5;
491 when SI5 =>
492 if (data_read (7 downto 0) = X"13") then -- is open?
493 state_init <= SI6;
494 else
495 state_init <= SI4;
496 end if;
497 when SI6 =>
498 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
499 par_data <= X"0002"; -- LISTEN
500 state_init <= WRITE_REG;
501 socket_cnt <= socket_cnt + 1;
502 if (socket_cnt = W5300_LAST_SOCKET) then
503 socket_cnt <= "000";
504 next_state <= ESTABLISH; -- All Sockets open
505 else
506 next_state <= SI; -- Next Socket
507 end if;
508 -- End Socket Init
509
510 when ESTABLISH =>
511 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
512 state_init <= READ_REG;
513 next_state <= EST1;
514 when EST1 =>
515 case data_read (7 downto 0) is
516 when X"17" => -- established
517 if (socket_cnt = W5300_LAST_SOCKET) then
518 socket_cnt <= "000";
519 busy <= '0';
520 state_init <= MAIN;
521 -- -- --
522 config_started_ack <= '0';
523 dd_block_ready <= '0';
524 dd_send_ack <= '0';
525 dd_send_ready <= '0';
526 ftu_error_send_ack <= '0';
527 ftu_error_send_ready <= '0';
528 led_int <= X"00";
529 wait_for_data_flag <= '0';
530 -- -- --
531 else
532 socket_cnt <= socket_cnt + 1;
533 state_init <= ESTABLISH;
534 end if;
535 when others =>
536 state_init <= ESTABLISH;
537 -- -- --
538 -- Just for fun...
539 if (led_cnt = 1100000) then
540 if (led_int = X"00") then
541 led_int <= X"18";
542 else
543 led_int (7 downto 4) <= led_int (6 downto 4) & '0';
544 led_int (3 downto 0) <= '0' & led_int (3 downto 1);
545 end if;
546 led_cnt <= 0;
547 else
548 led_cnt <= led_cnt + 1;
549 end if;
550 -- -- --
551 end case;
552
553 when CONFIG =>
554 new_config <= '1';
555 config_started_ack <= '0';
556 if (config_started = '1') then
557 new_config <= '0';
558 config_started_ack <= '1';
559 state_init <= MAIN;
560 end if;
561
562 -- main "loop"
563 when MAIN =>
564 chk_recv_cntr <= chk_recv_cntr + 1;
565 if (chk_recv_cntr = 1000) then
566 chk_recv_cntr <= 0;
567 state_read_data <= RD_1;
568 state_init <= READ_DATA;
569 busy <= '1';
570 elsif ((dd_send = '1') and (wait_for_data_flag = '0')) then
571 internal_cmd <= '1';
572 dd_send_ack <= '1';
573 dd_send_ready <= '0';
574 if (autosend_flag = '0') then
575 state_read_dd_block <= READ_DD_BLOCK_END;
576 end if;
577 state_read_data <= RD_READ_DD_BLOCK;
578 state_init <= READ_DATA;
579 elsif ((ftu_error_send = '1') and (wait_for_data_flag = '0')) then
580 ftu_error_send_ack <= '1';
581 ftu_error_send_ready <= '0';
582 if (autosend_flag = '0') then
583 state_send_ftu_error <= SFE_END;
584 end if;
585 state_init <= SEND_FTU_ERROR;
586 end if;
587
588
589 -- send FTU error message
590 when SEND_FTU_ERROR =>
591 case state_send_ftu_error is
592 when SFE_START =>
593 next_state <= SEND_FTU_ERROR;
594 data_package_type <= FTM_PACKAGE_TYPE_FTU_ERR;
595 data_package_length <= FTU_ERROR_LENGTH + 1; -- +1 := package end
596 read_addr_state <= READ_FTU_ERROR;
597 local_sd_addr <= X"000";
598 local_write_length <= "00000" & FTU_ERROR_LENGTH;
599 state_send_ftu_error <= SFE_END;
600 state_init <= WRITE_DATA;
601 when SFE_END =>
602 if (ftu_error_send = '0') then
603 ftu_error_send_ack <= '0';
604 ftu_error_send_ready <= '1';
605 state_send_ftu_error <= SFE_START;
606 state_init <= MAIN;
607 end if;
608 end case;
609
610
611 -- read data from socket 0
612 when READ_DATA =>
613 case state_read_data is
614 when RD_1 =>
615 par_addr <= W5300_S0_RX_RSR;
616 state_init <= READ_REG;
617 next_state <= READ_DATA;
618 state_read_data <= RD_2;
619 when RD_2 =>
620 socket_rx_received (31 downto 16) <= data_read;
621 par_addr <= W5300_S0_RX_RSR + X"2";
622 state_init <= READ_REG;
623 next_state <= READ_DATA;
624 state_read_data <= RD_3;
625 when RD_3 =>
626 socket_rx_received (15 downto 0) <= data_read;
627 state_read_data <= RD_4;
628 when RD_4 =>
629 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
630 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
631 state_read_data <= RD_5;
632 else
633 busy <= '0';
634 state_init <= MAIN;
635 end if;
636 when RD_5 =>
637 if (rx_packets_cnt > 0) then
638 rx_packets_cnt <= rx_packets_cnt - '1';
639 par_addr <= W5300_S0_RX_FIFOR;
640 state_init <= READ_REG;
641 next_state <= READ_DATA;
642 state_read_data <= next_state_read_data;
643 else
644 state_read_data <= RD_END;
645 end if;
646
647 when RD_END =>
648 if (new_config_flag = '1') then
649 new_config_flag <= '0';
650 next_state <= CONFIG;
651 else
652 next_state <= MAIN;
653 end if;
654 if (internal_cmd = '0') then
655 par_addr <= W5300_S0_CR;
656 par_data <= X"0040"; -- RECV
657 state_init <= WRITE_REG;
658 else
659 internal_cmd <= '0';
660 state_init <= MAIN;
661 end if;
662
663
664 -------------------------
665 -- command handling
666 -------------------------
667
668 -- read command (5 words)
669 when RD_CMD =>
670 cmd_array (next_packet_data_cnt) <= data_read;
671 next_packet_data_cnt <= next_packet_data_cnt + 1;
672 -- look for command start
673 if (next_packet_data_cnt = 0) then
674 if (data_read /= CMD_START_DELIMITER) then
675 next_packet_data_cnt <= 0;
676 end if;
677 end if;
678 -- last command-word
679 if (next_packet_data_cnt = 4) then
680 next_packet_data_cnt <= 0;
681 state_read_data <= RD_CMD_PARSE;
682 else
683 state_read_data <= RD_5;
684 end if;
685
686 -- process commands and parameters
687 when RD_CMD_PARSE =>
688 case cmd_array (1) is
689
690 when CMD_TLED =>
691 led_int <= NOT led_int;
692 state_read_data <= RD_5;
693
694 when CMD_START =>
695 case cmd_array (2) is
696 -- start "normal" run
697 when PAR_START_RUN =>
698 start_run <= '1';
699 start_run_param <= cmd_array (2);
700 if (start_run_ack = '1') then
701 start_run <= '0';
702 state_read_data <= RD_5;
703 end if;
704 -- start run an take X events
705 when PAR_START_X_EVNTS =>
706 next_state_read_data <= RD_X_EVNTS;
707 wait_for_data_flag <= '1';
708 state_read_data <= RD_5;
709 when others =>
710 state_read_data <= RD_5;
711 end case;
712
713 when CMD_STOP =>
714 stop_run <= '1';
715 if (stop_run_ack = '1') then
716 stop_run <= '0';
717 state_read_data <= RD_5;
718 end if;
719
720 when CMD_CRESET =>
721 crate_reset <= '1';
722 crate_reset_param <= cmd_array (2);
723 if (crate_reset_ack = '1') then
724 crate_reset <= '0';
725 state_read_data <= RD_5;
726 end if;
727
728 when CMD_WRITE =>
729 case cmd_array (2) is
730 -- write to address in static data block
731 when PAR_WRITE_SD_ADDR =>
732 wait_for_data_flag <= '1';
733 next_state_read_data <= RD_WRITE_SD_ADDR;
734 state_read_data <= RD_5;
735 -- write static data block
736 when PAR_WRITE_SD =>
737 wait_for_data_flag <= '1';
738 next_state_read_data <= RD_WRITE_SD_BLOCK;
739 state_read_data <= RD_5;
740 when others =>
741 state_read_data <= RD_5;
742 end case; -- cmd_array (2)
743
744 when CMD_READ =>
745 case cmd_array (2) is
746 -- read from address in static data block
747 when PAR_READ_SD_ADDR =>
748 wait_for_data_flag <= '1';
749 next_state_read_data <= RD_READ_SD_ADDR;
750 state_read_data <= RD_5;
751 -- read static data block
752 when PAR_READ_SD =>
753 state_read_data <= RD_READ_SD_BLOCK;
754 -- read dynamic data block
755 when PAR_READ_DD =>
756 state_read_data <= RD_READ_DD_BLOCK;
757 when others =>
758 state_read_data <= RD_5;
759 end case; -- cmd_array (2)
760
761 when CMD_PING =>
762 state_ping <= PING_START;
763 state_read_data <= RD_PING;
764
765 when CMD_AUTOSEND =>
766 state_read_data <= RD_5;
767 case cmd_array (2) is
768 when PAR_AUTOSEND_EA =>
769 autosend_flag <= '1';
770 when PAR_AUTOSEND_DA =>
771 autosend_flag <= '0';
772 when others =>
773 null;
774 end case;
775
776 when others =>
777 state_read_data <= RD_5;
778
779 end case; -- cmd_array (1)
780
781
782 -- ping all FTUs and write FTU-list to ethernet
783 when RD_PING =>
784 case state_ping is
785 when PING_START =>
786 ping_ftu_start <= '1';
787 if (ping_ftu_started = '1') then
788 ping_ftu_start <= '0';
789 state_ping <= PING_WAIT;
790 end if;
791 when PING_WAIT =>
792 if (ping_ftu_ready = '1') then
793 state_ping <= PING_WRITE_LIST;
794 end if;
795 when PING_WRITE_LIST =>
796 state_read_data <= RD_5;
797 data_package_type <= FTM_PACKAGE_TYPE_FTU_LIST;
798 data_package_length <= FL_BLOCK_SIZE + 1; -- +1 := package end
799 read_addr_state <= READ_FROM_FL_ADDR;
800 local_sd_addr <= X"000"; --start at address 0x000
801 local_write_length <= "00000" & FL_BLOCK_SIZE;
802 next_state_read_data <= RD_CMD;
803 next_state <= READ_DATA;
804 state_init <= WRITE_DATA;
805 end case;
806
807 -- read dynamic data block and write it to ethernet
808 when RD_READ_DD_BLOCK =>
809 case state_read_dd_block is
810 when READ_DD_BLOCK_START =>
811 dd_block_start <= '1';
812 dd_block_ready <= '0';
813 if (dd_block_start_ack = '1') then
814 dd_block_start <= '0';
815 state_read_dd_block <= READ_DD_BLOCK_WRITE_GENERAL;
816 end if;
817 -- write on-time counter and tempertures to dd-block
818 when READ_DD_BLOCK_WRITE_GENERAL =>
819 dd_write_general <= '1';
820 if (dd_write_general_started = '1') then
821 dd_write_general <= '0';
822 state_read_dd_block <= READ_DD_BLOCK_WRITE;
823 end if;
824 -- write dd-block to ethernet when on-time counter and temperatures are ready
825 when READ_DD_BLOCK_WRITE =>
826 if (dd_write_general_ready = '1') then
827 data_package_type <= FTM_PACKAGE_TYPE_DD;
828 data_package_length <= DD_BLOCK_SIZE + 1; -- +1 := package end
829 read_addr_state <= READ_FROM_DD_ADDR;
830 local_sd_addr <= X"000"; -- start at address 0x000
831 local_write_length <= "00000" & DD_BLOCK_SIZE;
832 state_read_dd_block <= READ_DD_BLOCK_END;
833 next_state <= READ_DATA;
834 state_init <= WRITE_DATA;
835 end if;
836 when READ_DD_BLOCK_END =>
837 dd_block_ready <= '1';
838 next_state_read_data <= RD_CMD;
839 --
840 if (internal_cmd = '1') then
841 state_read_dd_block <= READ_DD_BLOCK_INTERN;
842 else
843 state_read_dd_block <= READ_DD_BLOCK_START;
844 state_read_data <= RD_5;
845 end if;
846 when READ_DD_BLOCK_INTERN =>
847 if (dd_send = '0') then
848 dd_send_ready <= '1';
849 dd_send_ack <= '0';
850 state_read_dd_block <= READ_DD_BLOCK_START;
851 state_read_data <= RD_5;
852 end if;
853
854 end case;
855
856 -- read static data block and write it to ethernet
857 when RD_READ_SD_BLOCK =>
858 data_package_type <= FTM_PACKAGE_TYPE_SD;
859 data_package_length <= SD_BLOCK_SIZE + 1; -- +1 := package end
860 state_read_data <= RD_5;
861 read_addr_state <= READ_FROM_SD_ADDR;
862 local_sd_addr <= X"000"; -- start at address 0x000
863 local_write_length <= "00000" & SD_BLOCK_SIZE;
864 next_state_read_data <= RD_CMD;
865 next_state <= READ_DATA;
866 state_init <= WRITE_DATA;
867
868 -- read from address in static data ram and write data to ethernet
869 when RD_READ_SD_ADDR =>
870 data_package_type <= FTM_PACKAGE_TYPE_SD_WORD;
871 data_package_length <= SD_SINGLE_WORD_SIZE + 1; -- +1 := package end
872 state_read_data <= RD_5;
873 read_addr_state <= READ_FROM_SD_ADDR;
874 local_sd_addr <= data_read (11 downto 0);
875 local_write_length <= '0' & X"0001"; -- one word will be written to ethernet
876 next_state_read_data <= RD_CMD;
877 wait_for_data_flag <= '0';
878 next_state <= READ_DATA;
879 state_init <= WRITE_DATA;
880
881 -- read static data block from ethernet and write it to static data ram
882 when RD_WRITE_SD_BLOCK =>
883 state_read_data <= RD_5;
884 next_packet_data_cnt <= next_packet_data_cnt + 1;
885 local_sd_addr <= conv_std_logic_vector (next_packet_data_cnt, 12);
886 local_sd_data <= data_read;
887 next_state <= READ_DATA;
888 state_init <= WRITE_TO_SD_ADDR;
889 -- last word
890 if (next_packet_data_cnt = (SD_BLOCK_SIZE - 1)) then
891 next_packet_data_cnt <= 0;
892 wait_for_data_flag <= '0';
893 new_config_flag <= '1';
894 next_state_read_data <= RD_CMD;
895 end if;
896
897 -- write to address in static data ram
898 when RD_WRITE_SD_ADDR =>
899 state_read_data <= RD_5;
900 next_packet_data_cnt <= next_packet_data_cnt + 1;
901 if (next_packet_data_cnt = 0) then
902 local_sd_addr <= data_read (11 downto 0);
903 else
904 local_sd_data <= data_read;
905 next_packet_data_cnt <= 0;
906 wait_for_data_flag <= '0';
907 new_config_flag <= '1';
908 next_state_read_data <= RD_CMD;
909 next_state <= READ_DATA;
910 state_init <= WRITE_TO_SD_ADDR;
911 end if;
912
913 -- read X events
914 when RD_X_EVNTS =>
915 if (next_packet_data_cnt = 0) then
916 start_run_num_events (31 downto 16) <= data_read;
917 else
918 start_run_num_events (15 downto 0) <= data_read;
919 start_run_param <= cmd_array (2);
920 start_run <= '1';
921 if (start_run_ack = '1') then
922 start_run <= '0';
923 next_packet_data_cnt <= 0;
924 wait_for_data_flag <= '0';
925 next_state_read_data <= RD_CMD;
926 state_read_data <= RD_5;
927 end if;
928 end if;
929
930 end case; -- state_read_data
931
932
933 -- read FTU errors
934 when READ_FTU_ERROR =>
935 state_init <= next_state;
936 if (data_cnt = 0) then
937 local_sd_data <= ftu_error_calls;
938 else
939 local_sd_data <= X"00" & ftu_error_data (((data_cnt * 8) - 1) DOWNTO ((data_cnt * 8) - 8));
940 end if;
941
942
943 -- read from header modul
944 when READ_FROM_HEADER_MODUL =>
945 state_init <= next_state;
946 case header_cnt is
947 when X"00" =>
948 local_sd_data <= data_package_type;
949 when X"01" =>
950 local_sd_data <= data_package_length;
951 when X"02" =>
952 local_sd_data <= header_current_state;
953 when X"03" =>
954 local_sd_data <= header_board_id (63 DOWNTO 48);
955 when X"04" =>
956 local_sd_data <= header_board_id (47 DOWNTO 32);
957 when X"05" =>
958 local_sd_data <= header_board_id (31 DOWNTO 16);
959 when X"06" =>
960 local_sd_data <= header_board_id (15 DOWNTO 0);
961 when X"07" =>
962 local_sd_data <= header_firmware_id;
963 when X"08" =>
964 local_sd_data <= header_trigger_counter (31 DOWNTO 16);
965 when X"09" =>
966 local_sd_data <= header_trigger_counter (15 DOWNTO 0);
967 when X"0A" =>
968 local_sd_data <= X"0000";
969 when X"0B" =>
970 local_sd_data <= header_timestamp_counter (47 DOWNTO 32);
971 when X"0C" =>
972 local_sd_data <= header_timestamp_counter (31 DOWNTO 16);
973 when X"0D" =>
974 local_sd_data <= header_timestamp_counter (15 DOWNTO 0);
975 when others =>
976 null;
977 end case;
978
979 -- read from ftu list ram
980 when READ_FROM_FL_ADDR =>
981 case state_read_fl is
982 when READ_FL_START =>
983 if (fl_busy = '0') then
984 fl_addr <= local_sd_addr;
985 fl_read <= '1';
986 state_read_fl <= READ_FL_WAIT;
987 end if;
988 when READ_FL_WAIT =>
989 if (fl_started = '1') then
990 state_read_fl <= READ_FL_END;
991 end if;
992 when READ_FL_END =>
993 if (fl_ready = '1') then
994 local_sd_data <= fl_data_in;
995 fl_read <= '0';
996 state_read_fl <= READ_FL_START;
997 state_init <= next_state;
998 end if;
999 end case;
1000
1001 -- read from dynamic data block
1002 when READ_FROM_DD_ADDR =>
1003 case state_read_dd is
1004 when READ_DD_START =>
1005 if (dd_busy = '0') then
1006 dd_addr <= local_sd_addr;
1007 dd_read <= '1';
1008 state_read_dd <= READ_DD_WAIT;
1009 end if;
1010 when READ_DD_WAIT =>
1011 if (dd_started = '1') then
1012 state_read_dd <= READ_DD_END;
1013 end if;
1014 when READ_DD_END =>
1015 if (dd_ready = '1') then
1016 local_sd_data <= dd_data_in;
1017 dd_read <= '0';
1018 state_read_dd <= READ_DD_START;
1019 state_init <= next_state;
1020 end if;
1021 end case;
1022
1023 -- read from static data block
1024 when READ_FROM_SD_ADDR =>
1025 case state_read_sd is
1026 when READ_SD_START =>
1027 if (sd_busy = '0') then
1028 sd_addr <= local_sd_addr;
1029 sd_read <= '1';
1030 state_read_sd <= READ_SD_WAIT;
1031 end if;
1032 when READ_SD_WAIT =>
1033 if (sd_started = '1') then
1034 state_read_sd <= READ_SD_END;
1035 end if;
1036 when READ_SD_END =>
1037 if (sd_ready = '1') then
1038 local_sd_data <= sd_data_in;
1039 sd_read <= '0';
1040 state_read_sd <= READ_SD_START;
1041 state_init <= next_state;
1042 end if;
1043 end case;
1044
1045 -- write to static data block
1046 when WRITE_TO_SD_ADDR =>
1047 case state_write_sd is
1048 when WRITE_SD_START =>
1049 if (sd_busy = '0') then
1050 sd_addr <= local_sd_addr;
1051 sd_data_out <= local_sd_data;
1052 sd_write <= '1';
1053 state_write_sd <= WRITE_SD_WAIT;
1054 end if;
1055 when WRITE_SD_WAIT =>
1056 if (sd_started = '1') then
1057 sd_write <= '0';
1058 state_write_sd <= WRITE_SD_END;
1059 end if;
1060 when WRITE_SD_END =>
1061 if (sd_ready = '1') then
1062 state_write_sd <= WRITE_SD_START;
1063 state_init <= next_state;
1064 end if;
1065 end case;
1066
1067 -- write to ethernet interface
1068 when WRITE_DATA =>
1069 case state_write is
1070 when WR_START =>
1071 state_write <= WR_LENGTH;
1072 when WR_LENGTH =>
1073 local_socket_nr <= "000";
1074 next_state_tmp <= next_state;
1075 -- Write Length: 2 := START and END of package
1076 write_length_bytes <= (2 + FTM_HEADER_LENGTH + local_write_length (15 downto 0)) & '0'; -- shift left (*2)
1077 data_cnt <= 0;
1078 header_cnt <= X"00";
1079 state_write <= WR_01;
1080 -- Check FIFO Size
1081 when WR_01 =>
1082 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
1083 state_init <= READ_REG;
1084 next_state <= WRITE_DATA;
1085 state_write <= WR_02;
1086 when WR_02 =>
1087 socket_tx_free (31 downto 16) <= data_read;
1088 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
1089 state_init <= READ_REG;
1090 next_state <= WRITE_DATA;
1091 state_write <= WR_03;
1092 when WR_03 =>
1093 socket_tx_free (15 downto 0) <= data_read;
1094 state_write <= WR_04;
1095 when WR_04 =>
1096 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
1097 state_write <= WR_01;
1098 else
1099 state_write <= WR_WRITE_START_DEL;
1100 end if;
1101
1102 -- write package start delimiter
1103 when WR_WRITE_START_DEL =>
1104 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1105 par_data <= FTM_PACKAGE_START;
1106 state_init <= WRITE_REG;
1107 next_state <= WRITE_DATA;
1108 state_write <= WR_GET_HEADER;
1109
1110 -- get header data
1111 when WR_GET_HEADER =>
1112 get_header <= '1';
1113 if (get_header_started = '1') then
1114 get_header <= '0';
1115 state_write <= WR_GET_HEADER_WAIT;
1116 end if;
1117
1118 when WR_GET_HEADER_WAIT =>
1119 if (get_header_ready = '1') then
1120 state_write <= WR_FIFO_HEADER;
1121 end if;
1122
1123 -- Fill FIFO
1124 -- write header
1125 when WR_FIFO_HEADER =>
1126 state_init <= READ_FROM_HEADER_MODUL;
1127 next_state <= WRITE_DATA;
1128 state_write <= WR_FIFO_HEADER_01;
1129
1130 when WR_FIFO_HEADER_01 =>
1131 header_cnt <= header_cnt + 1;
1132 if (header_cnt < FTM_HEADER_LENGTH) then
1133 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1134 par_data <= local_sd_data;
1135 state_init <= WRITE_REG;
1136 next_state <= WRITE_DATA;
1137 state_write <= WR_FIFO_HEADER;
1138 else
1139 if (data_package_type = FTM_PACKAGE_TYPE_SD_WORD) then
1140 state_write <= WR_SD_ADDR;
1141 else
1142 state_write <= WR_FIFO_DATA;
1143 end if;
1144 end if;
1145
1146 -- write static data ram address (only for single address request)
1147 when WR_SD_ADDR =>
1148 write_length_bytes <= write_length_bytes + 2; -- one extra word to write
1149 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1150 par_data <= "0000" & local_sd_addr;
1151 state_init <= WRITE_REG;
1152 next_state <= WRITE_DATA;
1153 state_write <= WR_FIFO_DATA;
1154
1155 -- write data
1156 when WR_FIFO_DATA =>
1157 state_init <= read_addr_state;
1158 next_state <= WRITE_DATA;
1159 state_write <= WR_FIFO_DATA_01;
1160
1161 when WR_FIFO_DATA_01 =>
1162 data_cnt <= data_cnt + 1;
1163 if (data_cnt < local_write_length) then
1164 local_sd_addr <= local_sd_addr + 1;
1165 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1166 par_data <= local_sd_data;
1167 state_init <= WRITE_REG;
1168 next_state <= WRITE_DATA;
1169 state_write <= WR_FIFO_DATA;
1170 else
1171 state_write <= WR_WRITE_END_DEL;
1172 end if;
1173
1174 -- write package end delimiter
1175 when WR_WRITE_END_DEL =>
1176 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1177 par_data <= FTM_PACKAGE_END;
1178 state_init <= WRITE_REG;
1179 next_state <= WRITE_DATA;
1180 state_write <= WR_05;
1181
1182 -- Send FIFO
1183 when WR_05 =>
1184 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
1185 par_data <= (0 => write_length_bytes (16), others => '0');
1186 state_init <= WRITE_REG;
1187 state_write <= WR_06;
1188 when WR_06 =>
1189 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
1190 par_data <= write_length_bytes (15 downto 0);
1191 state_init <= WRITE_REG;
1192 state_write <= WR_07;
1193 when WR_07 =>
1194 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
1195 par_data <= X"0020"; -- Send
1196 state_init <= WRITE_REG;
1197 state_write <= WR_08;
1198 when others =>
1199 state_init <= next_state_tmp;
1200 state_write <= WR_START;
1201 end case;
1202 -- End WRITE_DATA
1203
1204 when READ_REG =>
1205 case count is
1206 when "000" =>
1207 cs <= '0';
1208 rd <= '0';
1209 wr <= '1';
1210 data <= (others => 'Z'); -- !!!!!!!!!!
1211 count <= "001";
1212 addr <= par_addr;
1213 when "001" =>
1214 count <= "010";
1215 when "010" =>
1216 count <= "100";
1217 when "100" =>
1218 data_read <= data;
1219 count <= "110";
1220 when "110" =>
1221 count <= "111";
1222 when "111" =>
1223 cs <= '1';
1224 rd <= '1';
1225 count <= "000";
1226 state_init <= next_state;
1227 when others =>
1228 null;
1229 end case;
1230
1231 when WRITE_REG =>
1232 case count is
1233 when "000" =>
1234 cs <= '0';
1235 wr <= '0';
1236 rd <= '1';
1237 addr <= par_addr;
1238 data <= par_data;
1239 count <= "100";
1240 when "100" =>
1241 count <= "101";
1242 when "101" =>
1243 count <= "110";
1244 when "110" =>
1245 cs <= '1';
1246 wr <= '1';
1247 state_init <= next_state;
1248 count <= "000";
1249 when others =>
1250 null;
1251 end case;
1252
1253 when others =>
1254 null;
1255 end case;
1256 end if; -- int_flag = '0'
1257
1258 end if; -- rising_edge (clk)
1259
1260 end process w5300_init_proc;
1261
1262end Behavioral;
1263
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