source: firmware/FTM/ftm_board.ucf@ 16318

Last change on this file since 16318 was 10879, checked in by weitzel, 14 years ago
FTM: new light pulser interface, new timing constraint in .ucf file
File size: 16.3 KB
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1########################################################
2# FTM Board
3# FACT Trigger Master
4#
5# Pin location constraints
6#
7# by Patrick Vogler, 18 August 2010
8#
9# modified by Q. Weitzel, 01 March 2011
10# (NET W_A<0> added and assigned to unconnected pin)
11########################################################
12
13#Clock
14#######################################################
15NET clk LOC = Y14 |IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47
16
17# Ethernet Interface
18# connection to the WIZnet W5300 ethernet controller (U37)
19# on IO-Bank 1
20#######################################################
21# data bus
22NET W_D<0> LOC = M22 |IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300
23NET W_D<1> LOC = L22 |IOSTANDARD=LVCMOS33; #
24NET W_D<2> LOC = K23 |IOSTANDARD=LVCMOS33; #
25NET W_D<3> LOC = K25 |IOSTANDARD=LVCMOS33; #
26NET W_D<4> LOC = K26 |IOSTANDARD=LVCMOS33; #
27NET W_D<5> LOC = J22 |IOSTANDARD=LVCMOS33; #
28NET W_D<6> LOC = J23 |IOSTANDARD=LVCMOS33; #
29NET W_D<7> LOC = G23 |IOSTANDARD=LVCMOS33; #
30NET W_D<8> LOC = G24 |IOSTANDARD=LVCMOS33; #
31NET W_D<9> LOC = F24 |IOSTANDARD=LVCMOS33; #
32NET W_D<10> LOC = F25 |IOSTANDARD=LVCMOS33; #
33NET W_D<11> LOC = E24 |IOSTANDARD=LVCMOS33; #
34NET W_D<12> LOC = E26 |IOSTANDARD=LVCMOS33; #
35NET W_D<13> LOC = D24 |IOSTANDARD=LVCMOS33; #
36NET W_D<14> LOC = D26 |IOSTANDARD=LVCMOS33; #
37NET W_D<15> LOC = D25 |IOSTANDARD=LVCMOS33; #
38# W5300 address bus
39NET W_A<0> LOC = U18 |IOSTANDARD=LVCMOS33; # there is no real net W_A0 because
40NET W_A<1> LOC = AA25 |IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode
41NET W_A<2> LOC = AA24 |IOSTANDARD=LVCMOS33; # (see W5300 datasheet)
42NET W_A<3> LOC = AA23 |IOSTANDARD=LVCMOS33; # -> W_A<0> assigned to unconnected pin
43NET W_A<4> LOC = Y25 |IOSTANDARD=LVCMOS33; #
44NET W_A<5> LOC = Y24 |IOSTANDARD=LVCMOS33; #
45NET W_A<6> LOC = Y23 |IOSTANDARD=LVCMOS33; #
46NET W_A<7> LOC = W23 |IOSTANDARD=LVCMOS33; #
47NET W_A<8> LOC = V25 |IOSTANDARD=LVCMOS33; #
48NET W_A<9> LOC = V24 |IOSTANDARD=LVCMOS33; #
49# W5300 control signals
50# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
51# W_CS is also routed to testpoint JP7
52NET W_CS LOC = T20 |IOSTANDARD=LVCMOS33; # W5300 chip select
53NET W_INT LOC = U22 |IOSTANDARD=LVCMOS33; # interrupt
54NET W_RD LOC = R20 |IOSTANDARD=LVCMOS33; # read
55NET W_WR LOC = P22 |IOSTANDARD=LVCMOS33; # write
56NET W_RES LOC = U23 |IOSTANDARD=LVCMOS33; # reset W5300 chip
57# W5300 buffer ready indicator
58# NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; #
59# NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; #
60# NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; #
61# NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; #
62# W5300 associated testpoints
63# NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; #
64# NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; #
65# NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; #
66# NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; #
67
68# SPI Interface
69# connection to the EEPROM U36 (AL25L016M) and the temperature
70# sensors U45, U46, U48 and U49 (all MAX6662)
71# on IO-Bank 1
72#######################################################
73# NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock
74# EEPROM
75# NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in
76# NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out
77# NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in
78# temperature sensors
79# NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO
80# NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0
81# NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1
82# NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2
83# NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3
84
85# Trigger primitives inputs
86# on IO-Bank 2
87#######################################################
88# crate 0
89# crate A
90NET Trig_Prim_A<0> LOC = AC6 |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0>
91NET Trig_Prim_A<1> LOC = AD6 |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1>
92NET Trig_Prim_A<2> LOC = AF3 |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2>
93NET Trig_Prim_A<3> LOC = AE4 |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3>
94NET Trig_Prim_A<4> LOC = AE6 |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4>
95NET Trig_Prim_A<5> LOC = AE7 |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5>
96NET Trig_Prim_A<6> LOC = AE8 |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6>
97NET Trig_Prim_A<7> LOC = AC8 |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7>
98NET Trig_Prim_A<8> LOC = AC11 |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8>
99NET Trig_Prim_A<9> LOC = AD11 |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9>
100# crate 1
101# crate B
102NET Trig_Prim_B<0> LOC = AB16 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0>
103NET Trig_Prim_B<1> LOC = AC15 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1>
104NET Trig_Prim_B<2> LOC = AC16 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2>
105NET Trig_Prim_B<3> LOC = AE17 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3>
106NET Trig_Prim_B<4> LOC = AD19 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4>
107NET Trig_Prim_B<5> LOC = AE19 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5>
108NET Trig_Prim_B<6> LOC = AE20 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6>
109NET Trig_Prim_B<7> LOC = AF20 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7>
110NET Trig_Prim_B<8> LOC = AD21 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8>
111NET Trig_Prim_B<9> LOC = AE23 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9>
112# crate 2
113# crate C
114NET Trig_Prim_C<0> LOC = AF23 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0>
115NET Trig_Prim_C<1> LOC = AC21 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1>
116NET Trig_Prim_C<2> LOC = AE21 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2>
117NET Trig_Prim_C<3> LOC = AD20 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3>
118NET Trig_Prim_C<4> LOC = AC20 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4>
119NET Trig_Prim_C<5> LOC = AF19 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5>
120NET Trig_Prim_C<6> LOC = AC19 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6>
121NET Trig_Prim_C<7> LOC = AD17 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7>
122NET Trig_Prim_C<8> LOC = AD14 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8>
123NET Trig_Prim_C<9> LOC = AC14 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9>
124# crate 3
125# crate D
126NET Trig_Prim_D<0> LOC = AB12 |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0>
127NET Trig_Prim_D<1> LOC = AC12 |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1>
128NET Trig_Prim_D<2> LOC = AC9 |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2>
129NET Trig_Prim_D<3> LOC = AB9 |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3>
130NET Trig_Prim_D<4> LOC = AB7 |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4>
131NET Trig_Prim_D<5> LOC = AF8 |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5>
132NET Trig_Prim_D<6> LOC = AF4 |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6>
133NET Trig_Prim_D<7> LOC = AF5 |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7>
134NET Trig_Prim_D<8> LOC = AD7 |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8>
135NET Trig_Prim_D<9> LOC = AE3 |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9>
136
137# NIM inputs
138#######################################################
139# on IO-Bank 3
140NET ext_Trig<1> LOC = B1 |IOSTANDARD=LVCMOS33; #
141NET ext_Trig<2> LOC = B2 |IOSTANDARD=LVCMOS33; #
142NET Veto LOC = E4 |IOSTANDARD=LVCMOS33; #
143# NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; #
144# NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; #
145# NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; #
146# on IO-Bank 0
147# input pin with global clock buffer available
148# NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33;
149
150# LEDs
151# on IO-Banks 0 and 3
152#######################################################
153# red
154NET LED_red<0> LOC = D6 |IOSTANDARD=LVCMOS33; # IO-Bank 0
155NET LED_red<1> LOC = A4 |IOSTANDARD=LVCMOS33; # IO-Bank 0
156NET LED_red<2> LOC = E1 |IOSTANDARD=LVCMOS33; # IO-Bank 3
157NET LED_red<3> LOC = J5 |IOSTANDARD=LVCMOS33; # IO-Bank 3
158# yellow
159NET LED_ye<0> LOC = C5 |IOSTANDARD=LVCMOS33; # IO-Bank 0
160NET LED_ye<1> LOC = B3 |IOSTANDARD=LVCMOS33; # IO-Bank 0
161# green
162NET LED_gn<0> LOC = B4 |IOSTANDARD=LVCMOS33; # IO-Bank 0
163NET LED_gn<1> LOC = A3 |IOSTANDARD=LVCMOS33; # IO-Bank 0
164
165# Clock conditioner LMK03000
166# on IO-Bank 3
167#######################################################
168NET CLK_Clk_Cond LOC = G4 |IOSTANDARD=LVCMOS33; # IO-Bank 3
169NET LE_Clk_Cond LOC = F2 |IOSTANDARD=LVCMOS33; # IO-Bank 3
170NET LD_Clk_Cond LOC = J4 |IOSTANDARD=LVCMOS33; # IO-Bank 3
171NET DATA_Clk_Cond LOC = F3 |IOSTANDARD=LVCMOS33; # IO-Bank 3
172NET SYNC_Clk_Cond LOC = H2 |IOSTANDARD=LVCMOS33; # IO-Bank 3
173
174# various RS-485 Interfaces
175# on IO-Bank 3
176#######################################################
177# Bus 1: FTU slow control
178NET Bus1_Tx_En LOC = H1 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
179NET Bus1_Rx_En LOC = G3 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
180# crate 0
181NET Bus1_RxD_0 LOC = K3 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
182NET Bus1_TxD_0 LOC = L3 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
183# crate 1
184NET Bus1_RxD_1 LOC = M2 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
185NET Bus1_TxD_1 LOC = N4 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
186# crate 2
187NET Bus1_RxD_2 LOC = P3 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
188NET Bus1_TxD_2 LOC = P4 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
189# crate 3
190NET Bus1_RxD_3 LOC = T4 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
191NET Bus1_TxD_3 LOC = T3 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
192
193# Bus 2: Trigger-ID to FAD boards
194NET Bus2_Tx_En LOC = K2 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
195NET Bus2_Rx_En LOC = K4 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
196# crate 0
197NET Bus2_RxD_0 LOC = L4 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
198NET Bus2_TxD_0 LOC = M3 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
199# crate 1
200NET Bus2_RxD_1 LOC = N2 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
201NET Bus2_TxD_1 LOC = N1 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
202# crate 2
203NET Bus2_RxD_2 LOC = R2 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
204NET Bus2_TxD_2 LOC = R1 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
205# crate 3
206NET Bus2_RxD_3 LOC = U4 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
207NET Bus2_TxD_3 LOC = U2 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
208
209# auxiliary access
210# NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
211# NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
212# NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable
213# NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary Trigger-ID
214# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
215# NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
216# NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
217
218# Crate-Resets
219# on IO-Bank 3
220#######################################################
221NET Crate_Res0 LOC = M1 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
222NET Crate_Res1 LOC = P1 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
223NET Crate_Res2 LOC = R3 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
224NET Crate_Res3 LOC = V2 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
225
226# Busy signals from the FAD boards
227# on IO-Bank 3
228#######################################################
229NET Busy0 LOC = M4 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
230NET Busy1 LOC = P2 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
231NET Busy2 LOC = R4 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
232NET Busy3 LOC = U1 |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
233
234# NIM outputs
235# on IO-Bank 0
236# LVDS output at the FPGA followed by LVDS to NIM
237# conversion stage
238#######################################################
239# calibration
240# NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1+
241# NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1-
242# NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2+
243# NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2-
244# auxiliarry / spare NIM outputs
245# NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0+
246# NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0-
247# NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # NIM_Out1+
248# NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out1-
249
250# fast control signal outputs
251# LVDS output at the FPGA followed by LVDS to NIM
252# conversion stage
253#######################################################
254NET RES_p LOC = D16 |IOSTANDARD=LVDS_33; # RES+ Reset
255NET RES_n LOC = C15 |IOSTANDARD=LVDS_33; # RES- IO-Bank 0
256NET TRG_p LOC = B15 |IOSTANDARD=LVDS_33; # TRG+ Trigger
257NET TRG_n LOC = A15 |IOSTANDARD=LVDS_33; # TRG- IO-Bank 0
258NET TIM_Run_p LOC = AF25 |IOSTANDARD=LVDS_33; # TIM_Run+ Time Marker
259NET TIM_Run_n LOC = AE25 |IOSTANDARD=LVDS_33; # TIM_Run- on IO-Bank2
260NET TIM_Sel LOC = AD22 |IOSTANDARD=LVCMOS33; # Time Marker selector IO-Bank 2
261# NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA
262
263# LVDS calibration outputs
264# on IO-Bank 0
265#######################################################
266# to connector J13
267NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33; # Cal_0+
268NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33; # Cal_0-
269NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33; # Cal_1+
270NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33; # Cal_1-
271NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33; # Cal_2+
272NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33; # Cal_2-
273NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33; # Cal_3+
274NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33; # Cal_3-
275# to connector J12
276NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33; # Cal_4+
277NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33; # Cal_4-
278NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33; # Cal_5+
279NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33; # Cal_5-
280NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33; # Cal_6+
281NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33; # Cal_6-
282NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33; # Cal_7+
283NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33; # Cal_7-
284
285# Testpoints
286######################################################
287# Connector T7
288# IO-Bank 0
289NET TP<0> LOC = B14 |IOSTANDARD=LVCMOS33; #
290NET TP<1> LOC = A14 |IOSTANDARD=LVCMOS33; #
291NET TP<2> LOC = C13 |IOSTANDARD=LVCMOS33; #
292NET TP<3> LOC = B13 |IOSTANDARD=LVCMOS33; #
293# Connector T10
294# IO-Bank 0
295NET TP<4> LOC = D13 |IOSTANDARD=LVCMOS33; #
296NET TP<5> LOC = C12 |IOSTANDARD=LVCMOS33; #
297NET TP<6> LOC = B12 |IOSTANDARD=LVCMOS33; #
298NET TP<7> LOC = A12 |IOSTANDARD=LVCMOS33; #
299# on Connector T12
300# IO-Bank 0
301NET TP<8> LOC = D11 |IOSTANDARD=LVCMOS33; #
302NET TP<9> LOC = C11 |IOSTANDARD=LVCMOS33; #
303# on Connector T14
304# IO-Bank 0
305NET TP<10> LOC = D10 |IOSTANDARD=LVCMOS33; #
306NET TP<11> LOC = C10 |IOSTANDARD=LVCMOS33; #
307NET TP<12> LOC = A10 |IOSTANDARD=LVCMOS33; #
308NET TP<13> LOC = B10 |IOSTANDARD=LVCMOS33; #
309# on Connector T16
310# IO-Bank 0
311NET TP<14> LOC = A9 |IOSTANDARD=LVCMOS33; #
312NET TP<15> LOC = B9 |IOSTANDARD=LVCMOS33; #
313NET TP<16> LOC = A8 |IOSTANDARD=LVCMOS33; #
314NET TP<17> LOC = B8 |IOSTANDARD=LVCMOS33; #
315# on Connector T8
316# IO-Bank 0
317NET TP<18> LOC = C8 |IOSTANDARD=LVCMOS33; #
318NET TP<19> LOC = D8 |IOSTANDARD=LVCMOS33; #
319NET TP<20> LOC = C6 |IOSTANDARD=LVCMOS33; #
320NET TP<21> LOC = B6 |IOSTANDARD=LVCMOS33; #
321# on Connector T9
322# IO-Bank 0
323NET TP<22> LOC = C7 |IOSTANDARD=LVCMOS33; #
324NET TP<23> LOC = B7 |IOSTANDARD=LVCMOS33; #
325# on Connector T11
326# IO-Bank 3
327NET TP<24> LOC = Y1 |IOSTANDARD=LVCMOS33; #
328NET TP<25> LOC = AA3 |IOSTANDARD=LVCMOS33; #
329NET TP<26> LOC = AA2 |IOSTANDARD=LVCMOS33; #
330NET TP<27> LOC = AC1 |IOSTANDARD=LVCMOS33; #
331# on Connector T13
332# IO-Bank 3
333NET TP<28> LOC = AB1 |IOSTANDARD=LVCMOS33; #
334NET TP<29> LOC = AC3 |IOSTANDARD=LVCMOS33; #
335NET TP<30> LOC = AC2 |IOSTANDARD=LVCMOS33; #
336NET TP<31> LOC = AD2 |IOSTANDARD=LVCMOS33; #
337# on Connector T15
338NET TP<32> LOC = AD1 |IOSTANDARD=LVCMOS33; # IO-Bank 3
339# NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only
340# NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only
341
342# Board ID - inputs
343# local board-ID "solder programmable"
344# all on 'input only' pins
345#######################################################
346# NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; #
347# NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; #
348# NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; #
349# NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; #
350# NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; #
351# NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; #
352# NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; #
353# NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; #
354
355NET "clk" TNM_NET = clk;
356TIMESPEC TS_clk = PERIOD "clk" 25 ns HIGH 50%;
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