source: firmware/FTM/ftm_definitions.vhd@ 10352

Last change on this file since 10352 was 10328, checked in by weitzel, 14 years ago
changes in FTM firmware to debug rates readout, clock conditioner added
File size: 18.3 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: February 2011
6-- Design Name:
7-- Module Name: ftm_definitions
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: library file for FTM design
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19-- modified: Patrick Vogler, February 17 2011
20-- merged with library file from Dortmund, Q. Weitzel, February 24, 2011
21--
22-- kw 25.02.: changes for HDL-Designer (use FACT_FTM.lib.ftm_...),
23-- DD_BLOCK_SIZE added (set to 0x008 for first tests), SD_ADDR_coin_win_[p,c] defined
24--
25-- modified: Quirin Weitzel, March 14 2011
26-- second merger with library file from dortmund (changes below)
27-- kw 01.03.: added array sd_block_default_ftu_active_list (type and defaults)
28-- kw 02.03.: added DD_BLOCK_SIZE_GENERAL (on-time counter + temperatures), changed DD_BLOCK_SIZE to 0x010 for testing
29-- kw 03.03.: added FTM_HEADER_LENGTH
30--
31----------------------------------------------------------------------------------
32
33
34library IEEE;
35use IEEE.STD_LOGIC_1164.all;
36use IEEE.STD_LOGIC_ARITH.ALL;
37use IEEE.STD_LOGIC_UNSIGNED.ALL;
38use IEEE.NUMERIC_STD.ALL;
39
40package ftm_array_types is
41
42 -- !!! some arrays are also defined in the ftm_constants package !!!
43
44 -- data arrays for a single FTU
45 type FTU_enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
46 type FTU_dac_array_type is array (0 to 4) of std_logic_vector(15 downto 0);
47 type FTU_rate_array_type is array (0 to 4) of std_logic_vector(31 downto 0);
48 type active_FTU_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
49 type FTU_answer_array_type is array (0 to 3) of integer range 0 to 10;
50
51 -- data array for clock conditioner interface
52 type clk_cond_array_type is array (0 to 14) of std_logic_vector (31 downto 0);
53
54 -- network array types
55 type ip_type is array (0 to 3) of integer;
56 type mac_type is array (0 to 2) of std_logic_vector (15 downto 0);
57
58 -- Temperature Sensor interface
59 type sensor_array_type is array (0 to 3) of integer range 0 to 2**16 - 1;
60
61end ftm_array_types;
62
63
64library IEEE;
65use IEEE.STD_LOGIC_1164.all;
66use IEEE.STD_LOGIC_ARITH.ALL;
67use IEEE.STD_LOGIC_UNSIGNED.ALL;
68-- for HDL-Designer
69-- LIBRARY FACT_FTM_lib;
70-- use FACT_FTM_lib.ftm_array_types.all;
71library ftm_definitions;
72use ftm_definitions.ftm_array_types.all;
73use IEEE.NUMERIC_STD.ALL;
74
75package ftm_constants is
76
77 -- !!! many constants depend on each other or are defined 2x with different types !!!
78
79 constant NO_OF_CRATES : integer := 4;
80 constant NO_OF_FTUS_PER_CRATE : integer := 10;
81 constant NO_OF_FTU_ENABLE_REG : integer := 4;
82 constant NO_OF_FTU_DAC_REG : integer := 5;
83
84 --internal FPGA clock frequencies
85 constant INT_CLK_FREQUENCY_1 : integer := 50000000; -- 50MHz
86 constant INT_CLK_FREQUENCY_2 : integer := 250000000; -- 250MHz
87 constant LOW_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY_1
88 --constant SCALER_FREQ_DIVIDER : integer := 10000; -- for simulation, should normally be 1
89 constant SCALER_FREQ_DIVIDER : integer := 1;
90
91 --FTM address and firmware ID
92 constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192
93 constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "00000001"; -- firmware version
94
95 --communication with FTUs
96 constant FTU_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case
97 constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 1000; -- 2ms @ 50MHz (100000 clk periods)
98 --constant FTU_RS485_BAUD_RATE : integer := 10000000; -- for simulation
99 --constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 40000; -- for simulation
100 constant FTU_RS485_NO_OF_RETRY : integer range 0 to 2 := 2; -- in case of timeout, !!! HAS TO BE < 3 !!!
101 constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol
102 constant FTU_RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter "@"
103
104 --CRC setup
105 constant CRC_POLYNOMIAL : std_logic_vector(7 downto 0) := "00000111"; -- 8-CCITT
106 constant CRC_INIT_VALUE : std_logic_vector(7 downto 0) := "11111111";
107
108 --DNA identifier for simulation
109 constant DNA_FOR_SIM : bit_vector := X"01710000E0000501";
110
111 -- Clock conditioner (LMK03000, National semiconductor) interface
112 constant MICROWIRE_CLK_FREQUENCY : integer := 2000000; -- 2 MHz
113 -- value to be written to R0 of the LMK03000 to perform a reset, see LMK03000 datasheet
114 constant LMK03000_Reset : std_logic_vector (31 downto 0) := x"80000000";
115 constant LMK03000_REGISTER_WIDTH : integer := 32;
116 constant LMK03000_REGISTER_COUNT : integer := 15; -- number of registers to be programmed in the LMK03000 including reset
117 constant cc_R2_const : std_logic_vector := X"00000102"; -- unused
118 constant cc_R3_const : std_logic_vector := X"00000103"; -- channels
119 constant cc_R4_const : std_logic_vector := X"00000104";
120 constant cc_R5_const : std_logic_vector := X"00000105";
121 constant cc_R6_const : std_logic_vector := X"00000106";
122 constant cc_R7_const : std_logic_vector := X"00000107";
123
124 -- network settings Dortmund
125 -- constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"95A0");
126 -- constant NETMASK : ip_type := (255, 255, 255, 0);
127 -- constant IP_ADDRESS : ip_type := (129, 217, 160, 118);
128 -- constant GATEWAY : ip_type := (129, 217, 160, 1);
129 -- constant FIRST_PORT : integer := 5000;
130
131 -- network settings Zuerich
132 constant MAC_ADDRESS : mac_type := (X"FAC7", X"0FAD", X"1101");
133 constant NETMASK : ip_type := (255, 255, 248, 0);
134 constant IP_ADDRESS : ip_type := (192, 33, 99, 246);
135 constant GATEWAY : ip_type := (192, 33, 96, 1);
136 constant FIRST_PORT : integer := 5000;
137
138 -- W5300 settings
139 constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset
140 -- W5300 Registers
141 constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0');
142 constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0";
143 constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2";
144 constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4";
145 constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8";
146 constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10";
147 constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14";
148 constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18";
149 constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C";
150 constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E";
151 constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20";
152 constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22";
153 constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24";
154 constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26";
155 constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28";
156 constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A";
157 constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C";
158 constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E";
159 constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30";
160 constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0";
161 constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2";
162 constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4";
163 constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6";
164 constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8";
165 constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A";
166 constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12";
167 constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14";
168 constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20";
169 constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24";
170 constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28";
171 constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E";
172 constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30";
173 -- End W5300 registers
174 constant W5300_TX_FIFO_SIZE_8B : integer := 65536; -- Socket TX FIFO-Size in Bytes
175 constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words
176 constant W5300_LAST_SOCKET : integer := 0;
177
178 -- Commands
179 constant CMD_START_DELIMITER : std_logic_vector := X"0040"; -- "@"
180 constant CMD_TLED : std_logic_vector := X"C000"; -- only a test
181 constant CMD_READ : std_logic_vector := X"0001";
182 constant PAR_READ_SD : std_logic_vector := X"0001"; -- read static data block
183 constant PAR_READ_DD : std_logic_vector := X"0002"; -- read dynamic data block
184 -- only for debugging: data_block (0) = ADDR
185 constant PAR_READ_SD_ADDR : std_logic_vector := X"0004"; -- read from address in static data block
186 constant PAR_READ_DD_ADDR : std_logic_vector := X"0008"; -- read from address in dynamic data block
187 constant CMD_WRITE : std_logic_vector := X"0002";
188 constant PAR_WRITE_SD : std_logic_vector := X"0001"; -- write static data block
189 -- only for debugging: data_block (0) = ADDR, data_block (1) = DATA
190 constant PAR_WRITE_SD_ADDR : std_logic_vector := X"0002"; -- write to address in static data ram
191 -- ping all FTUs
192 constant CMD_PING : std_logic_vector := X"0010"; -- ping all FTUs
193
194 -- header length of data packages
195 constant FTM_HEADER_LENGTH : std_logic_vector (7 DOWNTO 0) := X"0B";
196
197 -- FTU-list parameters
198 constant FL_BLOCK_SIZE : std_logic_vector := X"0F9"; -- FTU-list size -- 9 + (40 * 6) = 249
199 constant NO_OF_FTU_LIST_REG : integer := 6;
200 constant FTU_LIST_RAM_OFFSET : integer := 16#009#;
201 constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12;
202
203 -- Static data block
204 constant SD_BLOCK_SIZE_GENERAL : integer := 32; -- X"20" -- static data block size without FTU data
205 constant SD_FTU_BASE_ADDR : std_logic_vector := X"020"; -- beginning of FTU data
206 constant STATIC_RAM_CFG_FTU_OFFSET : integer := 16#020#;
207 constant STATIC_RAM_ADDR_WIDTH : integer := 12;
208 constant SD_FTU_DATA_SIZE : integer := 10; -- X"00A" -- size of one FTU data block
209 constant SD_FTU_NUM : integer := 40; -- number of FTUs
210 constant SD_FTU_ACTIVE_BASE_ADDR : std_logic_vector := X"1B0"; -- beginning of active FTU lists
211 constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3)
212 constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block
213
214 -- dynamic data block
215 --constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"010"; -- 7 + (40 * 12) = 0x1E7 --total size of dynamic data block
216 constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1E7"; -- 7 + (40 * 12) = 0x1E7 --total size of dynamic data block
217 constant DD_BLOCK_SIZE_GENERAL : integer := 7; -- dynamic block size without FTU data
218
219 -- addresses in static data block
220 constant SD_ADDR_general_settings : std_logic_vector := X"000";
221 constant SD_ADDR_led : std_logic_vector := X"001";
222 constant SD_ADDR_lp_pt_freq : std_logic_vector := X"002";
223 constant SD_ADDR_lp_pt_ratio : std_logic_vector := X"003";
224 constant SD_ADDR_lp1_amplitude : std_logic_vector := X"004";
225 constant SD_ADDR_lp2_amplitude : std_logic_vector := X"005";
226 constant SD_ADDR_lp1_delay : std_logic_vector := X"006";
227 constant SD_ADDR_lp2_delay : std_logic_vector := X"007";
228 constant SD_ADDR_coin_n_p : std_logic_vector := X"008";
229 constant SD_ADDR_coin_n_c : std_logic_vector := X"009";
230 constant SD_ADDR_trigger_delay : std_logic_vector := X"00A";
231 constant SD_ADDR_timemarker_delay : std_logic_vector := X"00B";
232 constant SD_ADDR_dead_time : std_logic_vector := X"00C";
233 constant SD_ADDR_cc_R0_HI : std_logic_vector := X"00D";
234 constant SD_ADDR_cc_R0_LO : std_logic_vector := X"00E";
235 constant SD_ADDR_cc_R1_HI : std_logic_vector := X"00F";
236 constant SD_ADDR_cc_R1_LO : std_logic_vector := X"010";
237 constant SD_ADDR_cc_R8_HI : std_logic_vector := X"011";
238 constant SD_ADDR_cc_R8_LO : std_logic_vector := X"012";
239 constant SD_ADDR_cc_R9_HI : std_logic_vector := X"013";
240 constant SD_ADDR_cc_R9_LO : std_logic_vector := X"014";
241 constant SD_ADDR_cc_R11_HI : std_logic_vector := X"015";
242 constant SD_ADDR_cc_R11_LO : std_logic_vector := X"016";
243 constant SD_ADDR_cc_R13_HI : std_logic_vector := X"017";
244 constant SD_ADDR_cc_R13_LO : std_logic_vector := X"018";
245 constant SD_ADDR_cc_R14_HI : std_logic_vector := X"019";
246 constant SD_ADDR_cc_R14_LO : std_logic_vector := X"01A";
247 constant SD_ADDR_cc_R15_HI : std_logic_vector := X"01B";
248 constant SD_ADDR_cc_R15_LO : std_logic_vector := X"01C";
249 constant SD_ADDR_coin_win_p : std_logic_vector := X"01D";
250 constant SD_ADDR_coin_win_c : std_logic_vector := X"01E";
251 constant SD_ADDR_ftu_active_cr0 : std_logic_vector := X"1B0";
252 constant SD_ADDR_ftu_active_cr1 : std_logic_vector := X"1B1";
253 constant SD_ADDR_ftu_active_cr2 : std_logic_vector := X"1B2";
254 constant SD_ADDR_ftu_active_cr3 : std_logic_vector := X"1B3";
255 constant STATIC_RAM_ACT_FTU_OFFSET : integer := 16#1B0#;
256
257
258 -- arrays for default values
259 type sd_block_default_array_type is array (0 to (SD_BLOCK_SIZE_GENERAL - 1)) of std_logic_vector (15 downto 0);
260 type sd_block_ftu_default_array_type is array (0 to (SD_FTU_DATA_SIZE - 1)) of std_logic_vector (15 downto 0);
261 type sd_block_default_ftu_active_list_type is array (0 to (SD_FTU_ACTIVE_NUM - 1)) of std_logic_vector (15 downto 0);
262
263 -- general default values
264 -- !!! to be defined !!!
265 constant sd_block_default_array : sd_block_default_array_type := (
266 X"0000", -- SD_ADDR_general_settings -- general settings
267 X"0000", -- SD_ADDR_led -- on-board status LEDs
268 X"0002", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency
269 X"0003", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers
270 X"0004", -- SD_ADDR_lp1_amplitude -- light pulser 1 amplitude
271 X"0005", -- SD_ADDR_lp2_amplitude -- light pulser 2 amplitude
272 X"0006", -- SD_ADDR_lp1_delay -- light pulser 1 delay
273 X"0007", -- SD_ADDR_lp2_delay -- light pulser 2 delay
274 X"0008", -- SD_ADDR_coin_n_p -- majority coincidence n (for physics)
275 X"0009", -- SD_ADDR_coin_n_c -- majority coincidence n (for calibration)
276 X"000A", -- SD_ADDR_trigger_delay -- trigger delay
277 X"000B", -- SD_ADDR_timemarker_delay -- timemarker delay
278 X"000C", -- SD_ADDR_dead_time -- dead time
279 X"0003", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16
280 X"8000", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0
281 X"0001", -- SD_ADDR_cc_R1_HI -- clock conditioner R1 bits 31...16
282 X"0101", -- SD_ADDR_cc_R1_LO -- clock conditioner R1 bits 15...0
283 X"1000", -- SD_ADDR_cc_R8_HI -- clock conditioner R8 bits 31...16
284 X"0908", -- SD_ADDR_cc_R8_LO -- clock conditioner R8 bits 15...0
285 X"A003", -- SD_ADDR_cc_R9_HI -- clock conditioner R9 bits 31...16
286 X"2A09", -- SD_ADDR_cc_R9_LO -- clock conditioner R9 bits 15...0
287 X"0082", -- SD_ADDR_cc_R11_HI -- clock conditioner R11 bits 31...16
288 X"000B", -- SD_ADDR_cc_R11_LO -- clock conditioner R11 bits 15...0
289 X"020A", -- SD_ADDR_cc_R13_HI -- clock conditioner R13 bits 31...16
290 X"000D", -- SD_ADDR_cc_R13_LO -- clock conditioner R13 bits 15...0
291 X"0830", -- SD_ADDR_cc_R14_HI -- clock conditioner R14 bits 31...16
292 X"280E", -- SD_ADDR_cc_R14_LO -- clock conditioner R14 bits 15...0
293 X"1400", -- SD_ADDR_cc_R15_HI -- clock conditioner R15 bits 31...16
294 X"FA0F", -- SD_ADDR_cc_R15_LO -- clock conditioner R15 bits 15...0
295 X"001D", -- SD_ADDR_coin_win_p -- majority coincidence window (for physics)
296 X"001E", -- SD_ADDR_coin_win_c -- majority coincidence window (for calibration)
297 X"001F" -- -- Spare
298 );
299
300 -- default values for all FTUs
301 constant sd_block_ftu_default_array : sd_block_ftu_default_array_type := (
302 X"01FF", -- enables patch 0 board x crate y
303 X"01FF", -- enables patch 1 board x crate y
304 X"01FF", -- enables patch 2 board x crate y
305 X"01FF", -- enables patch 3 board x crate y
306 X"01F4", -- DAC_A board x crate y
307 X"01F4", -- DAC_B board x crate y
308 X"01F4", -- DAC_C board x crate y
309 X"01F4", -- DAC_D board x crate y
310 X"0010", -- DAC_H board x crate y
311 X"0001" -- Prescaling board x crate y
312 );
313
314 --default values for active FTU lists
315 constant sd_block_default_ftu_active_list : sd_block_default_ftu_active_list_type := (
316 X"0001",
317 X"0000",
318 X"0000",
319 X"0000"
320 );
321
322 -- Light pulser interface
323 constant low_PLC : integer := 16; -- minimal pulse duration in units of 4 ns
324 constant width_PLC : integer := 6; -- counter width pulse duration
325
326 -- Timing counter
327-- constant tc_width : integer := 48; -- width (number of bits) of timing counter
328-- constant zero : unsigned (tc_width - 1 downto 0) := (others => '0');
329
330end ftm_constants;
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