1  


2   Company: ETH Zurich, Institute for Particle Physics


3   Engineer: Q. Weitzel


4  


5   Create Date: February 2011


6   Design Name:


7   Module Name: ftm_definitions


8   Project Name:


9   Target Devices:


10   Tool versions:


11   Description: library file for FTM design


12  


13   Dependencies:


14  


15   Revision:


16   Revision 0.01  File Created


17   Additional Comments:


18  


19   modified: Patrick Vogler, February 17 2011


20   merged with library file from Dortmund, Q. Weitzel, February 24, 2011


21  


22   kw 25.02.: changes for HDLDesigner (use FACT_FTM.lib.ftm_...),


23   DD_BLOCK_SIZE added (set to 0x008 for first tests), SD_ADDR_coin_win_[p,c] defined


24  


25   modified: Quirin Weitzel, March 14 2011


26   second merger with library file from dortmund (changes below)


27   kw 01.03.: added array sd_block_default_ftu_active_list (type and defaults)


28   kw 02.03.: added DD_BLOCK_SIZE_GENERAL (ontime counter + temperatures), changed DD_BLOCK_SIZE to 0x010 for testing


29   kw 03.03.: added FTM_HEADER_LENGTH


30  


31   modified: Quirin Weitzel, March 14 2011


32   third merger with library file from dortmund (changes below)


33   kw 22.03.: added FTU_ERROR_LENGTH


34   kw 30.03.: added CMD_AUTOSEND, PAR_AUTOSEND_EA, PAR_AUTOSEND_DA


35  


36  kw 11.04.: added SD_ADDR_ftu_prescaling_0


37  


38  


39 


40 


41  library IEEE;


42  use IEEE.STD_LOGIC_1164.all;


43  use IEEE.STD_LOGIC_ARITH.ALL;


44  use IEEE.STD_LOGIC_UNSIGNED.ALL;


45  use IEEE.NUMERIC_STD.ALL;


46 


47  package ftm_array_types is


48 


49   !!! some arrays are also defined in the ftm_constants package !!!


50 


51   data arrays for a single FTU


52  type FTU_enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0);


53  type FTU_dac_array_type is array (0 to 4) of std_logic_vector(15 downto 0);


54  type FTU_rate_array_type is array (0 to 4) of std_logic_vector(31 downto 0);


55  type active_FTU_array_type is array (0 to 3) of std_logic_vector(15 downto 0);


56  type FTU_answer_array_type is array (0 to 3) of integer range 0 to 10;


57 


58   data array for clock conditioner interface


59  type clk_cond_array_type is array (0 to 14) of std_logic_vector (31 downto 0);


60 


61   network array types


62  type ip_type is array (0 to 3) of integer;


63  type mac_type is array (0 to 2) of std_logic_vector (15 downto 0);


64 


65   Temperature Sensor interface


66  type sensor_array_type is array (0 to 3) of integer range 0 to 2**16  1;


67 


68  end ftm_array_types;


69 


70 


71  library IEEE;


72  use IEEE.STD_LOGIC_1164.all;


73  use IEEE.STD_LOGIC_ARITH.ALL;


74  use IEEE.STD_LOGIC_UNSIGNED.ALL;


75   for HDLDesigner


76   LIBRARY FACT_FTM_lib;


77   use FACT_FTM_lib.ftm_array_types.all;


78  library ftm_definitions;


79  use ftm_definitions.ftm_array_types.all;


80  use IEEE.NUMERIC_STD.ALL;


81  use ieee.math_real.all;


82 


83  package ftm_constants is


84 


85   !!! many constants depend on each other or are defined 2x with different types !!!


86 


87  constant NO_OF_CRATES : integer := 4;


88  constant NO_OF_FTUS_PER_CRATE : integer := 10;


89  constant NO_OF_FTU_ENABLE_REG : integer := 4;


90  constant NO_OF_FTU_DAC_REG : integer := 5;


91 


92  internal FPGA clock frequencies


93  constant INT_CLK_FREQUENCY_1 : integer := 50000000;  50MHz


94  constant INT_CLK_FREQUENCY_2 : integer := 250000000;  250MHz


95  constant LOW_FREQUENCY : integer := 1000000;  has to be smaller than INT_CLK_FREQUENCY_1


96  constant SCALER_FREQ_DIVIDER : integer := 10000;  for simulation, should normally be 1


97  constant SCALER_FREQ_DIVIDER : integer := 1;


98 


99  FTM address and firmware ID


100  constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000";  192


101  constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "00000001";  firmware version


102 


103  communication with FTUs


104  constant FTU_RS485_BAUD_RATE : integer := 250000;  bits / sec in our case


105  constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 1000;  2ms @ 50MHz (100000 clk periods)


106  constant FTU_RS485_BAUD_RATE : integer := 10000000;  for simulation


107  constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 40000;  for simulation


108  constant FTU_RS485_NO_OF_RETRY : integer range 0 to 2 := 2;  in case of timeout, !!! HAS TO BE < 3 !!!


109  constant FTU_RS485_BLOCK_WIDTH : integer := 224;  28 byte protocol


110  constant FTU_RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000";  start delimiter "@"


111 


112  CRC setup


113  constant CRC_POLYNOMIAL : std_logic_vector(7 downto 0) := "00000111";  8CCITT


114  constant CRC_INIT_VALUE : std_logic_vector(7 downto 0) := "11111111";


115 


116  DNA identifier for simulation


117  constant DNA_FOR_SIM : bit_vector := X"01710000E0000501";


118 


119   Clock conditioner (LMK03000, National semiconductor) interface


120  constant MICROWIRE_CLK_FREQUENCY : integer := 2000000;  2 MHz


121   value to be written to R0 of the LMK03000 to perform a reset, see LMK03000 datasheet


122  constant LMK03000_Reset : std_logic_vector (31 downto 0) := x"80000000";


123  constant LMK03000_REGISTER_WIDTH : integer := 32;


124  constant LMK03000_REGISTER_COUNT : integer := 15;  number of registers to be programmed in the LMK03000 including reset


125  constant cc_R2_const : std_logic_vector := X"00000102";  unused


126  constant cc_R3_const : std_logic_vector := X"00000103";  channels


127  constant cc_R4_const : std_logic_vector := X"00000104";


128  constant cc_R5_const : std_logic_vector := X"00000105";


129  constant cc_R6_const : std_logic_vector := X"00000106";


130  constant cc_R7_const : std_logic_vector := X"00000107";


131 


132   network settings Dortmund


133   constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"95A0");


134   constant NETMASK : ip_type := (255, 255, 255, 0);


135   constant IP_ADDRESS : ip_type := (129, 217, 160, 118);


136   constant GATEWAY : ip_type := (129, 217, 160, 1);


137   constant FIRST_PORT : integer := 5000;


138 


139   network settings Zuerich


140  constant MAC_ADDRESS : mac_type := (X"FAC7", X"0FAD", X"1101");


141  constant NETMASK : ip_type := (255, 255, 248, 0);


142  constant IP_ADDRESS : ip_type := (192, 33, 99, 246);


143  constant GATEWAY : ip_type := (192, 33, 96, 1);


144  constant FIRST_PORT : integer := 5000;


145 


146   W5300 settings


147  constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000";  socket address offset


148   W5300 Registers


149  constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0');


150  constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0";


151  constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2";


152  constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4";


153  constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8";


154  constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10";


155  constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14";


156  constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18";


157  constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C";


158  constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E";


159  constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20";


160  constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22";


161  constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24";


162  constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26";


163  constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28";


164  constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A";


165  constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C";


166  constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E";


167  constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30";


168  constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0";


169  constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2";


170  constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4";


171  constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6";


172  constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8";


173  constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A";


174  constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12";


175  constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14";


176  constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20";


177  constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24";


178  constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28";


179  constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E";


180  constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30";


181   End W5300 registers


182  constant W5300_TX_FIFO_SIZE_8B : integer := 65536;  Socket TX FIFOSize in Bytes


183  constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2);  Socket TX FIFOSize in 16 Bit Words


184  constant W5300_LAST_SOCKET : integer := 0;


185 


186   Commands


187  constant CMD_START_DELIMITER : std_logic_vector := X"0040";  "@"


188  constant CMD_TLED : std_logic_vector := X"C000";  only a test


189  constant CMD_READ : std_logic_vector := X"0001";


190  constant PAR_READ_SD : std_logic_vector := X"0001";  read static data block


191  constant PAR_READ_DD : std_logic_vector := X"0002";  read dynamic data block


192   only for debugging: data_block (0) = ADDR


193  constant PAR_READ_SD_ADDR : std_logic_vector := X"0004";  read from address in static data block


194  constant PAR_READ_DD_ADDR : std_logic_vector := X"0008";  read from address in dynamic data block


195  constant CMD_WRITE : std_logic_vector := X"0002";


196  constant PAR_WRITE_SD : std_logic_vector := X"0001";  write static data block


197   only for debugging: data_block (0) = ADDR, data_block (1) = DATA


198  constant PAR_WRITE_SD_ADDR : std_logic_vector := X"0002";  write to address in static data ram


199   ping all FTUs


200  constant CMD_PING : std_logic_vector := X"0010";  ping all FTUs


201   turn automatic sending of ddblock and ftuerrorlist on or off


202  constant CMD_AUTOSEND : std_logic_vector := X"0020";


203  constant PAR_AUTOSEND_EA : std_logic_vector := X"0001";  enable automatic sending


204  constant PAR_AUTOSEND_DA : std_logic_vector := X"0000";  disable automatic sending


205 


206   header length of data packages


207  constant FTM_HEADER_LENGTH : std_logic_vector (7 DOWNTO 0) := X"0B";


208 


209   FTU error message


210  constant FTU_ERROR_LENGTH : std_logic_vector (11 downto 0) := X"01D"; (number of unsuccessful calls) + (28 * data) = 29


211 


212   FTUlist parameters


213  constant FL_BLOCK_SIZE : std_logic_vector := X"0F9";  FTUlist size  9 + (40 * 6) = 249


214  constant NO_OF_FTU_LIST_REG : integer := 6;


215  constant FTU_LIST_RAM_OFFSET : integer := 16#009#;


216  constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12;


217 


218   Static data block


219  constant SD_BLOCK_SIZE_GENERAL : integer := 32;  X"20"  static data block size without FTU data


220  constant SD_FTU_BASE_ADDR : std_logic_vector := X"020";  beginning of FTU data


221  constant STATIC_RAM_CFG_FTU_OFFSET : integer := 16#020#;


222  constant STATIC_RAM_ADDR_WIDTH : integer := 12;


223  constant SD_FTU_DATA_SIZE : integer := 10;  X"00A"  size of one FTU data block


224  constant SD_FTU_NUM : integer := 40;  number of FTUs


225  constant SD_FTU_ACTIVE_BASE_ADDR : std_logic_vector := X"1B0";  beginning of active FTU lists


226  constant SD_FTU_ACTIVE_NUM : integer := 4;  number of active FTU lists (cr0 to cr3)


227  constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4";  total size of static data block


228 


229   dynamic data block


230  constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"010";  7 + (40 * 12) = 0x1E7 total size of dynamic data block


231  constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1E7";  7 + (40 * 12) = 0x1E7 total size of dynamic data block


232  constant DD_BLOCK_SIZE_GENERAL : integer := 7;  dynamic block size without FTU data


233 


234   addresses in static data block


235  constant SD_ADDR_general_settings : std_logic_vector := X"000";


236  constant SD_ADDR_led : std_logic_vector := X"001";


237  constant SD_ADDR_lp_pt_freq : std_logic_vector := X"002";


238  constant SD_ADDR_lp_pt_ratio : std_logic_vector := X"003";


239  constant SD_ADDR_lp1_amplitude : std_logic_vector := X"004";


240  constant SD_ADDR_lp2_amplitude : std_logic_vector := X"005";


241  constant SD_ADDR_lp1_delay : std_logic_vector := X"006";


242  constant SD_ADDR_lp2_delay : std_logic_vector := X"007";


243  constant SD_ADDR_coin_n_p : std_logic_vector := X"008";


244  constant SD_ADDR_coin_n_c : std_logic_vector := X"009";


245  constant SD_ADDR_trigger_delay : std_logic_vector := X"00A";


246  constant SD_ADDR_timemarker_delay : std_logic_vector := X"00B";


247  constant SD_ADDR_dead_time : std_logic_vector := X"00C";


248  constant SD_ADDR_cc_R0_HI : std_logic_vector := X"00D";


249  constant SD_ADDR_cc_R0_LO : std_logic_vector := X"00E";


250  constant SD_ADDR_cc_R1_HI : std_logic_vector := X"00F";


251  constant SD_ADDR_cc_R1_LO : std_logic_vector := X"010";


252  constant SD_ADDR_cc_R8_HI : std_logic_vector := X"011";


253  constant SD_ADDR_cc_R8_LO : std_logic_vector := X"012";


254  constant SD_ADDR_cc_R9_HI : std_logic_vector := X"013";


255  constant SD_ADDR_cc_R9_LO : std_logic_vector := X"014";


256  constant SD_ADDR_cc_R11_HI : std_logic_vector := X"015";


257  constant SD_ADDR_cc_R11_LO : std_logic_vector := X"016";


258  constant SD_ADDR_cc_R13_HI : std_logic_vector := X"017";


259  constant SD_ADDR_cc_R13_LO : std_logic_vector := X"018";


260  constant SD_ADDR_cc_R14_HI : std_logic_vector := X"019";


261  constant SD_ADDR_cc_R14_LO : std_logic_vector := X"01A";


262  constant SD_ADDR_cc_R15_HI : std_logic_vector := X"01B";


263  constant SD_ADDR_cc_R15_LO : std_logic_vector := X"01C";


264  constant SD_ADDR_coin_win_p : std_logic_vector := X"01D";


265  constant SD_ADDR_coin_win_c : std_logic_vector := X"01E";


266  constant SD_ADDR_ftu_prescaling_0 : std_logic_vector := X"029";


267  constant SD_ADDR_ftu_active_cr0 : std_logic_vector := X"1B0";


268  constant SD_ADDR_ftu_active_cr1 : std_logic_vector := X"1B1";


269  constant SD_ADDR_ftu_active_cr2 : std_logic_vector := X"1B2";


270  constant SD_ADDR_ftu_active_cr3 : std_logic_vector := X"1B3";


271  constant STATIC_RAM_ACT_FTU_OFFSET : integer := 16#1B0#;


272 


273 


274   arrays for default values


275  type sd_block_default_array_type is array (0 to (SD_BLOCK_SIZE_GENERAL  1)) of std_logic_vector (15 downto 0);


276  type sd_block_ftu_default_array_type is array (0 to (SD_FTU_DATA_SIZE  1)) of std_logic_vector (15 downto 0);


277  type sd_block_default_ftu_active_list_type is array (0 to (SD_FTU_ACTIVE_NUM  1)) of std_logic_vector (15 downto 0);


278 


279   general default values


280   !!! to be defined !!!


281  constant sd_block_default_array : sd_block_default_array_type := (


282  X"0080",  SD_ADDR_general_settings  general settings


283  X"0060",  SD_ADDR_general_settings  general settings


284  X"0000",  SD_ADDR_led  onboard status LEDs


285  X"0400",  SD_ADDR_lp_pt_freq  light pulser and pedestal trigger frequency


286  X"0001",  SD_ADDR_lp_pt_freq  light pulser and pedestal trigger frequency


287  X"0001",  SD_ADDR_lp_pt_ratio...  ratio between LP1, LP2 and pedestal triggers


288  X"0420",  SD_ADDR_lp_pt_ratio...  ratio between LP1, LP2 and pedestal triggers


289  X"0004",  SD_ADDR_lp1_amplitude  light pulser 1 amplitude


290  X"0005",  SD_ADDR_lp2_amplitude  light pulser 2 amplitude


291  X"0006",  SD_ADDR_lp1_delay  light pulser 1 delay


292  X"0007",  SD_ADDR_lp2_delay  light pulser 2 delay


293  X"0001",  SD_ADDR_coin_n_p  majority coincidence n (for physics)


294  X"001E",  SD_ADDR_coin_n_c  majority coincidence n (for calibration)


295  X"0000",  SD_ADDR_trigger_delay  trigger delay


296  X"0000",  SD_ADDR_timemarker_delay  timemarker delay


297  X"0019",  SD_ADDR_dead_time  dead time, 8ns + 4x25ns = 108ns


298  X"0000",  SD_ADDR_dead_time  dead time, 8ns + 4x25ns = 108ns


299  X"0003",  SD_ADDR_cc_R0_HI  clock conditioner R0 bits 31...16


300  X"8000",  SD_ADDR_cc_R0_LO  clock conditioner R0 bits 15...0


301  X"0001",  SD_ADDR_cc_R1_HI  clock conditioner R1 bits 31...16


302  X"0101",  SD_ADDR_cc_R1_LO  clock conditioner R1 bits 15...0


303  X"1000",  SD_ADDR_cc_R8_HI  clock conditioner R8 bits 31...16


304  X"0908",  SD_ADDR_cc_R8_LO  clock conditioner R8 bits 15...0


305  X"A003",  SD_ADDR_cc_R9_HI  clock conditioner R9 bits 31...16


306  X"2A09",  SD_ADDR_cc_R9_LO  clock conditioner R9 bits 15...0


307  X"0082",  SD_ADDR_cc_R11_HI  clock conditioner R11 bits 31...16


308  X"000B",  SD_ADDR_cc_R11_LO  clock conditioner R11 bits 15...0


309  X"020A",  SD_ADDR_cc_R13_HI  clock conditioner R13 bits 31...16


310  X"000D",  SD_ADDR_cc_R13_LO  clock conditioner R13 bits 15...0


311  X"0830",  SD_ADDR_cc_R14_HI  clock conditioner R14 bits 31...16


312  X"280E",  SD_ADDR_cc_R14_LO  clock conditioner R14 bits 15...0


313  X"1400",  SD_ADDR_cc_R15_HI  clock conditioner R15 bits 31...16


314  X"FA0F",  SD_ADDR_cc_R15_LO  clock conditioner R15 bits 15...0


315  X"0001",  SD_ADDR_coin_win_p  majority coincidence window (for physics), 8ns + 4x1ns = 12ns


316  X"0001",  SD_ADDR_coin_win_c  majority coincidence window (for calibration), 8ns + 4x1ns = 12ns


317  X"001F"   Spare


318  );


319 


320   default values for all FTUs


321  constant sd_block_ftu_default_array : sd_block_ftu_default_array_type := (


322  X"01FF",  enables patch 0 board x crate y


323  X"01FF",  enables patch 1 board x crate y


324  X"01FF",  enables patch 2 board x crate y


325  X"01FF",  enables patch 3 board x crate y


326  X"01F4",  DAC_A board x crate y


327  X"01F4",  DAC_B board x crate y


328  X"01F4",  DAC_C board x crate y


329  X"01F4",  DAC_D board x crate y


330  X"0010",  DAC_H board x crate y


331  X"0001"  Prescaling board x crate y


332  );


333 


334  default values for active FTU lists


335  constant sd_block_default_ftu_active_list : sd_block_default_ftu_active_list_type := (


336  X"0000",


337  X"0000",


338  X"0000",


339  X"0000"


340  );


341 


342   Light pulser interface


343  constant low_PLC : integer := 16;  minimal pulse duration in units of 4 ns


344  constant width_PLC : integer := 6;  counter width pulse duration


345 


346   Timing counter


347   constant tc_width : integer := 48;  width (number of bits) of timing counter


348   constant zero : unsigned (tc_width  1 downto 0) := (others => '0');


349 


350  ======================================================================================


351   Constants for calibration and pedestal triggers generation


352  ======================================================================================


353  constant LOW_SPEED_CLOCK_FREQ : real := 50000000.0;


354  constant LOW_SPEED_CLOCK_PERIOD : real := 1.0/LOW_SPEED_CLOCK_FREQ;


355  constant MS_PERIOD : real := 0.001;


356  constant MAX_MS_COUNTER_WIDTH : integer := integer(ceil(log2(real(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD))));


357  constant MAX_MS_COUNTER_VAL : integer := integer(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD);


358  ======================================================================================


359 


360  ======================================================================================


361   Constants for trigger and TIM signals width (8ns+value*4ns)


362  ======================================================================================


363  constant TRIG_SIGNAL_PULSE_WIDTH : integer range 0 to 15 := 10;


364  constant TIM_SIGNAL_PULSE_WIDTH : integer range 0 to 15 := 0;


365  ======================================================================================


366 


367  end ftm_constants;

