source: firmware/FTM/ftm_definitions.vhd@ 10454

Last change on this file since 10454 was 10441, checked in by weitzel, 14 years ago
new FTM firmware featuring e.g. start/stop run commands and new header
File size: 22.5 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: February 2011
6-- Design Name:
7-- Module Name: ftm_definitions
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: library file for FTM design
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19-- modified: Patrick Vogler, February 17 2011
20-- merged with library file from Dortmund, Q. Weitzel, February 24, 2011
21--
22-- kw 25.02.: changes for HDL-Designer (use FACT_FTM.lib.ftm_...),
23-- DD_BLOCK_SIZE added (set to 0x008 for first tests), SD_ADDR_coin_win_[p,c] defined
24--
25-- modified: Quirin Weitzel, March 14 2011
26-- second merger with library file from dortmund (changes below)
27-- kw 01.03.: added array sd_block_default_ftu_active_list (type and defaults)
28-- kw 02.03.: added DD_BLOCK_SIZE_GENERAL (on-time counter + temperatures), changed DD_BLOCK_SIZE to 0x010 for testing
29-- kw 03.03.: added FTM_HEADER_LENGTH
30--
31-- modified: Quirin Weitzel, March 14 2011
32-- third merger with library file from dortmund (changes below)
33-- kw 22.03.: added FTU_ERROR_LENGTH
34-- kw 30.03.: added CMD_AUTOSEND, PAR_AUTOSEND_EA, PAR_AUTOSEND_DA
35--
36---kw 11.04.: added SD_ADDR_ftu_prescaling_0
37--
38-- modified: Quirin Weitzel, April 20 2011
39-- next merger with library file from dortmund (changes below)
40-- kw 14.04.: added sensor_array_type (temperature sensors)
41-- changed CMD_AUTOSEND to X"0040"
42-- added "start run / take X events", "stop run", "crate reset"
43-- kw 18.04.: removed PAR_READ_DD_ADDR, changed PAR_WRITE_SD_ADDR to 0x0004
44-- added FTM_PACKAGE_START and FTM_PACKAGE_END
45-- increased DD_BLOCK_SIZE and DD_BLOCK_SIZE_GENERAL by 1 (64 bit on-time counter)
46-- changed FTM_HEADER_LENGTH to 0x0E
47-- kw 20.04.: added "package types", SD_SINGLE_WORD_SIZE
48--
49----------------------------------------------------------------------------------
50
51
52library IEEE;
53use IEEE.STD_LOGIC_1164.all;
54use IEEE.STD_LOGIC_ARITH.ALL;
55use IEEE.STD_LOGIC_UNSIGNED.ALL;
56use IEEE.NUMERIC_STD.ALL;
57
58package ftm_array_types is
59
60 -- !!! some arrays are also defined in the ftm_constants package !!!
61
62 -- data arrays for a single FTU
63 type FTU_enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
64 type FTU_dac_array_type is array (0 to 4) of std_logic_vector(15 downto 0);
65 type FTU_rate_array_type is array (0 to 4) of std_logic_vector(31 downto 0);
66 type active_FTU_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
67 type FTU_answer_array_type is array (0 to 3) of integer range 0 to 10;
68
69 -- data array for clock conditioner interface
70 type clk_cond_array_type is array (0 to 14) of std_logic_vector (31 downto 0);
71
72 -- network array types
73 type ip_type is array (0 to 3) of integer;
74 type mac_type is array (0 to 2) of std_logic_vector (15 downto 0);
75
76 -- Temperature Sensor interface
77 type sensor_array_type is array (0 to 3) of integer range 0 to 2**16 - 1;
78
79end ftm_array_types;
80
81
82library IEEE;
83use IEEE.STD_LOGIC_1164.all;
84use IEEE.STD_LOGIC_ARITH.ALL;
85use IEEE.STD_LOGIC_UNSIGNED.ALL;
86-- for HDL-Designer
87-- LIBRARY FACT_FTM_lib;
88-- use FACT_FTM_lib.ftm_array_types.all;
89library ftm_definitions;
90use ftm_definitions.ftm_array_types.all;
91use IEEE.NUMERIC_STD.ALL;
92use ieee.math_real.all;
93
94package ftm_constants is
95
96 -- !!! many constants depend on each other or are defined 2x with different types !!!
97
98 constant NO_OF_CRATES : integer := 4;
99 constant NO_OF_FTUS_PER_CRATE : integer := 10;
100 constant NO_OF_FTU_ENABLE_REG : integer := 4;
101 constant NO_OF_FTU_DAC_REG : integer := 5;
102
103 --internal FPGA clock frequencies
104 constant INT_CLK_FREQUENCY_1 : integer := 50000000; -- 50MHz
105 constant INT_CLK_FREQUENCY_2 : integer := 250000000; -- 250MHz
106 constant LOW_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY_1
107 --constant SCALER_FREQ_DIVIDER : integer := 10000; -- for simulation, should normally be 1
108 constant SCALER_FREQ_DIVIDER : integer := 1;
109
110 --FTM address and firmware ID
111 constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192
112 constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "00000001"; -- firmware version
113
114 --communication with FTUs
115 constant FTU_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case
116 constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 1000; -- 2ms @ 50MHz (100000 clk periods)
117 --constant FTU_RS485_BAUD_RATE : integer := 10000000; -- for simulation
118 --constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 40000; -- for simulation
119 constant FTU_RS485_NO_OF_RETRY : integer range 0 to 2 := 2; -- in case of timeout, !!! HAS TO BE < 3 !!!
120 constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol
121 constant FTU_RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter "@"
122
123 --broadcast to FADs
124 constant FAD_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case
125 constant FAD_RS485_BLOCK_WIDTH : integer := 56; -- 7 byte trigger ID
126
127 --CRC setup
128 constant CRC_POLYNOMIAL : std_logic_vector(7 downto 0) := "00000111"; -- 8-CCITT
129 constant CRC_INIT_VALUE : std_logic_vector(7 downto 0) := "11111111";
130
131 --DNA identifier for simulation
132 constant DNA_FOR_SIM : bit_vector := X"01710000F0000501";
133
134 -- Clock conditioner (LMK03000, National semiconductor) interface
135 constant MICROWIRE_CLK_FREQUENCY : integer := 2000000; -- 2 MHz
136 -- value to be written to R0 of the LMK03000 to perform a reset, see LMK03000 datasheet
137 constant LMK03000_Reset : std_logic_vector (31 downto 0) := x"80000000";
138 constant LMK03000_REGISTER_WIDTH : integer := 32;
139 constant LMK03000_REGISTER_COUNT : integer := 15; -- number of registers to be programmed in the LMK03000 including reset
140 constant cc_R2_const : std_logic_vector := X"00000102"; -- unused
141 constant cc_R3_const : std_logic_vector := X"00000103"; -- channels
142 constant cc_R4_const : std_logic_vector := X"00000104";
143 constant cc_R5_const : std_logic_vector := X"00000105";
144 constant cc_R6_const : std_logic_vector := X"00000106";
145 constant cc_R7_const : std_logic_vector := X"00000107";
146
147 -- network settings Dortmund
148 -- constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"95A0");
149 -- constant NETMASK : ip_type := (255, 255, 255, 0);
150 -- constant IP_ADDRESS : ip_type := (129, 217, 160, 118);
151 -- constant GATEWAY : ip_type := (129, 217, 160, 1);
152 -- constant FIRST_PORT : integer := 5000;
153
154 -- network settings Zuerich
155 constant MAC_ADDRESS : mac_type := (X"FAC7", X"0FAD", X"1101");
156 constant NETMASK : ip_type := (255, 255, 248, 0);
157 constant IP_ADDRESS : ip_type := (192, 33, 99, 246);
158 constant GATEWAY : ip_type := (192, 33, 96, 1);
159 constant FIRST_PORT : integer := 5000;
160
161 -- W5300 settings
162 constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset
163 -- W5300 Registers
164 constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0');
165 constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0";
166 constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2";
167 constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4";
168 constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8";
169 constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10";
170 constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14";
171 constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18";
172 constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C";
173 constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E";
174 constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20";
175 constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22";
176 constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24";
177 constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26";
178 constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28";
179 constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A";
180 constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C";
181 constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E";
182 constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30";
183 constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0";
184 constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2";
185 constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4";
186 constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6";
187 constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8";
188 constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A";
189 constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12";
190 constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14";
191 constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20";
192 constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24";
193 constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28";
194 constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E";
195 constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30";
196 -- End W5300 registers
197 constant W5300_TX_FIFO_SIZE_8B : integer := 65536; -- Socket TX FIFO-Size in Bytes
198 constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words
199 constant W5300_LAST_SOCKET : integer := 0;
200
201 -- Commands
202 constant CMD_START_DELIMITER : std_logic_vector := X"0040"; -- "@"
203 constant CMD_TLED : std_logic_vector := X"C000"; -- only a test
204 constant CMD_READ : std_logic_vector := X"0001";
205 constant PAR_READ_SD : std_logic_vector := X"0001"; -- read static data block
206 constant PAR_READ_DD : std_logic_vector := X"0002"; -- read dynamic data block
207 -- only for debugging: data_block (0) = ADDR
208 constant PAR_READ_SD_ADDR : std_logic_vector := X"0004"; -- read from address in static data block
209 constant CMD_WRITE : std_logic_vector := X"0002";
210 constant PAR_WRITE_SD : std_logic_vector := X"0001"; -- write static data block
211 -- only for debugging: data_block (0) = ADDR, data_block (1) = DATA
212 constant PAR_WRITE_SD_ADDR : std_logic_vector := X"0004"; -- write to address in static data ram
213 -- ping all FTUs
214 constant CMD_PING : std_logic_vector := X"0010"; -- ping all FTUs
215 -- turn automatic sending of dd-block and ftu-error-list on or off
216 constant CMD_AUTOSEND : std_logic_vector := X"0040";
217 constant PAR_AUTOSEND_EA : std_logic_vector := X"0001"; -- enable automatic sending
218 constant PAR_AUTOSEND_DA : std_logic_vector := X"0000"; -- disable automatic sending
219
220 -- start run / take X events
221 constant CMD_START : std_logic_vector := X"0004";
222 constant PAR_START_RUN : std_logic_vector := X"0001";
223 constant PAR_START_X_EVNTS : std_logic_vector := X"0002";
224
225 -- stop run
226 constant CMD_STOP : std_logic_vector := X"0008";
227
228 -- crate reset
229 constant CMD_CRESET : std_logic_vector := X"0020";
230
231 -- start and end of package
232 constant FTM_PACKAGE_START : std_logic_vector := X"FB01";
233 constant FTM_PACKAGE_END : std_logic_vector := X"04FE";
234
235 -- package types
236 constant FTM_PACKAGE_TYPE_SD : std_logic_vector := X"0001";
237 constant FTM_PACKAGE_TYPE_DD : std_logic_vector := X"0002";
238 constant FTM_PACKAGE_TYPE_FTU_LIST : std_logic_vector := X"0003";
239 constant FTM_PACKAGE_TYPE_FTU_ERR : std_logic_vector := X"0004";
240 constant FTM_PACKAGE_TYPE_SD_WORD : std_logic_vector := X"0005";
241
242 -- state types
243 constant FTM_STATE_IDLE : std_logic_vector := X"0001";
244 constant FTM_STATE_CFG : std_logic_vector := X"0002";
245 constant FTM_STATE_RUN : std_logic_vector := X"0003";
246 constant FTM_STATE_CALIB : std_logic_vector := X"0004";
247
248 -- header length of data packages
249 constant FTM_HEADER_LENGTH : std_logic_vector (7 DOWNTO 0) := X"0E";
250
251 -- FTU error message
252 constant FTU_ERROR_LENGTH : std_logic_vector (11 downto 0) := X"01D"; --(number of unsuccessful calls) + (28 * data) = 29
253
254 -- FTU-list parameters
255 constant FL_BLOCK_SIZE : std_logic_vector := X"0F9"; -- FTU-list size -- 9 + (40 * 6) = 249
256 constant NO_OF_FTU_LIST_REG : integer := 6;
257 constant FTU_LIST_RAM_OFFSET : integer := 16#009#;
258 constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12;
259
260 constant NO_OF_DD_RAM_REG : integer := 12;
261
262 -- Static data block
263 constant SD_BLOCK_SIZE_GENERAL : integer := 32; -- X"20" -- static data block size without FTU data
264 constant SD_FTU_BASE_ADDR : std_logic_vector := X"020"; -- beginning of FTU data
265 constant STATIC_RAM_CFG_FTU_OFFSET : integer := 16#020#;
266 constant STATIC_RAM_ADDR_WIDTH : integer := 12;
267 constant SD_FTU_DATA_SIZE : integer := 10; -- X"00A" -- size of one FTU data block
268 constant SD_FTU_NUM : integer := 40; -- number of FTUs
269 constant SD_FTU_ACTIVE_BASE_ADDR : std_logic_vector := X"1B0"; -- beginning of active FTU lists
270 constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3)
271 constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block
272 constant SD_SINGLE_WORD_SIZE : std_logic_vector := X"001";
273
274 -- dynamic data block
275 constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1E8"; -- 8 + (40 * 12) = 0x1E8 --total size of dynamic data block
276 constant DD_BLOCK_SIZE_GENERAL : integer := 8; -- dynamic block size without FTU data
277 constant DYNAMIC_RAM_ADDR_WIDTH : integer := 12;
278
279 -- addresses in static data block
280 constant SD_ADDR_general_settings : std_logic_vector := X"000";
281 constant SD_ADDR_led : std_logic_vector := X"001";
282 constant SD_ADDR_lp_pt_freq : std_logic_vector := X"002";
283 constant SD_ADDR_lp_pt_ratio : std_logic_vector := X"003";
284 constant SD_ADDR_lp1_amplitude : std_logic_vector := X"004";
285 constant SD_ADDR_lp2_amplitude : std_logic_vector := X"005";
286 constant SD_ADDR_lp1_delay : std_logic_vector := X"006";
287 constant SD_ADDR_lp2_delay : std_logic_vector := X"007";
288 constant SD_ADDR_coin_n_p : std_logic_vector := X"008";
289 constant SD_ADDR_coin_n_c : std_logic_vector := X"009";
290 constant SD_ADDR_trigger_delay : std_logic_vector := X"00A";
291 constant SD_ADDR_timemarker_delay : std_logic_vector := X"00B";
292 constant SD_ADDR_dead_time : std_logic_vector := X"00C";
293 constant SD_ADDR_cc_R0_HI : std_logic_vector := X"00D";
294 constant SD_ADDR_cc_R0_LO : std_logic_vector := X"00E";
295 constant SD_ADDR_cc_R1_HI : std_logic_vector := X"00F";
296 constant SD_ADDR_cc_R1_LO : std_logic_vector := X"010";
297 constant SD_ADDR_cc_R8_HI : std_logic_vector := X"011";
298 constant SD_ADDR_cc_R8_LO : std_logic_vector := X"012";
299 constant SD_ADDR_cc_R9_HI : std_logic_vector := X"013";
300 constant SD_ADDR_cc_R9_LO : std_logic_vector := X"014";
301 constant SD_ADDR_cc_R11_HI : std_logic_vector := X"015";
302 constant SD_ADDR_cc_R11_LO : std_logic_vector := X"016";
303 constant SD_ADDR_cc_R13_HI : std_logic_vector := X"017";
304 constant SD_ADDR_cc_R13_LO : std_logic_vector := X"018";
305 constant SD_ADDR_cc_R14_HI : std_logic_vector := X"019";
306 constant SD_ADDR_cc_R14_LO : std_logic_vector := X"01A";
307 constant SD_ADDR_cc_R15_HI : std_logic_vector := X"01B";
308 constant SD_ADDR_cc_R15_LO : std_logic_vector := X"01C";
309 constant SD_ADDR_coin_win_p : std_logic_vector := X"01D";
310 constant SD_ADDR_coin_win_c : std_logic_vector := X"01E";
311 constant SD_ADDR_ftu_prescaling_0 : std_logic_vector := X"029";
312 constant SD_ADDR_ftu_active_cr0 : std_logic_vector := X"1B0";
313 constant SD_ADDR_ftu_active_cr1 : std_logic_vector := X"1B1";
314 constant SD_ADDR_ftu_active_cr2 : std_logic_vector := X"1B2";
315 constant SD_ADDR_ftu_active_cr3 : std_logic_vector := X"1B3";
316 constant STATIC_RAM_ACT_FTU_OFFSET : integer := 16#1B0#;
317
318
319 -- arrays for default values
320 type sd_block_default_array_type is array (0 to (SD_BLOCK_SIZE_GENERAL - 1)) of std_logic_vector (15 downto 0);
321 type sd_block_ftu_default_array_type is array (0 to (SD_FTU_DATA_SIZE - 1)) of std_logic_vector (15 downto 0);
322 type sd_block_default_ftu_active_list_type is array (0 to (SD_FTU_ACTIVE_NUM - 1)) of std_logic_vector (15 downto 0);
323
324 -- general default values
325 -- !!! to be defined !!!
326 constant sd_block_default_array : sd_block_default_array_type := (
327 X"0080", -- SD_ADDR_general_settings -- general settings
328 --X"0010", -- SD_ADDR_general_settings -- general settings
329 X"0000", -- SD_ADDR_led -- on-board status LEDs
330 X"03FF", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency
331 --X"0001", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency
332 --X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers
333 X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers
334 X"0004", -- SD_ADDR_lp1_amplitude -- light pulser 1 amplitude
335 X"0005", -- SD_ADDR_lp2_amplitude -- light pulser 2 amplitude
336 X"0006", -- SD_ADDR_lp1_delay -- light pulser 1 delay
337 X"0007", -- SD_ADDR_lp2_delay -- light pulser 2 delay
338 X"0001", -- SD_ADDR_coin_n_p -- majority coincidence n (for physics)
339 X"001E", -- SD_ADDR_coin_n_c -- majority coincidence n (for calibration)
340 X"0000", -- SD_ADDR_trigger_delay -- trigger delay
341 X"0000", -- SD_ADDR_timemarker_delay -- timemarker delay
342 X"0017", -- SD_ADDR_dead_time -- dead time, 8ns + 4x23ns = 100ns
343 --X"0000", -- SD_ADDR_dead_time -- dead time, 8ns + 4x25ns = 108ns
344 X"0003", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16
345 X"8000", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0
346 X"0001", -- SD_ADDR_cc_R1_HI -- clock conditioner R1 bits 31...16
347 X"0101", -- SD_ADDR_cc_R1_LO -- clock conditioner R1 bits 15...0
348 X"1000", -- SD_ADDR_cc_R8_HI -- clock conditioner R8 bits 31...16
349 X"0908", -- SD_ADDR_cc_R8_LO -- clock conditioner R8 bits 15...0
350 X"A003", -- SD_ADDR_cc_R9_HI -- clock conditioner R9 bits 31...16
351 X"2A09", -- SD_ADDR_cc_R9_LO -- clock conditioner R9 bits 15...0
352 X"0082", -- SD_ADDR_cc_R11_HI -- clock conditioner R11 bits 31...16
353 X"000B", -- SD_ADDR_cc_R11_LO -- clock conditioner R11 bits 15...0
354 X"020A", -- SD_ADDR_cc_R13_HI -- clock conditioner R13 bits 31...16
355 X"000D", -- SD_ADDR_cc_R13_LO -- clock conditioner R13 bits 15...0
356 X"0830", -- SD_ADDR_cc_R14_HI -- clock conditioner R14 bits 31...16
357 X"280E", -- SD_ADDR_cc_R14_LO -- clock conditioner R14 bits 15...0
358 X"1400", -- SD_ADDR_cc_R15_HI -- clock conditioner R15 bits 31...16
359 X"FA0F", -- SD_ADDR_cc_R15_LO -- clock conditioner R15 bits 15...0
360 X"0001", -- SD_ADDR_coin_win_p -- majority coincidence window (for physics), 8ns + 4x1ns = 12ns
361 X"0001", -- SD_ADDR_coin_win_c -- majority coincidence window (for calibration), 8ns + 4x1ns = 12ns
362 X"001F" -- -- Spare
363 );
364
365 -- default values for all FTUs
366 constant sd_block_ftu_default_array : sd_block_ftu_default_array_type := (
367 X"01FF", -- enables patch 0 board x crate y
368 X"01FF", -- enables patch 1 board x crate y
369 X"01FF", -- enables patch 2 board x crate y
370 X"01FF", -- enables patch 3 board x crate y
371 X"01F4", -- DAC_A board x crate y
372 X"01F4", -- DAC_B board x crate y
373 X"01F4", -- DAC_C board x crate y
374 X"01F4", -- DAC_D board x crate y
375 X"0010", -- DAC_H board x crate y
376 X"0001" -- Prescaling board x crate y
377 );
378
379 --default values for active FTU lists
380 constant sd_block_default_ftu_active_list : sd_block_default_ftu_active_list_type := (
381 X"0001",
382 X"0000",
383 X"0000",
384 X"0000"
385 );
386
387 -- Light pulser interface
388 constant low_PLC : integer := 16; -- minimal pulse duration in units of 4 ns
389 constant width_PLC : integer := 6; -- counter width pulse duration
390
391 -- Timing counter
392 -- constant tc_width : integer := 48; -- width (number of bits) of timing counter
393 -- constant zero : unsigned (tc_width - 1 downto 0) := (others => '0');
394
395 --======================================================================================
396 -- Constants for calibration and pedestal triggers generation
397 --======================================================================================
398 constant LOW_SPEED_CLOCK_FREQ : real := 50000000.0;
399 constant LOW_SPEED_CLOCK_PERIOD : real := 1.0/LOW_SPEED_CLOCK_FREQ;
400 constant MS_PERIOD : real := 0.001;
401 constant MAX_MS_COUNTER_WIDTH : integer := integer(ceil(log2(real(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD))));
402 constant MAX_MS_COUNTER_VAL : integer := integer(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD);
403 --======================================================================================
404
405 --======================================================================================
406 -- Constants for trigger and TIM signals width (8ns+value*4ns)
407 --======================================================================================
408 constant TRIG_SIGNAL_PULSE_WIDTH : integer range 0 to 15 := 10;
409 constant TIM_SIGNAL_PULSE_WIDTH : integer range 0 to 15 := 0;
410 --======================================================================================
411
412end ftm_constants;
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