source: firmware/FTU/FTU_control.vhd@ 9906

Last change on this file since 9906 was 9890, checked in by weitzel, 15 years ago
overflow register implemented for FTU rate counter
File size: 15.1 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 08/06/2010
6-- Design Name:
7-- Module Name: FTU_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Control FSM of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26library ftu_definitions;
27USE ftu_definitions.ftu_array_types.all;
28USE ftu_definitions.ftu_constants.all;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32--library UNISIM;
33--use UNISIM.VComponents.all;
34
35entity FTU_control is
36 port(
37 clk_50MHz : IN std_logic;
38 clk_ready : IN std_logic;
39 config_started : IN std_logic;
40 config_ready : IN std_logic;
41 ram_doa : IN STD_LOGIC_VECTOR(7 downto 0);
42 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0);
43 rate_array : IN rate_array_type;
44 overflow_array : in STD_LOGIC_VECTOR(7 downto 0);
45 new_rates : IN std_logic;
46 reset : OUT std_logic;
47 config_start : OUT std_logic;
48 ram_ena : OUT std_logic;
49 ram_enb : OUT std_logic;
50 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0);
51 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0);
52 ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0);
53 ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0);
54 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0);
55 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0);
56 dac_array : OUT dac_array_type;
57 enable_array : OUT enable_array_type;
58 cntr_reset : OUT STD_LOGIC;
59 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0)
60 );
61end FTU_control;
62
63architecture Behavioral of FTU_control is
64
65 signal reset_sig : STD_LOGIC := '0'; --initialize reset to 0 at power up
66
67 --DAC/SPI interface, default DACs come from RAM during INIT
68 signal config_start_sig : STD_LOGIC := '0';
69 signal dac_array_sig : dac_array_type := (0,0,0,0,0,0,0,0);
70
71 --enable signals for pixels in trigger, default values come from RAM during INIT
72 signal enable_array_sig : enable_array_type := ("0000000000000000", --patch A
73 "0000000000000000", --patch B
74 "0000000000000000", --patch C
75 "0000000000000000");--patch D
76
77 signal rate_array_sig : rate_array_type; -- initialized in FTU_top
78 signal cntr_reset_sig : STD_LOGIC := '0';
79 signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0) := "00011101"; -- 29
80
81 signal ram_ena_sig : STD_LOGIC := '0'; -- RAM enable for port A
82 signal ram_enb_sig : STD_LOGIC := '0'; -- RAM enable for port B
83 signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port A
84 signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port B
85 signal ram_ada_sig : STD_LOGIC_VECTOR(4 downto 0) := (others => '0'); --RAM port A address
86 signal ram_adb_sig : STD_LOGIC_VECTOR(3 downto 0) := (others => '0'); --RAM port B address
87 signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); --RAM data in A
88 signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); --RAM data in B
89
90 --counter to loop through RAM
91 signal ram_ada_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
92 signal ram_adb_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_B := 0;
93 signal ram_dac_cntr : INTEGER range 0 to (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2) := 0;
94 signal ram_enable_cntr : INTEGER range 0 to (NO_OF_ENABLE + 1) := 0;
95 signal ram_counter_cntr : INTEGER range 0 to (NO_OF_COUNTER + 2) := 0; --includes overflow register
96
97 signal wait_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
98
99 signal new_rates_sig : STD_LOGIC := '0';
100 signal new_rates_busy : STD_LOGIC := '0';
101
102 signal new_DACs_in_RAM : STD_LOGIC := '0';
103 signal new_enables_in_RAM : STD_LOGIC := '0';
104 signal new_prescaling_in_RAM : STD_LOGIC := '0';
105
106 type FTU_control_StateType is (IDLE, INIT, RUNNING, CONFIG_ENABLE, CONFIG_DAC, CONFIG_COUNTER, WRITE_RATES, RESET_ALL);
107 signal FTU_control_State : FTU_control_StateType;
108
109begin
110
111 --FTU control finite state machine
112
113 FTU_control_FSM: process (clk_50MHz)
114
115 begin
116
117 if Rising_edge(clk_50MHz) then
118
119 case FTU_control_State is
120
121 when IDLE => -- wait for DCMs to lock
122 reset_sig <= '0';
123 config_start_sig <= '0';
124 ram_ena_sig <= '0';
125 ram_wea_sig <= "0";
126 if (clk_ready = '1') then
127 FTU_control_State <= INIT;
128 end if;
129
130 when INIT => -- load default config data to RAM, see also ftu_definitions.vhd for more info
131 reset_sig <= '0';
132 new_rates_busy <= '1';
133 config_start_sig <= '0';
134 ram_ena_sig <= '1';
135 ram_wea_sig <= "1";
136 ram_ada_cntr <= ram_ada_cntr + 1;
137 ram_ada_sig <= conv_std_logic_vector(ram_ada_cntr, RAM_ADDR_WIDTH_A);
138 if (ram_ada_cntr < NO_OF_ENABLE*RAM_ADDR_RATIO) then -- default enables
139 if (ram_ada_cntr mod 2 = 0) then
140 ram_dia_sig <= DEFAULT_ENABLE(ram_ada_cntr / 2)(7 downto 0);
141 else
142 ram_dia_sig <= DEFAULT_ENABLE(ram_ada_cntr / 2)(15 downto 8);
143 end if;
144 FTU_control_State <= INIT;
145 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) then -- default counter values
146 ram_dia_sig <= (others => '0');
147 FTU_control_State <= INIT;
148 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default DACs
149 if (ram_ada_cntr < NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)*RAM_ADDR_RATIO) then
150 if (ram_ada_cntr mod 2 = 0) then
151 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2),16)(7 downto 0);
152 else
153 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2),16)(15 downto 8);
154 end if;
155 else
156 if (ram_ada_cntr mod 2 = 0) then
157 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2) + NO_OF_DAC_NOT_USED),16)(7 downto 0);
158 else
159 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2) + NO_OF_DAC_NOT_USED),16)(15 downto 8);
160 end if;
161 end if;
162 FTU_control_State <= INIT;
163 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default prescaling
164 ram_dia_sig <= conv_std_logic_vector(DEFAULT_PRESCALING,8);
165 FTU_control_State <= INIT;
166 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1) then -- default overflow register
167 ram_dia_sig <= (others => '0');
168 FTU_control_State <= INIT;
169 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 2) then -- default checksum
170 ram_dia_sig <= (others => '0');
171 FTU_control_State <= INIT;
172 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 3) then -- empty RAM cell
173 ram_dia_sig <= (others => '0');
174 FTU_control_State <= INIT;
175 else
176 ram_dia_sig <= (others => '0');
177 ram_ada_cntr <= 0;
178 ram_ada_sig <= (others => '0');
179 ram_ena_sig <= '0';
180 ram_wea_sig <= "0";
181 new_DACs_in_RAM <= '1';
182 new_enables_in_RAM <= '1';
183 new_prescaling_in_RAM <= '1';
184 cntr_reset_sig <= '1';
185 new_rates_busy <= '0';
186 FTU_control_State <= RUNNING;
187 end if;
188
189 when RUNNING => -- count triggers and react to commands from FTM
190 cntr_reset_sig <= '0';
191 reset_sig <= '0';
192 config_start_sig <= '0';
193 if (new_rates_sig = '1') then
194 FTU_control_State <= WRITE_RATES;
195 else
196 if (new_DACs_in_RAM = '1') then
197 ram_enb_sig <= '1';
198 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER), RAM_ADDR_WIDTH_B);
199 FTU_control_State <= CONFIG_DAC;
200 elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '1') then
201 ram_enb_sig <= '1';
202 ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B);
203 FTU_control_State <= CONFIG_ENABLE;
204 elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '0' and new_prescaling_in_RAM = '1') then
205 ram_ena_sig <= '1';
206 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
207 FTU_control_State <= CONFIG_COUNTER;
208 else
209 FTU_control_State <= RUNNING;
210 end if;
211 end if;
212
213 when CONFIG_COUNTER =>
214 wait_cntr <= wait_cntr + 1;
215 new_rates_busy <= '1';
216 if (wait_cntr = 0) then
217 FTU_control_State <= CONFIG_COUNTER;
218 elsif (wait_cntr = 1) then
219 prescaling_sig <= ram_doa;
220 FTU_control_State <= CONFIG_COUNTER;
221 else
222 cntr_reset_sig <= '1';
223 ram_ada_sig <= (others => '0');
224 wait_cntr <= 0;
225 new_prescaling_in_RAM <= '0';
226 ram_ena_sig <= '0';
227 new_rates_busy <= '0';
228 FTU_control_State <= RUNNING;
229 end if;
230
231 when CONFIG_ENABLE =>
232 ram_enable_cntr <= ram_enable_cntr + 1;
233 new_rates_busy <= '1';
234 if (ram_enable_cntr = 0) then
235 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
236 FTU_control_State <= CONFIG_ENABLE;
237 elsif (ram_enable_cntr > 0 and ram_enable_cntr < NO_OF_ENABLE + 1) then
238 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
239 enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
240 FTU_control_State <= CONFIG_ENABLE;
241 else
242 ram_adb_sig <= (others => '0');
243 ram_enable_cntr <= 0;
244 new_enables_in_RAM <= '0';
245 ram_enb_sig <= '0';
246 cntr_reset_sig <= '1';
247 new_rates_busy <= '0';
248 FTU_control_State <= RUNNING;
249 end if;
250
251 when CONFIG_DAC =>
252 new_rates_busy <= '1';
253 if (ram_dac_cntr <= (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2)) then
254 ram_dac_cntr <= ram_dac_cntr + 1;
255 if (ram_dac_cntr = 0) then
256 FTU_control_State <= CONFIG_DAC;
257 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
258 elsif (ram_dac_cntr > 0 and ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then
259 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob));
260 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
261 FTU_control_State <= CONFIG_DAC;
262 elsif (ram_dac_cntr > 0 and ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED + 1)) then
263 dac_array_sig(ram_dac_cntr - 1 + NO_OF_DAC_NOT_USED) <= conv_integer(unsigned(ram_dob));
264 ram_adb_sig <= (others => '0');
265 FTU_control_State <= CONFIG_DAC;
266 else
267 ram_adb_sig <= (others => '0');
268 config_start_sig <= '1';
269 FTU_control_State <= CONFIG_DAC;
270 end if;
271 else
272 if (config_ready = '1') then
273 ram_dac_cntr <= 0;
274 new_DACs_in_RAM <= '0';
275 cntr_reset_sig <= '1';
276 new_rates_busy <= '0';
277 FTU_control_State <= RUNNING;
278 elsif (config_ready = '0' and config_started = '1') then
279 ram_enb_sig <= '0';
280 config_start_sig <= '0';
281 FTU_control_State <= CONFIG_DAC;
282 else
283 FTU_control_State <= CONFIG_DAC;
284 end if;
285 end if;
286
287 when WRITE_RATES => -- write trigger/patch rates to RAM B and overflow register to RAM A
288 new_rates_busy <= '1';
289 ram_counter_cntr <= ram_counter_cntr + 1;
290 if (ram_counter_cntr < NO_OF_COUNTER) then
291 ram_enb_sig <= '1';
292 ram_web_sig <= "1";
293 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr), RAM_ADDR_WIDTH_B);
294 ram_dib_sig <= conv_std_logic_vector(rate_array_sig(ram_counter_cntr), 16);
295 FTU_control_State <= WRITE_RATES;
296 elsif (ram_counter_cntr = NO_Of_COUNTER) then
297 ram_dib_sig <= (others => '0');
298 ram_adb_sig <= (others => '0');
299 ram_enb_sig <= '0';
300 ram_web_sig <= "0";
301 ram_ena_sig <= '1';
302 ram_wea_sig <= "1";
303 ram_ada_sig <= conv_std_logic_vector(NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1, RAM_ADDR_WIDTH_A);
304 ram_dia_sig <= overflow_array;
305 FTU_control_State <= WRITE_RATES;
306 else
307 ram_ena_sig <= '0';
308 ram_wea_sig <= "0";
309 ram_counter_cntr <= 0;
310 new_rates_busy <= '0';
311 FTU_control_State <= RUNNING;
312 end if;
313
314 when RESET_ALL => -- reset/clear and start from scratch
315 reset_sig <= '1';
316 config_start_sig <= '0';
317 FTU_control_State <= IDLE;
318 end case;
319 end if;
320 end process FTU_control_FSM;
321
322 detect_new_rates: process(new_rates, new_rates_busy)
323 begin
324 if (new_rates_busy = '0' and rising_edge(new_rates)) then
325 new_rates_sig <= '1';
326 else
327 new_rates_sig <= '0';
328 end if;
329 end process detect_new_rates;
330
331 reset <= reset_sig;
332
333 config_start <= config_start_sig;
334 dac_array <= dac_array_sig;
335
336 enable_array <= enable_array_sig;
337
338 rate_array_sig <= rate_array;
339
340 cntr_reset <= cntr_reset_sig;
341 prescaling <= prescaling_sig;
342
343 ram_ena <= ram_ena_sig;
344 ram_enb <= ram_enb_sig;
345 ram_wea <= ram_wea_sig;
346 ram_web <= ram_web_sig;
347 ram_ada <= ram_ada_sig;
348 ram_adb <= ram_adb_sig;
349 ram_dia <= ram_dia_sig;
350 ram_dib <= ram_dib_sig;
351
352end Behavioral;
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