source: firmware/FTU/FTU_top.vhd@ 9968

Last change on this file since 9968 was 9939, checked in by weitzel, 15 years ago
FTU RS485 interface is now connected to main control
File size: 18.6 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 11:59:40 01/19/2010
6-- Design Name:
7-- Module Name: FTU_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Revision 0.02 - New design of FTU firmware, 12.07.2010, Q. Weitzel
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27library ftu_definitions;
28USE ftu_definitions.ftu_array_types.all;
29USE ftu_definitions.ftu_constants.all;
30
31---- Uncomment the following library declaration if instantiating
32---- any Xilinx primitives in this code.
33library UNISIM;
34use UNISIM.VComponents.all;
35
36entity FTU_top is
37 port(
38 -- global control
39 ext_clk : IN STD_LOGIC; -- external clock from FTU board
40 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
41 brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID
42
43 -- rate counters LVDS inputs
44 -- use IBUFDS differential input buffer
45 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
46 patch_A_n : IN STD_LOGIC;
47 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
48 patch_B_n : IN STD_LOGIC;
49 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
50 patch_C_n : IN STD_LOGIC;
51 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
52 patch_D_n : IN STD_LOGIC;
53 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
54 trig_prim_n : IN STD_LOGIC;
55
56 -- DAC interface
57 sck : OUT STD_LOGIC; -- serial clock to DAC
58 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
59 clr : OUT STD_LOGIC; -- clear signal to DAC
60 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
61
62 -- RS-485 interface to FTM
63 rx : IN STD_LOGIC; -- serial data from FTM
64 tx : OUT STD_LOGIC; -- serial data to FTM
65 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
66 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
67
68 -- analog buffer enable
69 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
70 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
71 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
72 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
73
74 -- testpoints
75 TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints
76 );
77end FTU_top;
78
79architecture Behavioral of FTU_top is
80
81 signal reset_sig : STD_LOGIC; -- initialized in FTU_control
82
83 --single-ended trigger signals for rate counter
84 signal patch_A_sig : STD_LOGIC := '0';
85 signal patch_B_sig : STD_LOGIC := '0';
86 signal patch_C_sig : STD_LOGIC := '0';
87 signal patch_D_sig : STD_LOGIC := '0';
88 signal trigger_sig : STD_LOGIC := '0';
89
90 --DAC/SPI interface
91 signal config_start_sig : STD_LOGIC; -- initialized in FTU_control
92 signal config_started_sig : STD_LOGIC; -- initialized in spi_interface
93 signal config_ready_sig : STD_LOGIC; -- initialized in spi_interface
94 signal dac_array_sig : dac_array_type; -- initialized in FTU_control
95
96 signal enable_array_sig : enable_array_type; -- initialized in FTU_control
97
98 --rate counter signals
99 signal cntr_reset_sig : STD_LOGIC; -- initialized in FTU_control
100 signal rate_array_sig : rate_array_type; -- initialized by counters
101 signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0); -- initialized in FTU_control
102 signal overflow_array : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
103 signal new_rate_A_sig : STD_LOGIC; -- initialized by patch A counter
104 signal new_rate_B_sig : STD_LOGIC; -- initialized by patch B counter
105 signal new_rate_C_sig : STD_LOGIC; -- initialized by patch C counter
106 signal new_rate_D_sig : STD_LOGIC; -- initialized by patch D counter
107 signal new_rate_t_sig : STD_LOGIC; -- initialized by trigger counter
108 signal new_rates_sig : STD_LOGIC := '0';
109
110 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM
111 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTU_clk_gen when DCMs have locked
112
113 --signals for RAM control, all initialized in FTU_control
114 signal ram_ena_sig : STD_LOGIC;
115 signal ram_enb_sig : STD_LOGIC;
116 signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0);
117 signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0);
118 signal ram_ada_sig : STD_LOGIC_VECTOR(4 downto 0);
119 signal ram_adb_sig : STD_LOGIC_VECTOR(3 downto 0);
120 signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0);
121 signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0);
122 signal ram_doa_sig : STD_LOGIC_VECTOR(7 downto 0);
123 signal ram_dob_sig : STD_LOGIC_VECTOR(15 downto 0);
124
125 --signals from RS485 module, all initialized in FTU_rs485_control (or deeper)
126 signal new_DACs_sig : std_logic;
127 signal new_enables_sig : std_logic;
128 signal new_prescaling_sig : std_logic;
129 signal read_rates_sig : std_logic;
130 signal read_DACs_sig : std_logic;
131 signal read_enables_sig : std_logic;
132 signal read_prescaling_sig : std_logic;
133 signal dac_array_rs485_out_sig : dac_array_type;
134 signal enable_array_rs485_out_sig : enable_array_type;
135 signal prescaling_rs485_out_sig : STD_LOGIC_VECTOR(7 downto 0);
136
137 --signals to RS485 module, all initialized in FTU_control
138 signal rates_ready_sig : std_logic;
139 signal DACs_ready_sig : std_logic;
140 signal enables_ready_sig : std_logic;
141 signal prescaling_ready_sig : std_logic;
142 signal rate_array_rs485_sig : rate_array_type;
143 signal overflow_array_rs485_in_sig : STD_LOGIC_VECTOR(7 downto 0);
144
145 component FTU_clk_gen
146 port(
147 clk : IN STD_LOGIC;
148 rst : IN STD_LOGIC;
149 clk_50 : OUT STD_LOGIC;
150 ready : OUT STD_LOGIC
151 );
152 end component;
153
154 component FTU_rate_counter is
155 port(
156 clk : in std_logic;
157 cntr_reset : in std_logic;
158 trigger : in std_logic;
159 prescaling : in std_logic_vector(7 downto 0);
160 counts : out integer range 0 to 2**16 - 1;
161 overflow : out std_logic;
162 new_rate : out std_logic
163 );
164 end component;
165
166 component FTU_control -- comments: see entity file
167 port(
168 clk_50MHz : IN std_logic;
169 clk_ready : IN std_logic;
170 config_started : IN std_logic;
171 config_ready : IN std_logic;
172 ram_doa : IN STD_LOGIC_VECTOR(7 downto 0);
173 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0);
174 rate_array : IN rate_array_type;
175 overflow_array : in STD_LOGIC_VECTOR(7 downto 0);
176 new_rates : IN std_logic;
177 new_DACs : IN std_logic;
178 new_enables : IN std_logic;
179 new_prescaling : IN std_logic;
180 read_rates : IN std_logic;
181 read_DACs : IN std_logic;
182 read_enables : IN std_logic;
183 read_prescaling : IN std_logic;
184 dac_array_rs485_out : IN dac_array_type;
185 enable_array_rs485_out : IN enable_array_type;
186 prescaling_rs485_out : IN STD_LOGIC_VECTOR(7 downto 0);
187 reset : OUT std_logic;
188 config_start : OUT std_logic;
189 ram_ena : OUT std_logic;
190 ram_enb : OUT std_logic;
191 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0);
192 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0);
193 ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0);
194 ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0);
195 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0);
196 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0);
197 rate_array_rs485 : OUT rate_array_type;
198 overflow_array_rs485_in : OUT STD_LOGIC_VECTOR(7 downto 0);
199 rates_ready : OUT std_logic;
200 DACs_ready : OUT std_logic;
201 enables_ready : OUT std_logic;
202 prescaling_ready : OUT std_logic;
203 dac_array : OUT dac_array_type;
204 enable_array : OUT enable_array_type;
205 cntr_reset : OUT STD_LOGIC;
206 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0)
207 );
208 end component;
209
210 component FTU_spi_interface
211 port(
212 clk_50MHz : IN std_logic;
213 config_start : IN std_logic;
214 dac_array : IN dac_array_type;
215 config_ready : OUT std_logic;
216 config_started : OUT std_logic;
217 dac_cs : OUT std_logic;
218 mosi : OUT std_logic;
219 sclk : OUT std_logic
220 );
221 end component;
222
223 component FTU_rs485_control -- comments: see entity file
224 port(
225 main_clk : IN std_logic;
226 brd_add : IN std_logic_vector(5 downto 0);
227 rx_d : IN std_logic;
228 rates_ready : IN std_logic;
229 DACs_ready : IN std_logic;
230 enables_ready : IN std_logic;
231 prescaling_ready : IN std_logic;
232 rate_array_rs485 : IN rate_array_type;
233 overflow_array_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
234 dac_array_rs485_in : IN dac_array_type;
235 enable_array_rs485_in : IN enable_array_type;
236 prescaling_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
237 rx_en : OUT std_logic;
238 tx_d : OUT std_logic;
239 tx_en : OUT std_logic;
240 new_DACs : OUT std_logic;
241 new_enables : OUT std_logic;
242 new_prescaling : OUT std_logic;
243 read_rates : OUT std_logic;
244 read_DACs : OUT std_logic;
245 read_enables : OUT std_logic;
246 read_prescaling : OUT std_logic;
247 dac_array_rs485_out : OUT dac_array_type;
248 enable_array_rs485_out : OUT enable_array_type;
249 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
250 );
251 end component;
252
253 component FTU_dual_port_ram
254 port(
255 clka : IN std_logic;
256 ena : IN std_logic;
257 wea : IN std_logic_VECTOR(0 downto 0);
258 addra : IN std_logic_VECTOR(4 downto 0);
259 dina : IN std_logic_VECTOR(7 downto 0);
260 douta : OUT std_logic_VECTOR(7 downto 0);
261 clkb : IN std_logic;
262 enb : IN std_logic;
263 web : IN std_logic_VECTOR(0 downto 0);
264 addrb : IN std_logic_VECTOR(3 downto 0);
265 dinb : IN std_logic_VECTOR(15 downto 0);
266 doutb : OUT std_logic_VECTOR(15 downto 0)
267 );
268 end component;
269
270 -- Synplicity black box declaration
271 attribute syn_black_box : boolean;
272 attribute syn_black_box of FTU_dual_port_ram: component is true;
273 -- avoid "black box" warning during synthesis
274 attribute box_type : string;
275 attribute box_type of FTU_dual_port_ram: component is "black_box";
276
277begin
278
279 clr <= '1';
280 TP_A <= "000000000000";
281
282 enables_A <= enable_array_sig(0)(8 downto 0);
283 enables_B <= enable_array_sig(1)(8 downto 0);
284 enables_C <= enable_array_sig(2)(8 downto 0);
285 enables_D <= enable_array_sig(3)(8 downto 0);
286
287 new_rates_sig <= new_rate_A_sig and new_rate_B_sig and new_rate_C_sig and new_rate_D_sig and new_rate_t_sig;
288
289 --these bits are not used, others come from rate counters
290 overflow_array(5) <= '0';
291 overflow_array(6) <= '0';
292 overflow_array(7) <= '0';
293
294 --differential input buffer for patch A
295 IBUFDS_LVDS_33_A : IBUFDS_LVDS_33
296 port map(
297 O => patch_A_sig,
298 I => patch_A_p,
299 IB => patch_A_n
300 );
301
302 --differential input buffer for patch B
303 IBUFDS_LVDS_33_B : IBUFDS_LVDS_33
304 port map(
305 O => patch_B_sig,
306 I => patch_B_p,
307 IB => patch_B_n
308 );
309
310 --differential input buffer for patch C
311 IBUFDS_LVDS_33_C : IBUFDS_LVDS_33
312 port map(
313 O => patch_C_sig,
314 I => patch_C_p,
315 IB => patch_C_n
316 );
317
318 --differential input buffer for patch D
319 IBUFDS_LVDS_33_D : IBUFDS_LVDS_33
320 port map(
321 O => patch_D_sig,
322 I => patch_D_p,
323 IB => patch_D_n
324 );
325
326 --differential input buffer for trigger
327 IBUFDS_LVDS_33_t : IBUFDS_LVDS_33
328 port map(
329 O => trigger_sig,
330 I => trig_prim_p,
331 IB => trig_prim_n
332 );
333
334 Inst_FTU_clk_gen : FTU_clk_gen
335 port map(
336 clk => ext_clk,
337 rst => reset_sig,
338 clk_50 => clk_50M_sig,
339 ready => clk_ready_sig
340 );
341
342 Inst_FTU_rate_counter_A : FTU_rate_counter
343 port map(
344 clk => clk_50M_sig,
345 cntr_reset => cntr_reset_sig,
346 trigger => patch_A_sig,
347 prescaling => prescaling_sig,
348 counts => rate_array_sig(0),
349 overflow => overflow_array(0),
350 new_rate => new_rate_A_sig
351 );
352
353 Inst_FTU_rate_counter_B : FTU_rate_counter
354 port map(
355 clk => clk_50M_sig,
356 cntr_reset => cntr_reset_sig,
357 trigger => patch_B_sig,
358 prescaling => prescaling_sig,
359 counts => rate_array_sig(1),
360 overflow => overflow_array(1),
361 new_rate => new_rate_B_sig
362 );
363
364 Inst_FTU_rate_counter_C : FTU_rate_counter
365 port map(
366 clk => clk_50M_sig,
367 cntr_reset => cntr_reset_sig,
368 trigger => patch_C_sig,
369 prescaling => prescaling_sig,
370 counts => rate_array_sig(2),
371 overflow => overflow_array(2),
372 new_rate => new_rate_C_sig
373 );
374
375 Inst_FTU_rate_counter_D : FTU_rate_counter
376 port map(
377 clk => clk_50M_sig,
378 cntr_reset => cntr_reset_sig,
379 trigger => patch_D_sig,
380 prescaling => prescaling_sig,
381 counts => rate_array_sig(3),
382 overflow => overflow_array(3),
383 new_rate => new_rate_D_sig
384 );
385
386 Inst_FTU_rate_counter_t : FTU_rate_counter
387 port map(
388 clk => clk_50M_sig,
389 cntr_reset => cntr_reset_sig,
390 trigger => trigger_sig,
391 prescaling => prescaling_sig,
392 counts => rate_array_sig(4),
393 overflow => overflow_array(4),
394 new_rate => new_rate_t_sig
395 );
396
397 Inst_FTU_control : FTU_control
398 port map(
399 clk_50MHz => clk_50M_sig,
400 clk_ready => clk_ready_sig,
401 config_started => config_started_sig,
402 config_ready => config_ready_sig,
403 ram_doa => ram_doa_sig,
404 ram_dob => ram_dob_sig,
405 rate_array => rate_array_sig,
406 overflow_array => overflow_array,
407 new_rates => new_rates_sig,
408 new_DACs => new_DACs_sig,
409 new_enables => new_enables_sig,
410 new_prescaling => new_prescaling_sig,
411 read_rates => read_rates_sig,
412 read_DACs => read_DACs_sig,
413 read_enables => read_enables_sig,
414 read_prescaling => read_prescaling_sig,
415 dac_array_rs485_out => dac_array_rs485_out_sig,
416 enable_array_rs485_out => enable_array_rs485_out_sig,
417 prescaling_rs485_out => prescaling_rs485_out_sig,
418 reset => reset_sig,
419 config_start => config_start_sig,
420 ram_ena => ram_ena_sig,
421 ram_enb => ram_enb_sig,
422 ram_wea => ram_wea_sig,
423 ram_web => ram_web_sig,
424 ram_ada => ram_ada_sig,
425 ram_adb => ram_adb_sig,
426 ram_dia => ram_dia_sig,
427 ram_dib => ram_dib_sig,
428 rate_array_rs485 => rate_array_rs485_sig,
429 overflow_array_rs485_in => overflow_array_rs485_in_sig,
430 rates_ready => rates_ready_sig,
431 DACs_ready => DACs_ready_sig,
432 enables_ready => enables_ready_sig,
433 prescaling_ready => prescaling_ready_sig,
434 dac_array => dac_array_sig,
435 enable_array => enable_array_sig,
436 cntr_reset => cntr_reset_sig,
437 prescaling => prescaling_sig
438 );
439
440 Inst_FTU_spi_interface : FTU_spi_interface
441 port map(
442 clk_50MHz => clk_50M_sig,
443 config_start => config_start_sig,
444 dac_array => dac_array_sig,
445 config_ready => config_ready_sig,
446 config_started => config_started_sig,
447 dac_cs => cs_ld,
448 mosi => mosi,
449 sclk => sck
450 );
451
452 Inst_FTU_rs485_control : FTU_rs485_control
453 port map(
454 main_clk => clk_50M_sig,
455 brd_add => brd_add,
456 rx_d => rx,
457 rates_ready => rates_ready_sig,
458 DACs_ready => DACs_ready_sig,
459 enables_ready => enables_ready_sig,
460 prescaling_ready => prescaling_ready_sig,
461 rate_array_rs485 => rate_array_rs485_sig,
462 overflow_array_rs485_in => overflow_array_rs485_in_sig,
463 dac_array_rs485_in => dac_array_sig,
464 enable_array_rs485_in => enable_array_sig,
465 prescaling_rs485_in => prescaling_sig,
466 rx_en => rx_en,
467 tx_d => tx,
468 tx_en => tx_en,
469 new_DACs => new_DACs_sig,
470 new_enables => new_enables_sig,
471 new_prescaling => new_prescaling_sig,
472 read_rates => read_rates_sig,
473 read_DACs => read_DACs_sig,
474 read_enables => read_enables_sig,
475 read_prescaling => read_prescaling_sig,
476 dac_array_rs485_out => dac_array_rs485_out_sig,
477 enable_array_rs485_out => enable_array_rs485_out_sig,
478 prescaling_rs485_out => prescaling_rs485_out_sig
479 );
480
481 Inst_FTU_dual_port_ram : FTU_dual_port_ram
482 port map(
483 clka => clk_50M_sig,
484 ena => ram_ena_sig,
485 wea => ram_wea_sig,
486 addra => ram_ada_sig,
487 dina => ram_dia_sig,
488 douta => ram_doa_sig,
489 clkb => clk_50M_sig,
490 enb => ram_enb_sig,
491 web => ram_web_sig,
492 addrb => ram_adb_sig,
493 dinb => ram_dib_sig,
494 doutb => ram_dob_sig
495 );
496
497end Behavioral;
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