source: firmware/FTU/rs485/FTU_rs485_control.vhd@ 10047

Last change on this file since 10047 was 10037, checked in by weitzel, 14 years ago
FTU counter changed from 16 to 30 bit
File size: 51.7 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 09/13/2010
6-- Design Name:
7-- Module Name: FTU_rs485_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: top level entity of FTU RS485 module
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26library ftu_definitions;
27USE ftu_definitions.ftu_array_types.all;
28USE ftu_definitions.ftu_constants.all;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32--library UNISIM;
33--use UNISIM.VComponents.all;
34
35entity FTU_rs485_control is
36 port(
37 main_clk : IN std_logic;
38 brd_add : IN std_logic_vector(5 downto 0);
39 rx_d : IN std_logic;
40 rates_ready : IN std_logic; -- rate_array_rs485 has now valid rates for sending
41 DACs_ready : IN std_logic; -- dac_array_rs485_in is ok for sending
42 enables_ready : IN std_logic; -- enable_array_rs485_in is ok for sending
43 prescaling_ready : IN std_logic; -- prescaling byte is ok for sending
44 ping_pong_ready : IN std_logic; -- ping pong successful
45 rate_array_rs485 : IN rate_array_type;
46 overflow_array_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
47 dac_array_rs485_in : IN dac_array_type;
48 enable_array_rs485_in : IN enable_array_type;
49 prescaling_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
50 dna : IN STD_LOGIC_VECTOR(63 downto 0);
51 rx_en : OUT std_logic;
52 tx_d : OUT std_logic;
53 tx_en : OUT std_logic;
54 new_DACs : OUT std_logic := '0'; -- new DACs arrived via RS485
55 new_enables : OUT std_logic := '0'; -- new enables arrived via RS485
56 new_prescaling : OUT std_logic := '0'; -- new prescaling arrived via RS485
57 read_rates : OUT std_logic := '0'; -- FTM wants to read rates
58 read_DACs : OUT std_logic := '0'; -- FTM wants to read DACs
59 read_enables : OUT std_logic := '0'; -- FTM wants to read enable pattern
60 read_prescaling : OUT std_logic := '0'; -- FTM wants to read prescaling value
61 ping_pong : OUT std_logic := '0'; -- ping pong command from FTM
62 dac_array_rs485_out : OUT dac_array_type;
63 enable_array_rs485_out : OUT enable_array_type;
64 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
65 );
66end FTU_rs485_control;
67
68architecture Behavioral of FTU_rs485_control is
69
70 signal tx_start_sig : std_logic := '0';
71 signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
72 signal tx_busy_sig : std_logic; -- initialized in FTU_rs485_interface
73
74 signal rx_valid_sig : std_logic; -- initialized in FTU_rs485_interface
75 signal rx_data_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTU_rs485_interface
76 --signal rx_busy_sig : std_logic; -- initialized in FTU_rs485_interface
77
78 signal block_valid_sig : std_logic; -- initialized in FTU_rs485_receiver
79 signal data_block_sig : std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0); -- initialized in FTU_rs485_receiver
80
81 signal int_new_DACs_sig : std_logic; -- initialized in FTU_rs485_interpreter
82 signal int_new_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter
83 signal int_new_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter
84 signal int_read_rates_sig : std_logic; -- initialized in FTU_rs485_interpreter
85 signal int_read_DACs_sig : std_logic; -- initialized in FTU_rs485_interpreter
86 signal int_read_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter
87 signal int_read_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter
88 signal int_ping_pong_sig : std_logic; -- initialized in FTU_rs485_interpreter
89
90 signal txcnt : integer range 0 to (RS485_BLOCK_WIDTH / 8) := 0; -- count 28 1-byte frames
91
92 component FTU_rs485_receiver
93 port(
94 rec_clk : in std_logic;
95 --rx_busy : in std_logic;
96 rec_din : in std_logic_vector(7 downto 0);
97 rec_den : in std_logic;
98 rec_dout : out std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0);
99 rec_valid : out std_logic
100 );
101 end component;
102
103 component FTU_rs485_interpreter
104 port(
105 clk : IN std_logic;
106 data_block : IN std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0);
107 block_valid : IN std_logic;
108 brd_add : IN std_logic_vector(5 downto 0);
109 int_new_DACs : OUT std_logic;
110 int_new_enables : OUT std_logic;
111 int_new_prescaling : OUT std_logic;
112 int_read_rates : OUT std_logic;
113 int_read_DACs : OUT std_logic;
114 int_read_enables : OUT std_logic;
115 int_read_prescaling : OUT std_logic;
116 int_ping_pong : OUT std_logic;
117 dac_array_rs485_out : OUT dac_array_type;
118 enable_array_rs485_out : OUT enable_array_type;
119 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
120 );
121 end component;
122
123 component FTU_rs485_interface
124 port(
125 clk : IN std_logic;
126 -- RS485
127 rx_d : IN std_logic;
128 rx_en : OUT std_logic;
129 tx_d : OUT std_logic;
130 tx_en : OUT std_logic;
131 -- FPGA
132 rx_data : OUT std_logic_vector (7 DOWNTO 0);
133 --rx_busy : OUT std_logic := '0';
134 rx_valid : OUT std_logic := '0';
135 tx_data : IN std_logic_vector (7 DOWNTO 0);
136 tx_busy : OUT std_logic := '0';
137 tx_start : IN std_logic
138 );
139 end component;
140
141 type FTU_rs485_control_StateType is (RECEIVE,
142 READ_RATES_WAIT, READ_DAC_WAIT, READ_ENABLE_WAIT, READ_PRESCALING_WAIT,
143 SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT, PING_PONG_WAIT,
144 READ_RATES_TRANSMIT, READ_DAC_TRANSMIT, READ_ENABLE_TRANSMIT, READ_PRESCALING_TRANSMIT,
145 SET_DAC_TRANSMIT, SET_ENABLE_TRANSMIT, SET_PRESCALING_TRANSMIT, PING_PONG_TRANSMIT);
146 signal FTU_rs485_control_State : FTU_rs485_control_StateType;
147
148begin
149
150 Inst_FTU_rs485_receiver : FTU_rs485_receiver
151 port map(
152 rec_clk => main_clk,
153 --rx_busy =>,
154 rec_din => rx_data_sig,
155 rec_den => rx_valid_sig,
156 rec_dout => data_block_sig,
157 rec_valid => block_valid_sig
158 );
159
160 Inst_FTU_rs485_interpreter : FTU_rs485_interpreter
161 port map(
162 clk => main_clk,
163 data_block => data_block_sig,
164 block_valid => block_valid_sig,
165 brd_add => brd_add,
166 int_new_DACs => int_new_DACs_sig,
167 int_new_enables => int_new_enables_sig,
168 int_new_prescaling => int_new_prescaling_sig,
169 int_read_rates => int_read_rates_sig,
170 int_read_DACs => int_read_DACs_sig,
171 int_read_enables => int_read_enables_sig,
172 int_read_prescaling => int_read_prescaling_sig,
173 int_ping_pong => int_ping_pong_sig,
174 dac_array_rs485_out => dac_array_rs485_out,
175 enable_array_rs485_out => enable_array_rs485_out,
176 prescaling_rs485_out => prescaling_rs485_out
177 );
178
179 Inst_FTU_rs485_interface : FTU_rs485_interface
180 port map(
181 clk => main_clk,
182 -- RS485
183 rx_d => rx_d,
184 rx_en => rx_en,
185 tx_d => tx_d,
186 tx_en => tx_en,
187 -- FPGA
188 rx_data => rx_data_sig,
189 --rx_busy => rx_busy_sig,
190 rx_valid => rx_valid_sig,
191 tx_data => tx_data_sig,
192 tx_busy => tx_busy_sig,
193 tx_start => tx_start_sig
194 );
195
196 --FTU RS485 control finite state machine
197
198 FTU_rs485_control_FSM: process (main_clk)
199 begin
200 if Rising_edge(main_clk) then
201 case FTU_rs485_control_State is
202
203 when RECEIVE => -- default state, receiver on, no transmission
204 tx_start_sig <= '0';
205 if (int_new_DACs_sig = '1') then
206 new_DACs <= '1';
207 new_enables <= '0';
208 new_prescaling <= '0';
209 read_rates <= '0';
210 read_DACs <= '0';
211 read_enables <= '0';
212 read_prescaling <= '0';
213 ping_pong <= '0';
214 FTU_rs485_control_State <= SET_DAC_WAIT;
215 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '1') then
216 new_DACs <= '0';
217 new_enables <= '1';
218 new_prescaling <= '0';
219 read_rates <= '0';
220 read_DACs <= '0';
221 read_enables <= '0';
222 read_prescaling <= '0';
223 ping_pong <= '0';
224 FTU_rs485_control_State <= SET_ENABLE_WAIT;
225 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '1') then
226 new_DACs <= '0';
227 new_enables <= '0';
228 new_prescaling <= '1';
229 read_rates <= '0';
230 read_DACs <= '0';
231 read_enables <= '0';
232 read_prescaling <= '0';
233 ping_pong <= '0';
234 FTU_rs485_control_State <= SET_PRESCALING_WAIT;
235 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
236 int_read_rates_sig = '1') then
237 new_DACs <= '0';
238 new_enables <= '0';
239 new_prescaling <= '0';
240 read_rates <= '1';
241 read_DACs <= '0';
242 read_enables <= '0';
243 read_prescaling <= '0';
244 ping_pong <= '0';
245 FTU_rs485_control_State <= READ_RATES_WAIT;
246 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
247 int_read_rates_sig = '0' and int_read_DACs_sig = '1') then
248 new_DACs <= '0';
249 new_enables <= '0';
250 new_prescaling <= '0';
251 read_rates <= '0';
252 read_DACs <= '1';
253 read_enables <= '0';
254 read_prescaling <= '0';
255 ping_pong <= '0';
256 FTU_rs485_control_State <= READ_DAC_WAIT;
257 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
258 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '1') then
259 new_DACs <= '0';
260 new_enables <= '0';
261 new_prescaling <= '0';
262 read_rates <= '0';
263 read_DACs <= '0';
264 read_enables <= '1';
265 read_prescaling <= '0';
266 ping_pong <= '0';
267 FTU_rs485_control_State <= READ_ENABLE_WAIT;
268 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
269 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '0' and int_read_prescaling_sig = '1') then
270 new_DACs <= '0';
271 new_enables <= '0';
272 new_prescaling <= '0';
273 read_rates <= '0';
274 read_DACs <= '0';
275 read_enables <= '0';
276 read_prescaling <= '1';
277 ping_pong <= '0';
278 FTU_rs485_control_State <= READ_PRESCALING_WAIT;
279 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
280 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '0' and int_read_prescaling_sig = '0' and
281 int_ping_pong_sig = '1') then
282 new_DACs <= '0';
283 new_enables <= '0';
284 new_prescaling <= '0';
285 read_rates <= '0';
286 read_DACs <= '0';
287 read_enables <= '0';
288 read_prescaling <= '0';
289 ping_pong <= '1';
290 FTU_rs485_control_State <= PING_PONG_WAIT;
291 else
292 new_DACs <= '0';
293 new_enables <= '0';
294 new_prescaling <= '0';
295 read_rates <= '0';
296 read_DACs <= '0';
297 read_enables <= '0';
298 read_prescaling <= '0';
299 ping_pong <= '0';
300 FTU_rs485_control_State <= RECEIVE;
301 end if;
302
303 when SET_DAC_WAIT=> -- wait until FTU control says "done" and then answer to FTM
304 if (DACs_ready = '1') then
305 new_DACs <= '0';
306 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
307 else
308 new_DACs <= '1';
309 FTU_rs485_control_State <= SET_DAC_WAIT;
310 end if;
311
312 when SET_ENABLE_WAIT => -- wait until FTU control says "done" and then answer to FTM
313 if (enables_ready = '1') then
314 new_enables <= '0';
315 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
316 else
317 new_enables <= '1';
318 FTU_rs485_control_State <= SET_ENABLE_WAIT;
319 end if;
320
321 when SET_PRESCALING_WAIT => -- wait until FTU control says "done" and then answer to FTM
322 if (prescaling_ready = '1') then
323 new_prescaling <= '0';
324 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
325 else
326 new_prescaling <= '1';
327 FTU_rs485_control_State <= SET_PRESCALING_WAIT;
328 end if;
329
330 when READ_RATES_WAIT => -- wait until FTU control says "done" and then answer to FTM
331 if (rates_ready = '1') then
332 read_rates <= '0';
333 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
334 else
335 read_rates <= '1';
336 FTU_rs485_control_State <= READ_RATES_WAIT;
337 end if;
338
339 when READ_DAC_WAIT => -- wait until FTU control says "done" and then answer to FTM
340 if (DACs_ready = '1') then
341 read_DACs <= '0';
342 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
343 else
344 read_DACs <= '1';
345 FTU_rs485_control_State <= READ_DAC_WAIT;
346 end if;
347
348 when READ_ENABLE_WAIT => -- wait until FTU control says "done" and then answer to FTM
349 if (enables_ready = '1') then
350 read_enables <= '0';
351 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
352 else
353 read_enables <= '1';
354 FTU_rs485_control_State <= READ_ENABLE_WAIT;
355 end if;
356
357 when READ_PRESCALING_WAIT => -- wait until FTU control says "done" and then answer to FTM
358 if (prescaling_ready = '1') then
359 read_prescaling <= '0';
360 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
361 else
362 read_prescaling <= '1';
363 FTU_rs485_control_State <= READ_PRESCALING_WAIT;
364 end if;
365
366 when PING_PONG_WAIT => -- wait until FTU control says "done" and then answer to FTM
367 if (ping_pong_ready = '1') then
368 ping_pong <= '0';
369 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
370 else
371 ping_pong <= '1';
372 FTU_rs485_control_State <= PING_PONG_WAIT;
373 end if;
374
375 when SET_DAC_TRANSMIT =>
376 if tx_busy_sig = '0' then
377 if txcnt = 0 then -- start delimiter
378 txcnt <= txcnt + 1;
379 tx_data_sig <= RS485_START_DELIM;
380 tx_start_sig <= '1';
381 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
382 elsif txcnt = 1 then -- FTM address
383 txcnt <= txcnt + 1;
384 tx_data_sig <= FTM_ADDRESS;
385 tx_start_sig <= '1';
386 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
387 elsif txcnt = 2 then -- board address
388 txcnt <= txcnt + 1;
389 tx_data_sig <= "00" & brd_add;
390 tx_start_sig <= '1';
391 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
392 elsif txcnt = 3 then -- firmware ID
393 txcnt <= txcnt + 1;
394 tx_data_sig <= FIRMWARE_ID;
395 tx_start_sig <= '1';
396 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
397 elsif txcnt = 4 then -- mirrored command
398 txcnt <= txcnt + 1;
399 tx_data_sig <= "00000000";
400 tx_start_sig <= '1';
401 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
402 elsif txcnt = 5 then -- data: DAC A low
403 txcnt <= txcnt + 1;
404 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0);
405 tx_start_sig <= '1';
406 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
407 elsif txcnt = 6 then -- data: DAC A high
408 txcnt <= txcnt + 1;
409 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8);
410 tx_start_sig <= '1';
411 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
412 elsif txcnt = 7 then -- data: DAC B low
413 txcnt <= txcnt + 1;
414 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0);
415 tx_start_sig <= '1';
416 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
417 elsif txcnt = 8 then -- data: DAC B high
418 txcnt <= txcnt + 1;
419 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8);
420 tx_start_sig <= '1';
421 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
422 elsif txcnt = 9 then -- data: DAC C low
423 txcnt <= txcnt + 1;
424 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0);
425 tx_start_sig <= '1';
426 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
427 elsif txcnt = 10 then -- data: DAC C high
428 txcnt <= txcnt + 1;
429 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8);
430 tx_start_sig <= '1';
431 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
432 elsif txcnt = 11 then -- data: DAC D low
433 txcnt <= txcnt + 1;
434 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0);
435 tx_start_sig <= '1';
436 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
437 elsif txcnt = 12 then -- data: DAC D high
438 txcnt <= txcnt + 1;
439 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8);
440 tx_start_sig <= '1';
441 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
442 elsif txcnt = 13 then -- data: DAC E low
443 txcnt <= txcnt + 1;
444 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0);
445 tx_start_sig <= '1';
446 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
447 elsif txcnt = 14 then -- data: DAC E high
448 txcnt <= txcnt + 1;
449 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8);
450 tx_start_sig <= '1';
451 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
452 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
453 txcnt <= txcnt + 1;
454 tx_data_sig <= "00000000";
455 tx_start_sig <= '1';
456 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
457 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
458 txcnt <= txcnt + 1;
459 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
460 tx_start_sig <= '1';
461 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
462 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
463 txcnt <= txcnt + 1;
464 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
465 tx_start_sig <= '1';
466 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
467 else -- transmission finished
468 txcnt <= 0;
469 FTU_rs485_control_State <= RECEIVE;
470 end if;
471 else
472 tx_start_sig <= '0';
473 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
474 end if;
475
476 when SET_ENABLE_TRANSMIT =>
477 if tx_busy_sig = '0' then
478 if txcnt = 0 then -- start delimiter
479 txcnt <= txcnt + 1;
480 tx_data_sig <= RS485_START_DELIM;
481 tx_start_sig <= '1';
482 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
483 elsif txcnt = 1 then -- FTM address
484 txcnt <= txcnt + 1;
485 tx_data_sig <= FTM_ADDRESS;
486 tx_start_sig <= '1';
487 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
488 elsif txcnt = 2 then -- board address
489 txcnt <= txcnt + 1;
490 tx_data_sig <= "00" & brd_add;
491 tx_start_sig <= '1';
492 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
493 elsif txcnt = 3 then -- firmware ID
494 txcnt <= txcnt + 1;
495 tx_data_sig <= FIRMWARE_ID;
496 tx_start_sig <= '1';
497 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
498 elsif txcnt = 4 then -- mirrored command
499 txcnt <= txcnt + 1;
500 tx_data_sig <= "00000011";
501 tx_start_sig <= '1';
502 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
503 elsif txcnt = 5 then -- data: enable pattern A7-0
504 txcnt <= txcnt + 1;
505 tx_data_sig <= enable_array_rs485_in(0)(7 downto 0);
506 tx_start_sig <= '1';
507 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
508 elsif txcnt = 6 then -- data: enable pattern A8
509 txcnt <= txcnt + 1;
510 tx_data_sig <= enable_array_rs485_in(0)(15 downto 8);
511 tx_start_sig <= '1';
512 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
513 elsif txcnt = 7 then -- data: enable pattern B7-0
514 txcnt <= txcnt + 1;
515 tx_data_sig <= enable_array_rs485_in(1)(7 downto 0);
516 tx_start_sig <= '1';
517 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
518 elsif txcnt = 8 then -- data: enable pattern B8
519 txcnt <= txcnt + 1;
520 tx_data_sig <= enable_array_rs485_in(1)(15 downto 8);
521 tx_start_sig <= '1';
522 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
523 elsif txcnt = 9 then -- data: enable pattern C7-0
524 txcnt <= txcnt + 1;
525 tx_data_sig <= enable_array_rs485_in(2)(7 downto 0);
526 tx_start_sig <= '1';
527 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
528 elsif txcnt = 10 then -- data: enable pattern C8
529 txcnt <= txcnt + 1;
530 tx_data_sig <= enable_array_rs485_in(2)(15 downto 8);
531 tx_start_sig <= '1';
532 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
533 elsif txcnt = 11 then -- data: enable pattern D7-0
534 txcnt <= txcnt + 1;
535 tx_data_sig <= enable_array_rs485_in(3)(7 downto 0);
536 tx_start_sig <= '1';
537 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
538 elsif txcnt = 12 then -- data: enable pattern D8
539 txcnt <= txcnt + 1;
540 tx_data_sig <= enable_array_rs485_in(3)(15 downto 8);
541 tx_start_sig <= '1';
542 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
543 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
544 txcnt <= txcnt + 1;
545 tx_data_sig <= "00000000";
546 tx_start_sig <= '1';
547 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
548 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
549 txcnt <= txcnt + 1;
550 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
551 tx_start_sig <= '1';
552 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
553 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
554 txcnt <= txcnt + 1;
555 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
556 tx_start_sig <= '1';
557 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
558 else -- transmission finished
559 txcnt <= 0;
560 FTU_rs485_control_State <= RECEIVE;
561 end if;
562 else
563 tx_start_sig <= '0';
564 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
565 end if;
566
567 when SET_PRESCALING_TRANSMIT =>
568 if tx_busy_sig = '0' then
569 if txcnt = 0 then -- start delimiter
570 txcnt <= txcnt + 1;
571 tx_data_sig <= RS485_START_DELIM;
572 tx_start_sig <= '1';
573 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
574 elsif txcnt = 1 then -- FTM address
575 txcnt <= txcnt + 1;
576 tx_data_sig <= FTM_ADDRESS;
577 tx_start_sig <= '1';
578 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
579 elsif txcnt = 2 then -- board address
580 txcnt <= txcnt + 1;
581 tx_data_sig <= "00" & brd_add;
582 tx_start_sig <= '1';
583 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
584 elsif txcnt = 3 then -- firmware ID
585 txcnt <= txcnt + 1;
586 tx_data_sig <= FIRMWARE_ID;
587 tx_start_sig <= '1';
588 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
589 elsif txcnt = 4 then -- mirrored command
590 txcnt <= txcnt + 1;
591 tx_data_sig <= "00000110";
592 tx_start_sig <= '1';
593 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
594 elsif txcnt = 5 then -- data: prescaling
595 txcnt <= txcnt + 1;
596 tx_data_sig <= prescaling_rs485_in;
597 tx_start_sig <= '1';
598 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
599 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
600 txcnt <= txcnt + 1;
601 tx_data_sig <= "00000000";
602 tx_start_sig <= '1';
603 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
604 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
605 txcnt <= txcnt + 1;
606 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
607 tx_start_sig <= '1';
608 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
609 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
610 txcnt <= txcnt + 1;
611 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
612 tx_start_sig <= '1';
613 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
614 else -- transmission finished
615 txcnt <= 0;
616 FTU_rs485_control_State <= RECEIVE;
617 end if;
618 else
619 tx_start_sig <= '0';
620 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
621 end if;
622
623 when READ_RATES_TRANSMIT =>
624 if tx_busy_sig = '0' then
625 if txcnt = 0 then -- start delimiter
626 txcnt <= txcnt + 1;
627 tx_data_sig <= RS485_START_DELIM;
628 tx_start_sig <= '1';
629 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
630 elsif txcnt = 1 then -- FTM address
631 txcnt <= txcnt + 1;
632 tx_data_sig <= FTM_ADDRESS;
633 tx_start_sig <= '1';
634 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
635 elsif txcnt = 2 then -- board address
636 txcnt <= txcnt + 1;
637 tx_data_sig <= "00" & brd_add;
638 tx_start_sig <= '1';
639 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
640 elsif txcnt = 3 then -- firmware ID
641 txcnt <= txcnt + 1;
642 tx_data_sig <= FIRMWARE_ID;
643 tx_start_sig <= '1';
644 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
645 elsif txcnt = 4 then -- mirrored command
646 txcnt <= txcnt + 1;
647 tx_data_sig <= "00000010";
648 tx_start_sig <= '1';
649 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
650 elsif txcnt = 5 then -- data: counter A 7...0
651 txcnt <= txcnt + 1;
652 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(7 downto 0);
653 tx_start_sig <= '1';
654 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
655 elsif txcnt = 6 then -- data: counter A 15...8
656 txcnt <= txcnt + 1;
657 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(15 downto 8);
658 tx_start_sig <= '1';
659 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
660 elsif txcnt = 7 then -- data: counter A 23...16
661 txcnt <= txcnt + 1;
662 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(23 downto 16);
663 tx_start_sig <= '1';
664 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
665 elsif txcnt = 8 then -- data: counter A 31...24
666 txcnt <= txcnt + 1;
667 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(31 downto 24);
668 tx_start_sig <= '1';
669 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
670 elsif txcnt = 9 then -- data: counter B 7...0
671 txcnt <= txcnt + 1;
672 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(7 downto 0);
673 tx_start_sig <= '1';
674 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
675 elsif txcnt = 10 then -- data: counter B 15...8
676 txcnt <= txcnt + 1;
677 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(15 downto 8);
678 tx_start_sig <= '1';
679 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
680 elsif txcnt = 11 then -- data: counter B 23...16
681 txcnt <= txcnt + 1;
682 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(23 downto 16);
683 tx_start_sig <= '1';
684 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
685 elsif txcnt = 12 then -- data: counter B 31...24
686 txcnt <= txcnt + 1;
687 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(31 downto 24);
688 tx_start_sig <= '1';
689 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
690 elsif txcnt = 13 then -- data: counter C 7...0
691 txcnt <= txcnt + 1;
692 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(7 downto 0);
693 tx_start_sig <= '1';
694 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
695 elsif txcnt = 14 then -- data: counter C 15...8
696 txcnt <= txcnt + 1;
697 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(15 downto 8);
698 tx_start_sig <= '1';
699 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
700 elsif txcnt = 15 then -- data: counter C 23...16
701 txcnt <= txcnt + 1;
702 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(23 downto 16);
703 tx_start_sig <= '1';
704 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
705 elsif txcnt = 16 then -- data: counter C 31...24
706 txcnt <= txcnt + 1;
707 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(31 downto 24);
708 tx_start_sig <= '1';
709 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
710 elsif txcnt = 17 then -- data: counter D 7...0
711 txcnt <= txcnt + 1;
712 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(7 downto 0);
713 tx_start_sig <= '1';
714 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
715 elsif txcnt = 18 then -- data: counter D 15...8
716 txcnt <= txcnt + 1;
717 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(15 downto 8);
718 tx_start_sig <= '1';
719 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
720 elsif txcnt = 19 then -- data: counter D 23...16
721 txcnt <= txcnt + 1;
722 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(23 downto 16);
723 tx_start_sig <= '1';
724 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
725 elsif txcnt = 20 then -- data: counter D 31...24
726 txcnt <= txcnt + 1;
727 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(31 downto 24);
728 tx_start_sig <= '1';
729 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
730 elsif txcnt = 21 then -- data: trigger counter 7...0
731 txcnt <= txcnt + 1;
732 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(7 downto 0);
733 tx_start_sig <= '1';
734 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
735 elsif txcnt = 22 then -- data: trigger counter 15...8
736 txcnt <= txcnt + 1;
737 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(15 downto 8);
738 tx_start_sig <= '1';
739 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
740 elsif txcnt = 23 then -- data: trigger counter 23...16
741 txcnt <= txcnt + 1;
742 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(23 downto 16);
743 tx_start_sig <= '1';
744 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
745 elsif txcnt = 24 then -- data: trigger counter 31...24
746 txcnt <= txcnt + 1;
747 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(31 downto 24);
748 tx_start_sig <= '1';
749 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
750 elsif txcnt = 25 then -- data: overflow register
751 txcnt <= txcnt + 1;
752 tx_data_sig <= overflow_array_rs485_in;
753 tx_start_sig <= '1';
754 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
755 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
756 txcnt <= txcnt + 1;
757 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
758 tx_start_sig <= '1';
759 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
760 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
761 txcnt <= txcnt + 1;
762 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
763 tx_start_sig <= '1';
764 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
765 else -- transmission finished
766 txcnt <= 0;
767 FTU_rs485_control_State <= RECEIVE;
768 end if;
769 else
770 tx_start_sig <= '0';
771 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
772 end if;
773
774 when READ_DAC_TRANSMIT =>
775 if tx_busy_sig = '0' then
776 if txcnt = 0 then -- start delimiter
777 txcnt <= txcnt + 1;
778 tx_data_sig <= RS485_START_DELIM;
779 tx_start_sig <= '1';
780 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
781 elsif txcnt = 1 then -- FTM address
782 txcnt <= txcnt + 1;
783 tx_data_sig <= FTM_ADDRESS;
784 tx_start_sig <= '1';
785 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
786 elsif txcnt = 2 then -- board address
787 txcnt <= txcnt + 1;
788 tx_data_sig <= "00" & brd_add;
789 tx_start_sig <= '1';
790 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
791 elsif txcnt = 3 then -- firmware ID
792 txcnt <= txcnt + 1;
793 tx_data_sig <= FIRMWARE_ID;
794 tx_start_sig <= '1';
795 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
796 elsif txcnt = 4 then -- mirrored command
797 txcnt <= txcnt + 1;
798 tx_data_sig <= "00000001";
799 tx_start_sig <= '1';
800 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
801 elsif txcnt = 5 then -- data: DAC A low
802 txcnt <= txcnt + 1;
803 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0);
804 tx_start_sig <= '1';
805 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
806 elsif txcnt = 6 then -- data: DAC A high
807 txcnt <= txcnt + 1;
808 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8);
809 tx_start_sig <= '1';
810 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
811 elsif txcnt = 7 then -- data: DAC B low
812 txcnt <= txcnt + 1;
813 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0);
814 tx_start_sig <= '1';
815 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
816 elsif txcnt = 8 then -- data: DAC B high
817 txcnt <= txcnt + 1;
818 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8);
819 tx_start_sig <= '1';
820 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
821 elsif txcnt = 9 then -- data: DAC C low
822 txcnt <= txcnt + 1;
823 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0);
824 tx_start_sig <= '1';
825 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
826 elsif txcnt = 10 then -- data: DAC C high
827 txcnt <= txcnt + 1;
828 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8);
829 tx_start_sig <= '1';
830 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
831 elsif txcnt = 11 then -- data: DAC D low
832 txcnt <= txcnt + 1;
833 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0);
834 tx_start_sig <= '1';
835 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
836 elsif txcnt = 12 then -- data: DAC D high
837 txcnt <= txcnt + 1;
838 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8);
839 tx_start_sig <= '1';
840 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
841 elsif txcnt = 13 then -- data: DAC E low
842 txcnt <= txcnt + 1;
843 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0);
844 tx_start_sig <= '1';
845 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
846 elsif txcnt = 14 then -- data: DAC E high
847 txcnt <= txcnt + 1;
848 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8);
849 tx_start_sig <= '1';
850 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
851 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
852 txcnt <= txcnt + 1;
853 tx_data_sig <= "00000000";
854 tx_start_sig <= '1';
855 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
856 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
857 txcnt <= txcnt + 1;
858 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
859 tx_start_sig <= '1';
860 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
861 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
862 txcnt <= txcnt + 1;
863 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
864 tx_start_sig <= '1';
865 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
866 else -- transmission finished
867 txcnt <= 0;
868 FTU_rs485_control_State <= RECEIVE;
869 end if;
870 else
871 tx_start_sig <= '0';
872 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
873 end if;
874
875 when READ_ENABLE_TRANSMIT =>
876 if tx_busy_sig = '0' then
877 if txcnt = 0 then -- start delimiter
878 txcnt <= txcnt + 1;
879 tx_data_sig <= RS485_START_DELIM;
880 tx_start_sig <= '1';
881 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
882 elsif txcnt = 1 then -- FTM address
883 txcnt <= txcnt + 1;
884 tx_data_sig <= FTM_ADDRESS;
885 tx_start_sig <= '1';
886 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
887 elsif txcnt = 2 then -- board address
888 txcnt <= txcnt + 1;
889 tx_data_sig <= "00" & brd_add;
890 tx_start_sig <= '1';
891 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
892 elsif txcnt = 3 then -- firmware ID
893 txcnt <= txcnt + 1;
894 tx_data_sig <= FIRMWARE_ID;
895 tx_start_sig <= '1';
896 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
897 elsif txcnt = 4 then -- mirrored command
898 txcnt <= txcnt + 1;
899 tx_data_sig <= "00000100";
900 tx_start_sig <= '1';
901 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
902 elsif txcnt = 5 then -- data: enable pattern A7-0
903 txcnt <= txcnt + 1;
904 tx_data_sig <= enable_array_rs485_in(0)(7 downto 0);
905 tx_start_sig <= '1';
906 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
907 elsif txcnt = 6 then -- data: enable pattern A8
908 txcnt <= txcnt + 1;
909 tx_data_sig <= enable_array_rs485_in(0)(15 downto 8);
910 tx_start_sig <= '1';
911 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
912 elsif txcnt = 7 then -- data: enable pattern B7-0
913 txcnt <= txcnt + 1;
914 tx_data_sig <= enable_array_rs485_in(1)(7 downto 0);
915 tx_start_sig <= '1';
916 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
917 elsif txcnt = 8 then -- data: enable pattern B8
918 txcnt <= txcnt + 1;
919 tx_data_sig <= enable_array_rs485_in(1)(15 downto 8);
920 tx_start_sig <= '1';
921 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
922 elsif txcnt = 9 then -- data: enable pattern C7-0
923 txcnt <= txcnt + 1;
924 tx_data_sig <= enable_array_rs485_in(2)(7 downto 0);
925 tx_start_sig <= '1';
926 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
927 elsif txcnt = 10 then -- data: enable pattern C8
928 txcnt <= txcnt + 1;
929 tx_data_sig <= enable_array_rs485_in(2)(15 downto 8);
930 tx_start_sig <= '1';
931 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
932 elsif txcnt = 11 then -- data: enable pattern D7-0
933 txcnt <= txcnt + 1;
934 tx_data_sig <= enable_array_rs485_in(3)(7 downto 0);
935 tx_start_sig <= '1';
936 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
937 elsif txcnt = 12 then -- data: enable pattern D8
938 txcnt <= txcnt + 1;
939 tx_data_sig <= enable_array_rs485_in(3)(15 downto 8);
940 tx_start_sig <= '1';
941 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
942 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
943 txcnt <= txcnt + 1;
944 tx_data_sig <= "00000000";
945 tx_start_sig <= '1';
946 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
947 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
948 txcnt <= txcnt + 1;
949 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
950 tx_start_sig <= '1';
951 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
952 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
953 txcnt <= txcnt + 1;
954 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
955 tx_start_sig <= '1';
956 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
957 else -- transmission finished
958 txcnt <= 0;
959 FTU_rs485_control_State <= RECEIVE;
960 end if;
961 else
962 tx_start_sig <= '0';
963 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
964 end if;
965
966 when READ_PRESCALING_TRANSMIT =>
967 if tx_busy_sig = '0' then
968 if txcnt = 0 then -- start delimiter
969 txcnt <= txcnt + 1;
970 tx_data_sig <= RS485_START_DELIM;
971 tx_start_sig <= '1';
972 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
973 elsif txcnt = 1 then -- FTM address
974 txcnt <= txcnt + 1;
975 tx_data_sig <= FTM_ADDRESS;
976 tx_start_sig <= '1';
977 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
978 elsif txcnt = 2 then -- board address
979 txcnt <= txcnt + 1;
980 tx_data_sig <= "00" & brd_add;
981 tx_start_sig <= '1';
982 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
983 elsif txcnt = 3 then -- firmware ID
984 txcnt <= txcnt + 1;
985 tx_data_sig <= FIRMWARE_ID;
986 tx_start_sig <= '1';
987 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
988 elsif txcnt = 4 then -- mirrored command
989 txcnt <= txcnt + 1;
990 tx_data_sig <= "00000111";
991 tx_start_sig <= '1';
992 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
993 elsif txcnt = 5 then -- data: prescaling
994 txcnt <= txcnt + 1;
995 tx_data_sig <= prescaling_rs485_in;
996 tx_start_sig <= '1';
997 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
998 elsif txcnt = 6 then -- data: overflow register
999 txcnt <= txcnt + 1;
1000 tx_data_sig <= overflow_array_rs485_in;
1001 tx_start_sig <= '1';
1002 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1003 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
1004 txcnt <= txcnt + 1;
1005 tx_data_sig <= "00000000";
1006 tx_start_sig <= '1';
1007 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1008 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
1009 txcnt <= txcnt + 1;
1010 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
1011 tx_start_sig <= '1';
1012 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1013 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
1014 txcnt <= txcnt + 1;
1015 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
1016 tx_start_sig <= '1';
1017 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1018 else -- transmission finished
1019 txcnt <= 0;
1020 FTU_rs485_control_State <= RECEIVE;
1021 end if;
1022 else
1023 tx_start_sig <= '0';
1024 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1025 end if;
1026
1027 when PING_PONG_TRANSMIT =>
1028 if tx_busy_sig = '0' then
1029 if txcnt = 0 then -- start delimiter
1030 txcnt <= txcnt + 1;
1031 tx_data_sig <= RS485_START_DELIM;
1032 tx_start_sig <= '1';
1033 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1034 elsif txcnt = 1 then -- FTM address
1035 txcnt <= txcnt + 1;
1036 tx_data_sig <= FTM_ADDRESS;
1037 tx_start_sig <= '1';
1038 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1039 elsif txcnt = 2 then -- board address
1040 txcnt <= txcnt + 1;
1041 tx_data_sig <= "00" & brd_add;
1042 tx_start_sig <= '1';
1043 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1044 elsif txcnt = 3 then -- firmware ID
1045 txcnt <= txcnt + 1;
1046 tx_data_sig <= FIRMWARE_ID;
1047 tx_start_sig <= '1';
1048 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1049 elsif txcnt = 4 then -- mirrored command
1050 txcnt <= txcnt + 1;
1051 tx_data_sig <= "00000101";
1052 tx_start_sig <= '1';
1053 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1054 elsif txcnt = 5 then -- data: device DNA
1055 txcnt <= txcnt + 1;
1056 tx_data_sig <= dna(7 downto 0);
1057 tx_start_sig <= '1';
1058 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1059 elsif txcnt = 6 then -- data: device DNA
1060 txcnt <= txcnt + 1;
1061 tx_data_sig <= dna(15 downto 8);
1062 tx_start_sig <= '1';
1063 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1064 elsif txcnt = 7 then -- data: device DNA
1065 txcnt <= txcnt + 1;
1066 tx_data_sig <= dna(23 downto 16);
1067 tx_start_sig <= '1';
1068 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1069 elsif txcnt = 8 then -- data: device DNA
1070 txcnt <= txcnt + 1;
1071 tx_data_sig <= dna(31 downto 24);
1072 tx_start_sig <= '1';
1073 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1074 elsif txcnt = 9 then -- data: device DNA
1075 txcnt <= txcnt + 1;
1076 tx_data_sig <= dna(39 downto 32);
1077 tx_start_sig <= '1';
1078 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1079 elsif txcnt = 10 then -- data: device DNA
1080 txcnt <= txcnt + 1;
1081 tx_data_sig <= dna(47 downto 40);
1082 tx_start_sig <= '1';
1083 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1084 elsif txcnt = 11 then -- data: device DNA
1085 txcnt <= txcnt + 1;
1086 tx_data_sig <= dna(55 downto 48);
1087 tx_start_sig <= '1';
1088 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1089 elsif txcnt = 12 then -- data: device DNA
1090 txcnt <= txcnt + 1;
1091 tx_data_sig <= dna(63 downto 56);
1092 tx_start_sig <= '1';
1093 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1094 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
1095 txcnt <= txcnt + 1;
1096 tx_data_sig <= "00000000";
1097 tx_start_sig <= '1';
1098 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1099 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
1100 txcnt <= txcnt + 1;
1101 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
1102 tx_start_sig <= '1';
1103 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1104 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
1105 txcnt <= txcnt + 1;
1106 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
1107 tx_start_sig <= '1';
1108 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1109 else -- transmission finished
1110 txcnt <= 0;
1111 FTU_rs485_control_State <= RECEIVE;
1112 end if;
1113 else
1114 tx_start_sig <= '0';
1115 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1116 end if;
1117
1118 end case;
1119 end if;
1120 end process FTU_rs485_control_FSM;
1121
1122end Behavioral;
1123
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