source: firmware/FTU/rs485/FTU_rs485_control.vhd@ 10068

Last change on this file since 10068 was 10051, checked in by weitzel, 15 years ago
some code cleaning and more comments for FTU firmware
File size: 62.8 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 09/13/2010
6-- Design Name:
7-- Module Name: FTU_rs485_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: top level entity of FTU RS485 module
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26library ftu_definitions;
27USE ftu_definitions.ftu_array_types.all;
28USE ftu_definitions.ftu_constants.all;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32--library UNISIM;
33--use UNISIM.VComponents.all;
34
35entity FTU_rs485_control is
36 port(
37 main_clk : IN std_logic;
38 brd_add : IN std_logic_vector(5 downto 0);
39 rx_d : IN std_logic;
40 rates_ready : IN std_logic; -- rate_array_rs485 has now valid rates for sending
41 DACs_ready : IN std_logic; -- dac_array_rs485_in is ok for sending
42 enables_ready : IN std_logic; -- enable_array_rs485_in is ok for sending
43 prescaling_ready : IN std_logic; -- prescaling byte is ok for sending
44 ping_pong_ready : IN std_logic; -- ping pong successful
45 rate_array_rs485 : IN rate_array_type;
46 overflow_array_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
47 dac_array_rs485_in : IN dac_array_type;
48 enable_array_rs485_in : IN enable_array_type;
49 prescaling_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
50 dna : IN STD_LOGIC_VECTOR(63 downto 0);
51 rx_en : OUT std_logic;
52 tx_d : OUT std_logic;
53 tx_en : OUT std_logic;
54 new_DACs : OUT std_logic := '0'; -- new DACs arrived via RS485
55 new_enables : OUT std_logic := '0'; -- new enables arrived via RS485
56 new_prescaling : OUT std_logic := '0'; -- new prescaling arrived via RS485
57 read_rates : OUT std_logic := '0'; -- FTM wants to read rates
58 read_DACs : OUT std_logic := '0'; -- FTM wants to read DACs
59 read_enables : OUT std_logic := '0'; -- FTM wants to read enable pattern
60 read_prescaling : OUT std_logic := '0'; -- FTM wants to read prescaling value
61 ping_pong : OUT std_logic := '0'; -- ping pong command from FTM
62 dac_array_rs485_out : OUT dac_array_type;
63 enable_array_rs485_out : OUT enable_array_type;
64 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
65 );
66end FTU_rs485_control;
67
68architecture Behavioral of FTU_rs485_control is
69
70 signal tx_start_sig : std_logic := '0';
71 signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
72 signal tx_busy_sig : std_logic; -- initialized in FTU_rs485_interface
73
74 signal rx_valid_sig : std_logic; -- initialized in FTU_rs485_interface
75 signal rx_data_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTU_rs485_interface
76 --signal rx_busy_sig : std_logic; -- initialized in FTU_rs485_interface
77
78 signal block_valid_sig : std_logic; -- initialized in FTU_rs485_receiver
79 signal data_block_sig : std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0); -- initialized in FTU_rs485_receiver
80
81 signal int_new_DACs_sig : std_logic; -- initialized in FTU_rs485_interpreter
82 signal int_new_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter
83 signal int_new_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter
84 signal int_read_rates_sig : std_logic; -- initialized in FTU_rs485_interpreter
85 signal int_read_DACs_sig : std_logic; -- initialized in FTU_rs485_interpreter
86 signal int_read_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter
87 signal int_read_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter
88 signal int_ping_pong_sig : std_logic; -- initialized in FTU_rs485_interpreter
89
90 signal txcnt : integer range 0 to (RS485_BLOCK_WIDTH / 8) := 0; -- count 28 1-byte frames
91
92 signal reset_crc_sig : std_logic := '0';
93 signal crc_enable_sig : std_logic := '0';
94 signal crc_input_sig : std_logic_vector(RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
95 signal crc_sig : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0) := (others => '0');
96 signal crc_sig_inv : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0) := (others => '0');
97 signal crc_error_cnt_sig : integer range 0 to 255 := 0;
98
99 component ucrc_par
100 generic(
101 POLYNOMIAL : std_logic_vector;
102 INIT_VALUE : std_logic_vector;
103 DATA_WIDTH : integer range 2 to 256;
104 SYNC_RESET : integer range 0 to 1
105 );
106 port(
107 clk_i : in std_logic;
108 rst_i : in std_logic;
109 clken_i : in std_logic;
110 data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
111 match_o : out std_logic;
112 crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)
113 );
114 end component;
115
116 component FTU_rs485_receiver
117 port(
118 rec_clk : in std_logic;
119 --rx_busy : in std_logic;
120 rec_din : in std_logic_vector(7 downto 0);
121 rec_den : in std_logic;
122 rec_dout : out std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0);
123 rec_valid : out std_logic
124 );
125 end component;
126
127 component FTU_rs485_interpreter
128 port(
129 clk : IN std_logic;
130 data_block : IN std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0);
131 block_valid : IN std_logic;
132 brd_add : IN std_logic_vector(5 downto 0);
133 crc_error_cnt : OUT integer range 0 to 255;
134 int_new_DACs : OUT std_logic;
135 int_new_enables : OUT std_logic;
136 int_new_prescaling : OUT std_logic;
137 int_read_rates : OUT std_logic;
138 int_read_DACs : OUT std_logic;
139 int_read_enables : OUT std_logic;
140 int_read_prescaling : OUT std_logic;
141 int_ping_pong : OUT std_logic;
142 dac_array_rs485_out : OUT dac_array_type;
143 enable_array_rs485_out : OUT enable_array_type;
144 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
145 );
146 end component;
147
148 component FTU_rs485_interface
149 port(
150 clk : IN std_logic;
151 -- RS485
152 rx_d : IN std_logic;
153 rx_en : OUT std_logic;
154 tx_d : OUT std_logic;
155 tx_en : OUT std_logic;
156 -- FPGA
157 rx_data : OUT std_logic_vector (7 DOWNTO 0);
158 --rx_busy : OUT std_logic := '0';
159 rx_valid : OUT std_logic := '0';
160 tx_data : IN std_logic_vector (7 DOWNTO 0);
161 tx_busy : OUT std_logic := '0';
162 tx_start : IN std_logic
163 );
164 end component;
165
166 type FTU_rs485_control_StateType is (INIT, RECEIVE,
167 READ_RATES_WAIT, READ_DAC_WAIT, READ_ENABLE_WAIT, READ_PRESCALING_WAIT,
168 READ_RATES_WAIT_2, READ_DAC_WAIT_2, READ_ENABLE_WAIT_2, READ_PRESCALING_WAIT_2,
169 SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT, PING_PONG_WAIT,
170 SET_DAC_WAIT_2, SET_ENABLE_WAIT_2, SET_PRESCALING_WAIT_2, PING_PONG_WAIT_2,
171 READ_RATES_TRANSMIT, READ_DAC_TRANSMIT, READ_ENABLE_TRANSMIT, READ_PRESCALING_TRANSMIT,
172 SET_DAC_TRANSMIT, SET_ENABLE_TRANSMIT, SET_PRESCALING_TRANSMIT, PING_PONG_TRANSMIT);
173 signal FTU_rs485_control_State : FTU_rs485_control_StateType;
174
175begin
176
177 crc_sig <= crc_sig_inv(0) & crc_sig_inv(1) & crc_sig_inv(2) & crc_sig_inv(3) & crc_sig_inv(4) & crc_sig_inv(5) & crc_sig_inv(6) & crc_sig_inv(7);
178
179 Inst_ucrc_par : ucrc_par
180 generic map(
181 POLYNOMIAL => CRC_POLYNOMIAL,
182 INIT_VALUE => CRC_INIT_VALUE,
183 DATA_WIDTH => 216,
184 SYNC_RESET => 1
185 )
186 port map(
187 clk_i => main_clk,
188 rst_i => reset_crc_sig,
189 clken_i => crc_enable_sig,
190 data_i => crc_input_sig,
191 match_o => open,
192 crc_o => crc_sig_inv
193 );
194
195 Inst_FTU_rs485_receiver : FTU_rs485_receiver
196 port map(
197 rec_clk => main_clk,
198 --rx_busy =>,
199 rec_din => rx_data_sig,
200 rec_den => rx_valid_sig,
201 rec_dout => data_block_sig,
202 rec_valid => block_valid_sig
203 );
204
205 Inst_FTU_rs485_interpreter : FTU_rs485_interpreter
206 port map(
207 clk => main_clk,
208 data_block => data_block_sig,
209 block_valid => block_valid_sig,
210 brd_add => brd_add,
211 crc_error_cnt => crc_error_cnt_sig,
212 int_new_DACs => int_new_DACs_sig,
213 int_new_enables => int_new_enables_sig,
214 int_new_prescaling => int_new_prescaling_sig,
215 int_read_rates => int_read_rates_sig,
216 int_read_DACs => int_read_DACs_sig,
217 int_read_enables => int_read_enables_sig,
218 int_read_prescaling => int_read_prescaling_sig,
219 int_ping_pong => int_ping_pong_sig,
220 dac_array_rs485_out => dac_array_rs485_out,
221 enable_array_rs485_out => enable_array_rs485_out,
222 prescaling_rs485_out => prescaling_rs485_out
223 );
224
225 Inst_FTU_rs485_interface : FTU_rs485_interface
226 port map(
227 clk => main_clk,
228 -- RS485
229 rx_d => rx_d,
230 rx_en => rx_en,
231 tx_d => tx_d,
232 tx_en => tx_en,
233 -- FPGA
234 rx_data => rx_data_sig,
235 --rx_busy => rx_busy_sig,
236 rx_valid => rx_valid_sig,
237 tx_data => tx_data_sig,
238 tx_busy => tx_busy_sig,
239 tx_start => tx_start_sig
240 );
241
242 --FTU RS485 control finite state machine
243
244 FTU_rs485_control_FSM: process (main_clk)
245 begin
246 if Rising_edge(main_clk) then
247 case FTU_rs485_control_State is
248
249 when INIT => -- reset CRC register
250 reset_crc_sig <= '1';
251 FTU_rs485_control_State <= RECEIVE;
252
253 when RECEIVE => -- default state, receiver on, no transmission
254 reset_crc_sig <= '0';
255 crc_enable_sig <= '0';
256 tx_start_sig <= '0';
257 if (int_new_DACs_sig = '1') then
258 new_DACs <= '1';
259 new_enables <= '0';
260 new_prescaling <= '0';
261 read_rates <= '0';
262 read_DACs <= '0';
263 read_enables <= '0';
264 read_prescaling <= '0';
265 ping_pong <= '0';
266 FTU_rs485_control_State <= SET_DAC_WAIT;
267 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '1') then
268 new_DACs <= '0';
269 new_enables <= '1';
270 new_prescaling <= '0';
271 read_rates <= '0';
272 read_DACs <= '0';
273 read_enables <= '0';
274 read_prescaling <= '0';
275 ping_pong <= '0';
276 FTU_rs485_control_State <= SET_ENABLE_WAIT;
277 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '1') then
278 new_DACs <= '0';
279 new_enables <= '0';
280 new_prescaling <= '1';
281 read_rates <= '0';
282 read_DACs <= '0';
283 read_enables <= '0';
284 read_prescaling <= '0';
285 ping_pong <= '0';
286 FTU_rs485_control_State <= SET_PRESCALING_WAIT;
287 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
288 int_read_rates_sig = '1') then
289 new_DACs <= '0';
290 new_enables <= '0';
291 new_prescaling <= '0';
292 read_rates <= '1';
293 read_DACs <= '0';
294 read_enables <= '0';
295 read_prescaling <= '0';
296 ping_pong <= '0';
297 FTU_rs485_control_State <= READ_RATES_WAIT;
298 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
299 int_read_rates_sig = '0' and int_read_DACs_sig = '1') then
300 new_DACs <= '0';
301 new_enables <= '0';
302 new_prescaling <= '0';
303 read_rates <= '0';
304 read_DACs <= '1';
305 read_enables <= '0';
306 read_prescaling <= '0';
307 ping_pong <= '0';
308 FTU_rs485_control_State <= READ_DAC_WAIT;
309 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
310 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '1') then
311 new_DACs <= '0';
312 new_enables <= '0';
313 new_prescaling <= '0';
314 read_rates <= '0';
315 read_DACs <= '0';
316 read_enables <= '1';
317 read_prescaling <= '0';
318 ping_pong <= '0';
319 FTU_rs485_control_State <= READ_ENABLE_WAIT;
320 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
321 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '0' and int_read_prescaling_sig = '1') then
322 new_DACs <= '0';
323 new_enables <= '0';
324 new_prescaling <= '0';
325 read_rates <= '0';
326 read_DACs <= '0';
327 read_enables <= '0';
328 read_prescaling <= '1';
329 ping_pong <= '0';
330 FTU_rs485_control_State <= READ_PRESCALING_WAIT;
331 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
332 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '0' and int_read_prescaling_sig = '0' and
333 int_ping_pong_sig = '1') then
334 new_DACs <= '0';
335 new_enables <= '0';
336 new_prescaling <= '0';
337 read_rates <= '0';
338 read_DACs <= '0';
339 read_enables <= '0';
340 read_prescaling <= '0';
341 ping_pong <= '1';
342 FTU_rs485_control_State <= PING_PONG_WAIT;
343 else
344 new_DACs <= '0';
345 new_enables <= '0';
346 new_prescaling <= '0';
347 read_rates <= '0';
348 read_DACs <= '0';
349 read_enables <= '0';
350 read_prescaling <= '0';
351 ping_pong <= '0';
352 FTU_rs485_control_State <= RECEIVE;
353 end if;
354
355 when SET_DAC_WAIT=> -- wait until FTU control says "done" and then answer to FTM
356 if (DACs_ready = '1') then
357 new_DACs <= '0';
358 crc_enable_sig <= '1';
359 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
360 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
361 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
362 & "00000000"
363 & conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0)
364 & conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0)
365 & conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0)
366 & conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0)
367 & conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0) & "00000000"
368 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
369 FTU_rs485_control_State <= SET_DAC_WAIT_2;
370 else
371 new_DACs <= '1';
372 FTU_rs485_control_State <= SET_DAC_WAIT;
373 end if;
374
375 when SET_DAC_WAIT_2 => -- wait one cycle for CRC calculation
376 crc_enable_sig <= '0';
377 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
378
379 when SET_ENABLE_WAIT => -- wait until FTU control says "done" and then answer to FTM
380 if (enables_ready = '1') then
381 new_enables <= '0';
382 crc_enable_sig <= '1';
383 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
384 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
385 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
386 & "00000000" & "00000000" & "00000000"
387 & enable_array_rs485_in(3)(15 downto 8) & enable_array_rs485_in(3)(7 downto 0)
388 & enable_array_rs485_in(2)(15 downto 8) & enable_array_rs485_in(2)(7 downto 0)
389 & enable_array_rs485_in(1)(15 downto 8) & enable_array_rs485_in(1)(7 downto 0)
390 & enable_array_rs485_in(0)(15 downto 8) & enable_array_rs485_in(0)(7 downto 0) & "00000011"
391 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
392 FTU_rs485_control_State <= SET_ENABLE_WAIT_2;
393 else
394 new_enables <= '1';
395 FTU_rs485_control_State <= SET_ENABLE_WAIT;
396 end if;
397
398 when SET_ENABLE_WAIT_2 => -- wait one cycle for CRC calculation
399 crc_enable_sig <= '0';
400 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
401
402 when SET_PRESCALING_WAIT => -- wait until FTU control says "done" and then answer to FTM
403 if (prescaling_ready = '1') then
404 new_prescaling <= '0';
405 crc_enable_sig <= '1';
406 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
407 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
408 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
409 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
410 & "00000000" & "00000000" & "00000000" & "00000000"
411 & overflow_array_rs485_in & prescaling_rs485_in & "00000110"
412 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
413 FTU_rs485_control_State <= SET_PRESCALING_WAIT_2;
414 else
415 new_prescaling <= '1';
416 FTU_rs485_control_State <= SET_PRESCALING_WAIT;
417 end if;
418
419 when SET_PRESCALING_WAIT_2 => -- wait one cycle for CRC calculation
420 crc_enable_sig <= '0';
421 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
422
423 when READ_RATES_WAIT => -- wait until FTU control says "done" and then answer to FTM
424 if (rates_ready = '1') then
425 read_rates <= '0';
426 crc_enable_sig <= '1';
427 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
428 & overflow_array_rs485_in
429 & conv_std_logic_vector(rate_array_rs485(4),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(4),32)(23 downto 16)
430 & conv_std_logic_vector(rate_array_rs485(4),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(4),32)(7 downto 0)
431 & conv_std_logic_vector(rate_array_rs485(3),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(3),32)(23 downto 16)
432 & conv_std_logic_vector(rate_array_rs485(3),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(3),32)(7 downto 0)
433 & conv_std_logic_vector(rate_array_rs485(2),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(2),32)(23 downto 16)
434 & conv_std_logic_vector(rate_array_rs485(2),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(2),32)(7 downto 0)
435 & conv_std_logic_vector(rate_array_rs485(1),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(1),32)(23 downto 16)
436 & conv_std_logic_vector(rate_array_rs485(1),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(1),32)(7 downto 0)
437 & conv_std_logic_vector(rate_array_rs485(0),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(0),32)(23 downto 16)
438 & conv_std_logic_vector(rate_array_rs485(0),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(0),32)(7 downto 0) & "00000010"
439 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
440 FTU_rs485_control_State <= READ_RATES_WAIT_2;
441 else
442 read_rates <= '1';
443 FTU_rs485_control_State <= READ_RATES_WAIT;
444 end if;
445
446 when READ_RATES_WAIT_2 => -- wait one cycle for CRC calculation
447 crc_enable_sig <= '0';
448 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
449
450 when READ_DAC_WAIT => -- wait until FTU control says "done" and then answer to FTM
451 if (DACs_ready = '1') then
452 read_DACs <= '0';
453 crc_enable_sig <= '1';
454 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
455 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
456 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
457 & "00000000"
458 & conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0)
459 & conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0)
460 & conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0)
461 & conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0)
462 & conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0) & "00000001"
463 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
464 FTU_rs485_control_State <= READ_DAC_WAIT_2;
465 else
466 read_DACs <= '1';
467 FTU_rs485_control_State <= READ_DAC_WAIT;
468 end if;
469
470 when READ_DAC_WAIT_2 => -- wait one cycle for CRC calculation
471 crc_enable_sig <= '0';
472 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
473
474 when READ_ENABLE_WAIT => -- wait until FTU control says "done" and then answer to FTM
475 if (enables_ready = '1') then
476 read_enables <= '0';
477 crc_enable_sig <= '1';
478 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
479 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
480 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
481 & "00000000" & "00000000" & "00000000"
482 & enable_array_rs485_in(3)(15 downto 8) & enable_array_rs485_in(3)(7 downto 0)
483 & enable_array_rs485_in(2)(15 downto 8) & enable_array_rs485_in(2)(7 downto 0)
484 & enable_array_rs485_in(1)(15 downto 8) & enable_array_rs485_in(1)(7 downto 0)
485 & enable_array_rs485_in(0)(15 downto 8) & enable_array_rs485_in(0)(7 downto 0) & "00000100"
486 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
487 FTU_rs485_control_State <= READ_ENABLE_WAIT_2;
488 else
489 read_enables <= '1';
490 FTU_rs485_control_State <= READ_ENABLE_WAIT;
491 end if;
492
493 when READ_ENABLE_WAIT_2 => -- wait one cycle for CRC calculation
494 crc_enable_sig <= '0';
495 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
496
497 when READ_PRESCALING_WAIT => -- wait until FTU control says "done" and then answer to FTM
498 if (prescaling_ready = '1') then
499 read_prescaling <= '0';
500 crc_enable_sig <= '1';
501 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
502 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
503 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
504 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
505 & "00000000" & "00000000" & "00000000" & "00000000"
506 & overflow_array_rs485_in & prescaling_rs485_in & "00000111"
507 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
508 FTU_rs485_control_State <= READ_PRESCALING_WAIT_2;
509 else
510 read_prescaling <= '1';
511 FTU_rs485_control_State <= READ_PRESCALING_WAIT;
512 end if;
513
514 when READ_PRESCALING_WAIT_2 => -- wait one cycle for CRC calculation
515 crc_enable_sig <= '0';
516 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
517
518 when PING_PONG_WAIT => -- wait until FTU control says "done" and then answer to FTM
519 if (ping_pong_ready = '1') then
520 ping_pong <= '0';
521 crc_enable_sig <= '1';
522 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
523 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
524 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
525 & "00000000" & "00000000" & "00000000"
526 & dna(63 downto 0) & "00000101"
527 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
528 FTU_rs485_control_State <= PING_PONG_WAIT_2;
529 else
530 ping_pong <= '1';
531 FTU_rs485_control_State <= PING_PONG_WAIT;
532 end if;
533
534 when PING_PONG_WAIT_2 => -- wait one cycle for CRC calculation
535 crc_enable_sig <= '0';
536 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
537
538 when SET_DAC_TRANSMIT =>
539 if tx_busy_sig = '0' then
540 if txcnt = 0 then -- start delimiter
541 txcnt <= txcnt + 1;
542 tx_data_sig <= RS485_START_DELIM;
543 tx_start_sig <= '1';
544 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
545 elsif txcnt = 1 then -- FTM address
546 txcnt <= txcnt + 1;
547 tx_data_sig <= FTM_ADDRESS;
548 tx_start_sig <= '1';
549 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
550 elsif txcnt = 2 then -- board address
551 txcnt <= txcnt + 1;
552 tx_data_sig <= "00" & brd_add;
553 tx_start_sig <= '1';
554 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
555 elsif txcnt = 3 then -- firmware ID
556 txcnt <= txcnt + 1;
557 tx_data_sig <= FIRMWARE_ID;
558 tx_start_sig <= '1';
559 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
560 elsif txcnt = 4 then -- mirrored command
561 txcnt <= txcnt + 1;
562 tx_data_sig <= "00000000";
563 tx_start_sig <= '1';
564 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
565 elsif txcnt = 5 then -- data: DAC A low
566 txcnt <= txcnt + 1;
567 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0);
568 tx_start_sig <= '1';
569 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
570 elsif txcnt = 6 then -- data: DAC A high
571 txcnt <= txcnt + 1;
572 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8);
573 tx_start_sig <= '1';
574 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
575 elsif txcnt = 7 then -- data: DAC B low
576 txcnt <= txcnt + 1;
577 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0);
578 tx_start_sig <= '1';
579 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
580 elsif txcnt = 8 then -- data: DAC B high
581 txcnt <= txcnt + 1;
582 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8);
583 tx_start_sig <= '1';
584 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
585 elsif txcnt = 9 then -- data: DAC C low
586 txcnt <= txcnt + 1;
587 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0);
588 tx_start_sig <= '1';
589 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
590 elsif txcnt = 10 then -- data: DAC C high
591 txcnt <= txcnt + 1;
592 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8);
593 tx_start_sig <= '1';
594 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
595 elsif txcnt = 11 then -- data: DAC D low
596 txcnt <= txcnt + 1;
597 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0);
598 tx_start_sig <= '1';
599 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
600 elsif txcnt = 12 then -- data: DAC D high
601 txcnt <= txcnt + 1;
602 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8);
603 tx_start_sig <= '1';
604 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
605 elsif txcnt = 13 then -- data: DAC E low
606 txcnt <= txcnt + 1;
607 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0);
608 tx_start_sig <= '1';
609 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
610 elsif txcnt = 14 then -- data: DAC E high
611 txcnt <= txcnt + 1;
612 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8);
613 tx_start_sig <= '1';
614 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
615 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
616 txcnt <= txcnt + 1;
617 tx_data_sig <= "00000000";
618 tx_start_sig <= '1';
619 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
620 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
621 txcnt <= txcnt + 1;
622 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
623 tx_start_sig <= '1';
624 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
625 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
626 txcnt <= txcnt + 1;
627 tx_data_sig <= crc_sig;
628 tx_start_sig <= '1';
629 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
630 else -- transmission finished
631 txcnt <= 0;
632 reset_crc_sig <= '1';
633 FTU_rs485_control_State <= RECEIVE;
634 end if;
635 else
636 tx_start_sig <= '0';
637 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
638 end if;
639
640 when SET_ENABLE_TRANSMIT =>
641 if tx_busy_sig = '0' then
642 if txcnt = 0 then -- start delimiter
643 txcnt <= txcnt + 1;
644 tx_data_sig <= RS485_START_DELIM;
645 tx_start_sig <= '1';
646 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
647 elsif txcnt = 1 then -- FTM address
648 txcnt <= txcnt + 1;
649 tx_data_sig <= FTM_ADDRESS;
650 tx_start_sig <= '1';
651 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
652 elsif txcnt = 2 then -- board address
653 txcnt <= txcnt + 1;
654 tx_data_sig <= "00" & brd_add;
655 tx_start_sig <= '1';
656 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
657 elsif txcnt = 3 then -- firmware ID
658 txcnt <= txcnt + 1;
659 tx_data_sig <= FIRMWARE_ID;
660 tx_start_sig <= '1';
661 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
662 elsif txcnt = 4 then -- mirrored command
663 txcnt <= txcnt + 1;
664 tx_data_sig <= "00000011";
665 tx_start_sig <= '1';
666 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
667 elsif txcnt = 5 then -- data: enable pattern A7-0
668 txcnt <= txcnt + 1;
669 tx_data_sig <= enable_array_rs485_in(0)(7 downto 0);
670 tx_start_sig <= '1';
671 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
672 elsif txcnt = 6 then -- data: enable pattern A8
673 txcnt <= txcnt + 1;
674 tx_data_sig <= enable_array_rs485_in(0)(15 downto 8);
675 tx_start_sig <= '1';
676 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
677 elsif txcnt = 7 then -- data: enable pattern B7-0
678 txcnt <= txcnt + 1;
679 tx_data_sig <= enable_array_rs485_in(1)(7 downto 0);
680 tx_start_sig <= '1';
681 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
682 elsif txcnt = 8 then -- data: enable pattern B8
683 txcnt <= txcnt + 1;
684 tx_data_sig <= enable_array_rs485_in(1)(15 downto 8);
685 tx_start_sig <= '1';
686 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
687 elsif txcnt = 9 then -- data: enable pattern C7-0
688 txcnt <= txcnt + 1;
689 tx_data_sig <= enable_array_rs485_in(2)(7 downto 0);
690 tx_start_sig <= '1';
691 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
692 elsif txcnt = 10 then -- data: enable pattern C8
693 txcnt <= txcnt + 1;
694 tx_data_sig <= enable_array_rs485_in(2)(15 downto 8);
695 tx_start_sig <= '1';
696 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
697 elsif txcnt = 11 then -- data: enable pattern D7-0
698 txcnt <= txcnt + 1;
699 tx_data_sig <= enable_array_rs485_in(3)(7 downto 0);
700 tx_start_sig <= '1';
701 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
702 elsif txcnt = 12 then -- data: enable pattern D8
703 txcnt <= txcnt + 1;
704 tx_data_sig <= enable_array_rs485_in(3)(15 downto 8);
705 tx_start_sig <= '1';
706 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
707 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
708 txcnt <= txcnt + 1;
709 tx_data_sig <= "00000000";
710 tx_start_sig <= '1';
711 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
712 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
713 txcnt <= txcnt + 1;
714 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
715 tx_start_sig <= '1';
716 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
717 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
718 txcnt <= txcnt + 1;
719 tx_data_sig <= crc_sig;
720 tx_start_sig <= '1';
721 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
722 else -- transmission finished
723 txcnt <= 0;
724 reset_crc_sig <= '1';
725 FTU_rs485_control_State <= RECEIVE;
726 end if;
727 else
728 tx_start_sig <= '0';
729 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
730 end if;
731
732 when SET_PRESCALING_TRANSMIT =>
733 if tx_busy_sig = '0' then
734 if txcnt = 0 then -- start delimiter
735 txcnt <= txcnt + 1;
736 tx_data_sig <= RS485_START_DELIM;
737 tx_start_sig <= '1';
738 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
739 elsif txcnt = 1 then -- FTM address
740 txcnt <= txcnt + 1;
741 tx_data_sig <= FTM_ADDRESS;
742 tx_start_sig <= '1';
743 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
744 elsif txcnt = 2 then -- board address
745 txcnt <= txcnt + 1;
746 tx_data_sig <= "00" & brd_add;
747 tx_start_sig <= '1';
748 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
749 elsif txcnt = 3 then -- firmware ID
750 txcnt <= txcnt + 1;
751 tx_data_sig <= FIRMWARE_ID;
752 tx_start_sig <= '1';
753 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
754 elsif txcnt = 4 then -- mirrored command
755 txcnt <= txcnt + 1;
756 tx_data_sig <= "00000110";
757 tx_start_sig <= '1';
758 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
759 elsif txcnt = 5 then -- data: prescaling
760 txcnt <= txcnt + 1;
761 tx_data_sig <= prescaling_rs485_in;
762 tx_start_sig <= '1';
763 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
764 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
765 txcnt <= txcnt + 1;
766 tx_data_sig <= "00000000";
767 tx_start_sig <= '1';
768 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
769 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
770 txcnt <= txcnt + 1;
771 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
772 tx_start_sig <= '1';
773 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
774 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
775 txcnt <= txcnt + 1;
776 tx_data_sig <= crc_sig;
777 tx_start_sig <= '1';
778 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
779 else -- transmission finished
780 txcnt <= 0;
781 reset_crc_sig <= '1';
782 FTU_rs485_control_State <= RECEIVE;
783 end if;
784 else
785 tx_start_sig <= '0';
786 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
787 end if;
788
789 when READ_RATES_TRANSMIT =>
790 if tx_busy_sig = '0' then
791 if txcnt = 0 then -- start delimiter
792 txcnt <= txcnt + 1;
793 tx_data_sig <= RS485_START_DELIM;
794 tx_start_sig <= '1';
795 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
796 elsif txcnt = 1 then -- FTM address
797 txcnt <= txcnt + 1;
798 tx_data_sig <= FTM_ADDRESS;
799 tx_start_sig <= '1';
800 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
801 elsif txcnt = 2 then -- board address
802 txcnt <= txcnt + 1;
803 tx_data_sig <= "00" & brd_add;
804 tx_start_sig <= '1';
805 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
806 elsif txcnt = 3 then -- firmware ID
807 txcnt <= txcnt + 1;
808 tx_data_sig <= FIRMWARE_ID;
809 tx_start_sig <= '1';
810 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
811 elsif txcnt = 4 then -- mirrored command
812 txcnt <= txcnt + 1;
813 tx_data_sig <= "00000010";
814 tx_start_sig <= '1';
815 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
816 elsif txcnt = 5 then -- data: counter A 7...0
817 txcnt <= txcnt + 1;
818 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(7 downto 0);
819 tx_start_sig <= '1';
820 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
821 elsif txcnt = 6 then -- data: counter A 15...8
822 txcnt <= txcnt + 1;
823 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(15 downto 8);
824 tx_start_sig <= '1';
825 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
826 elsif txcnt = 7 then -- data: counter A 23...16
827 txcnt <= txcnt + 1;
828 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(23 downto 16);
829 tx_start_sig <= '1';
830 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
831 elsif txcnt = 8 then -- data: counter A 31...24
832 txcnt <= txcnt + 1;
833 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(31 downto 24);
834 tx_start_sig <= '1';
835 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
836 elsif txcnt = 9 then -- data: counter B 7...0
837 txcnt <= txcnt + 1;
838 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(7 downto 0);
839 tx_start_sig <= '1';
840 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
841 elsif txcnt = 10 then -- data: counter B 15...8
842 txcnt <= txcnt + 1;
843 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(15 downto 8);
844 tx_start_sig <= '1';
845 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
846 elsif txcnt = 11 then -- data: counter B 23...16
847 txcnt <= txcnt + 1;
848 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(23 downto 16);
849 tx_start_sig <= '1';
850 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
851 elsif txcnt = 12 then -- data: counter B 31...24
852 txcnt <= txcnt + 1;
853 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(31 downto 24);
854 tx_start_sig <= '1';
855 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
856 elsif txcnt = 13 then -- data: counter C 7...0
857 txcnt <= txcnt + 1;
858 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(7 downto 0);
859 tx_start_sig <= '1';
860 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
861 elsif txcnt = 14 then -- data: counter C 15...8
862 txcnt <= txcnt + 1;
863 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(15 downto 8);
864 tx_start_sig <= '1';
865 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
866 elsif txcnt = 15 then -- data: counter C 23...16
867 txcnt <= txcnt + 1;
868 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(23 downto 16);
869 tx_start_sig <= '1';
870 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
871 elsif txcnt = 16 then -- data: counter C 31...24
872 txcnt <= txcnt + 1;
873 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(31 downto 24);
874 tx_start_sig <= '1';
875 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
876 elsif txcnt = 17 then -- data: counter D 7...0
877 txcnt <= txcnt + 1;
878 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(7 downto 0);
879 tx_start_sig <= '1';
880 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
881 elsif txcnt = 18 then -- data: counter D 15...8
882 txcnt <= txcnt + 1;
883 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(15 downto 8);
884 tx_start_sig <= '1';
885 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
886 elsif txcnt = 19 then -- data: counter D 23...16
887 txcnt <= txcnt + 1;
888 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(23 downto 16);
889 tx_start_sig <= '1';
890 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
891 elsif txcnt = 20 then -- data: counter D 31...24
892 txcnt <= txcnt + 1;
893 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(31 downto 24);
894 tx_start_sig <= '1';
895 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
896 elsif txcnt = 21 then -- data: trigger counter 7...0
897 txcnt <= txcnt + 1;
898 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(7 downto 0);
899 tx_start_sig <= '1';
900 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
901 elsif txcnt = 22 then -- data: trigger counter 15...8
902 txcnt <= txcnt + 1;
903 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(15 downto 8);
904 tx_start_sig <= '1';
905 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
906 elsif txcnt = 23 then -- data: trigger counter 23...16
907 txcnt <= txcnt + 1;
908 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(23 downto 16);
909 tx_start_sig <= '1';
910 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
911 elsif txcnt = 24 then -- data: trigger counter 31...24
912 txcnt <= txcnt + 1;
913 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(31 downto 24);
914 tx_start_sig <= '1';
915 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
916 elsif txcnt = 25 then -- data: overflow register
917 txcnt <= txcnt + 1;
918 tx_data_sig <= overflow_array_rs485_in;
919 tx_start_sig <= '1';
920 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
921 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
922 txcnt <= txcnt + 1;
923 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
924 tx_start_sig <= '1';
925 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
926 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
927 txcnt <= txcnt + 1;
928 tx_data_sig <= crc_sig;
929 tx_start_sig <= '1';
930 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
931 else -- transmission finished
932 txcnt <= 0;
933 reset_crc_sig <= '1';
934 FTU_rs485_control_State <= RECEIVE;
935 end if;
936 else
937 tx_start_sig <= '0';
938 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
939 end if;
940
941 when READ_DAC_TRANSMIT =>
942 if tx_busy_sig = '0' then
943 if txcnt = 0 then -- start delimiter
944 txcnt <= txcnt + 1;
945 tx_data_sig <= RS485_START_DELIM;
946 tx_start_sig <= '1';
947 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
948 elsif txcnt = 1 then -- FTM address
949 txcnt <= txcnt + 1;
950 tx_data_sig <= FTM_ADDRESS;
951 tx_start_sig <= '1';
952 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
953 elsif txcnt = 2 then -- board address
954 txcnt <= txcnt + 1;
955 tx_data_sig <= "00" & brd_add;
956 tx_start_sig <= '1';
957 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
958 elsif txcnt = 3 then -- firmware ID
959 txcnt <= txcnt + 1;
960 tx_data_sig <= FIRMWARE_ID;
961 tx_start_sig <= '1';
962 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
963 elsif txcnt = 4 then -- mirrored command
964 txcnt <= txcnt + 1;
965 tx_data_sig <= "00000001";
966 tx_start_sig <= '1';
967 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
968 elsif txcnt = 5 then -- data: DAC A low
969 txcnt <= txcnt + 1;
970 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0);
971 tx_start_sig <= '1';
972 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
973 elsif txcnt = 6 then -- data: DAC A high
974 txcnt <= txcnt + 1;
975 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8);
976 tx_start_sig <= '1';
977 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
978 elsif txcnt = 7 then -- data: DAC B low
979 txcnt <= txcnt + 1;
980 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0);
981 tx_start_sig <= '1';
982 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
983 elsif txcnt = 8 then -- data: DAC B high
984 txcnt <= txcnt + 1;
985 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8);
986 tx_start_sig <= '1';
987 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
988 elsif txcnt = 9 then -- data: DAC C low
989 txcnt <= txcnt + 1;
990 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0);
991 tx_start_sig <= '1';
992 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
993 elsif txcnt = 10 then -- data: DAC C high
994 txcnt <= txcnt + 1;
995 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8);
996 tx_start_sig <= '1';
997 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
998 elsif txcnt = 11 then -- data: DAC D low
999 txcnt <= txcnt + 1;
1000 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0);
1001 tx_start_sig <= '1';
1002 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1003 elsif txcnt = 12 then -- data: DAC D high
1004 txcnt <= txcnt + 1;
1005 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8);
1006 tx_start_sig <= '1';
1007 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1008 elsif txcnt = 13 then -- data: DAC E low
1009 txcnt <= txcnt + 1;
1010 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0);
1011 tx_start_sig <= '1';
1012 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1013 elsif txcnt = 14 then -- data: DAC E high
1014 txcnt <= txcnt + 1;
1015 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8);
1016 tx_start_sig <= '1';
1017 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1018 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
1019 txcnt <= txcnt + 1;
1020 tx_data_sig <= "00000000";
1021 tx_start_sig <= '1';
1022 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1023 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
1024 txcnt <= txcnt + 1;
1025 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
1026 tx_start_sig <= '1';
1027 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1028 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
1029 txcnt <= txcnt + 1;
1030 tx_data_sig <= crc_sig;
1031 tx_start_sig <= '1';
1032 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1033 else -- transmission finished
1034 txcnt <= 0;
1035 reset_crc_sig <= '1';
1036 FTU_rs485_control_State <= RECEIVE;
1037 end if;
1038 else
1039 tx_start_sig <= '0';
1040 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1041 end if;
1042
1043 when READ_ENABLE_TRANSMIT =>
1044 if tx_busy_sig = '0' then
1045 if txcnt = 0 then -- start delimiter
1046 txcnt <= txcnt + 1;
1047 tx_data_sig <= RS485_START_DELIM;
1048 tx_start_sig <= '1';
1049 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1050 elsif txcnt = 1 then -- FTM address
1051 txcnt <= txcnt + 1;
1052 tx_data_sig <= FTM_ADDRESS;
1053 tx_start_sig <= '1';
1054 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1055 elsif txcnt = 2 then -- board address
1056 txcnt <= txcnt + 1;
1057 tx_data_sig <= "00" & brd_add;
1058 tx_start_sig <= '1';
1059 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1060 elsif txcnt = 3 then -- firmware ID
1061 txcnt <= txcnt + 1;
1062 tx_data_sig <= FIRMWARE_ID;
1063 tx_start_sig <= '1';
1064 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1065 elsif txcnt = 4 then -- mirrored command
1066 txcnt <= txcnt + 1;
1067 tx_data_sig <= "00000100";
1068 tx_start_sig <= '1';
1069 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1070 elsif txcnt = 5 then -- data: enable pattern A7-0
1071 txcnt <= txcnt + 1;
1072 tx_data_sig <= enable_array_rs485_in(0)(7 downto 0);
1073 tx_start_sig <= '1';
1074 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1075 elsif txcnt = 6 then -- data: enable pattern A8
1076 txcnt <= txcnt + 1;
1077 tx_data_sig <= enable_array_rs485_in(0)(15 downto 8);
1078 tx_start_sig <= '1';
1079 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1080 elsif txcnt = 7 then -- data: enable pattern B7-0
1081 txcnt <= txcnt + 1;
1082 tx_data_sig <= enable_array_rs485_in(1)(7 downto 0);
1083 tx_start_sig <= '1';
1084 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1085 elsif txcnt = 8 then -- data: enable pattern B8
1086 txcnt <= txcnt + 1;
1087 tx_data_sig <= enable_array_rs485_in(1)(15 downto 8);
1088 tx_start_sig <= '1';
1089 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1090 elsif txcnt = 9 then -- data: enable pattern C7-0
1091 txcnt <= txcnt + 1;
1092 tx_data_sig <= enable_array_rs485_in(2)(7 downto 0);
1093 tx_start_sig <= '1';
1094 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1095 elsif txcnt = 10 then -- data: enable pattern C8
1096 txcnt <= txcnt + 1;
1097 tx_data_sig <= enable_array_rs485_in(2)(15 downto 8);
1098 tx_start_sig <= '1';
1099 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1100 elsif txcnt = 11 then -- data: enable pattern D7-0
1101 txcnt <= txcnt + 1;
1102 tx_data_sig <= enable_array_rs485_in(3)(7 downto 0);
1103 tx_start_sig <= '1';
1104 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1105 elsif txcnt = 12 then -- data: enable pattern D8
1106 txcnt <= txcnt + 1;
1107 tx_data_sig <= enable_array_rs485_in(3)(15 downto 8);
1108 tx_start_sig <= '1';
1109 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1110 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
1111 txcnt <= txcnt + 1;
1112 tx_data_sig <= "00000000";
1113 tx_start_sig <= '1';
1114 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1115 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
1116 txcnt <= txcnt + 1;
1117 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
1118 tx_start_sig <= '1';
1119 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1120 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
1121 txcnt <= txcnt + 1;
1122 tx_data_sig <= crc_sig;
1123 tx_start_sig <= '1';
1124 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1125 else -- transmission finished
1126 txcnt <= 0;
1127 reset_crc_sig <= '1';
1128 FTU_rs485_control_State <= RECEIVE;
1129 end if;
1130 else
1131 tx_start_sig <= '0';
1132 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1133 end if;
1134
1135 when READ_PRESCALING_TRANSMIT =>
1136 if tx_busy_sig = '0' then
1137 if txcnt = 0 then -- start delimiter
1138 txcnt <= txcnt + 1;
1139 tx_data_sig <= RS485_START_DELIM;
1140 tx_start_sig <= '1';
1141 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1142 elsif txcnt = 1 then -- FTM address
1143 txcnt <= txcnt + 1;
1144 tx_data_sig <= FTM_ADDRESS;
1145 tx_start_sig <= '1';
1146 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1147 elsif txcnt = 2 then -- board address
1148 txcnt <= txcnt + 1;
1149 tx_data_sig <= "00" & brd_add;
1150 tx_start_sig <= '1';
1151 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1152 elsif txcnt = 3 then -- firmware ID
1153 txcnt <= txcnt + 1;
1154 tx_data_sig <= FIRMWARE_ID;
1155 tx_start_sig <= '1';
1156 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1157 elsif txcnt = 4 then -- mirrored command
1158 txcnt <= txcnt + 1;
1159 tx_data_sig <= "00000111";
1160 tx_start_sig <= '1';
1161 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1162 elsif txcnt = 5 then -- data: prescaling
1163 txcnt <= txcnt + 1;
1164 tx_data_sig <= prescaling_rs485_in;
1165 tx_start_sig <= '1';
1166 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1167 elsif txcnt = 6 then -- data: overflow register
1168 txcnt <= txcnt + 1;
1169 tx_data_sig <= overflow_array_rs485_in;
1170 tx_start_sig <= '1';
1171 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1172 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
1173 txcnt <= txcnt + 1;
1174 tx_data_sig <= "00000000";
1175 tx_start_sig <= '1';
1176 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1177 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
1178 txcnt <= txcnt + 1;
1179 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
1180 tx_start_sig <= '1';
1181 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1182 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
1183 txcnt <= txcnt + 1;
1184 tx_data_sig <= crc_sig;
1185 tx_start_sig <= '1';
1186 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1187 else -- transmission finished
1188 txcnt <= 0;
1189 reset_crc_sig <= '1';
1190 FTU_rs485_control_State <= RECEIVE;
1191 end if;
1192 else
1193 tx_start_sig <= '0';
1194 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1195 end if;
1196
1197 when PING_PONG_TRANSMIT =>
1198 crc_enable_sig <= '0';
1199 if tx_busy_sig = '0' then
1200 if txcnt = 0 then -- start delimiter
1201 txcnt <= txcnt + 1;
1202 tx_data_sig <= RS485_START_DELIM;
1203 tx_start_sig <= '1';
1204 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1205 elsif txcnt = 1 then -- FTM address
1206 txcnt <= txcnt + 1;
1207 tx_data_sig <= FTM_ADDRESS;
1208 tx_start_sig <= '1';
1209 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1210 elsif txcnt = 2 then -- board address
1211 txcnt <= txcnt + 1;
1212 tx_data_sig <= "00" & brd_add;
1213 tx_start_sig <= '1';
1214 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1215 elsif txcnt = 3 then -- firmware ID
1216 txcnt <= txcnt + 1;
1217 tx_data_sig <= FIRMWARE_ID;
1218 tx_start_sig <= '1';
1219 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1220 elsif txcnt = 4 then -- mirrored command
1221 txcnt <= txcnt + 1;
1222 tx_data_sig <= "00000101";
1223 tx_start_sig <= '1';
1224 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1225 elsif txcnt = 5 then -- data: device DNA
1226 txcnt <= txcnt + 1;
1227 tx_data_sig <= dna(7 downto 0);
1228 tx_start_sig <= '1';
1229 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1230 elsif txcnt = 6 then -- data: device DNA
1231 txcnt <= txcnt + 1;
1232 tx_data_sig <= dna(15 downto 8);
1233 tx_start_sig <= '1';
1234 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1235 elsif txcnt = 7 then -- data: device DNA
1236 txcnt <= txcnt + 1;
1237 tx_data_sig <= dna(23 downto 16);
1238 tx_start_sig <= '1';
1239 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1240 elsif txcnt = 8 then -- data: device DNA
1241 txcnt <= txcnt + 1;
1242 tx_data_sig <= dna(31 downto 24);
1243 tx_start_sig <= '1';
1244 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1245 elsif txcnt = 9 then -- data: device DNA
1246 txcnt <= txcnt + 1;
1247 tx_data_sig <= dna(39 downto 32);
1248 tx_start_sig <= '1';
1249 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1250 elsif txcnt = 10 then -- data: device DNA
1251 txcnt <= txcnt + 1;
1252 tx_data_sig <= dna(47 downto 40);
1253 tx_start_sig <= '1';
1254 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1255 elsif txcnt = 11 then -- data: device DNA
1256 txcnt <= txcnt + 1;
1257 tx_data_sig <= dna(55 downto 48);
1258 tx_start_sig <= '1';
1259 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1260 elsif txcnt = 12 then -- data: device DNA
1261 txcnt <= txcnt + 1;
1262 tx_data_sig <= dna(63 downto 56);
1263 tx_start_sig <= '1';
1264 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1265 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
1266 txcnt <= txcnt + 1;
1267 tx_data_sig <= "00000000";
1268 tx_start_sig <= '1';
1269 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1270 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
1271 txcnt <= txcnt + 1;
1272 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
1273 tx_start_sig <= '1';
1274 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1275 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
1276 txcnt <= txcnt + 1;
1277 tx_data_sig <= crc_sig;
1278 tx_start_sig <= '1';
1279 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1280 else -- transmission finished
1281 txcnt <= 0;
1282 reset_crc_sig <= '1';
1283 FTU_rs485_control_State <= RECEIVE;
1284 end if;
1285 else
1286 tx_start_sig <= '0';
1287 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1288 end if;
1289
1290 end case;
1291 end if;
1292 end process FTU_rs485_control_FSM;
1293
1294end Behavioral;
1295
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