source: firmware/FTU/rs485/FTU_rs485_interpreter.vhd@ 9986

Last change on this file since 9986 was 9939, checked in by weitzel, 14 years ago
FTU RS485 interface is now connected to main control
File size: 8.1 KB
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1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 09/13/2010
6-- Design Name:
7-- Module Name: FTU_rs485_interpreter - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: command interpreter of FTU RS485 module
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26library ftu_definitions;
27USE ftu_definitions.ftu_array_types.all;
28USE ftu_definitions.ftu_constants.all;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32--library UNISIM;
33--use UNISIM.VComponents.all;
34
35entity FTU_rs485_interpreter is
36 port(
37 clk : IN std_logic;
38 data_block : IN std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0);
39 block_valid : IN std_logic;
40 brd_add : IN std_logic_vector(5 downto 0);
41 int_new_DACs : OUT std_logic := '0';
42 int_new_enables : OUT std_logic := '0';
43 int_new_prescaling : OUT std_logic := '0';
44 int_read_rates : OUT std_logic := '0';
45 int_read_DACs : OUT std_logic := '0';
46 int_read_enables : OUT std_logic := '0';
47 int_read_prescaling : OUT std_logic := '0';
48 dac_array_rs485_out : OUT dac_array_type;
49 enable_array_rs485_out : OUT enable_array_type;
50 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
51 );
52end FTU_rs485_interpreter;
53
54architecture Behavioral of FTU_rs485_interpreter is
55
56 signal block_valid_sr : std_logic_vector(3 downto 0) := (others => '0');
57
58 signal dac_array_rs485_out_sig : dac_array_type := DEFAULT_DAC;
59 signal enable_array_rs485_out_sig : enable_array_type := DEFAULT_ENABLE;
60 signal prescaling_rs485_out_sig : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(DEFAULT_PRESCALING,8);
61
62 type FTU_rs485_interpreter_StateType is (WAIT_FOR_DATA, CHECK_HEADER, DECODE);
63 signal FTU_rs485_interpreter_State : FTU_rs485_interpreter_StateType;
64
65begin
66
67 FTU_rs485_interpreter_FSM: process (clk)
68 begin
69 if Rising_edge(clk) then
70 case FTU_rs485_interpreter_State is
71
72 when WAIT_FOR_DATA => -- default state, waiting for valid 16-byte block
73 block_valid_sr <= block_valid_sr(2 downto 0) & block_valid;
74 int_new_DACs <= '0';
75 int_new_enables <= '0';
76 int_new_prescaling <= '0';
77 int_read_rates <= '0';
78 int_read_DACs <= '0';
79 int_read_enables <= '0';
80 int_read_prescaling <= '0';
81 if (block_valid_sr(3 downto 2) = "01") then -- rising edge of valid signal
82 FTU_rs485_interpreter_State <= CHECK_HEADER;
83 else
84 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
85 end if;
86
87 when CHECK_HEADER => -- check start delimiter and addresses
88 int_new_DACs <= '0';
89 int_new_enables <= '0';
90 int_new_prescaling <= '0';
91 int_read_rates <= '0';
92 int_read_DACs <= '0';
93 int_read_enables <= '0';
94 int_read_prescaling <= '0';
95 if (data_block(7 downto 0) = RS485_START_DELIM) and
96 (data_block(15 downto 8) = ("00" & brd_add)) and
97 (data_block(23 downto 16) = FTM_ADDRESS) then
98 FTU_rs485_interpreter_State <= DECODE;
99 else
100 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
101 end if;
102
103 when DECODE => -- decode instruction
104 if(data_block(31 downto 24) = "00000000") then
105 int_new_DACs <= '1';
106 int_new_enables <= '0';
107 int_new_prescaling <= '0';
108 int_read_rates <= '0';
109 int_read_DACs <= '0';
110 int_read_enables <= '0';
111 int_read_prescaling <= '0';
112 dac_array_rs485_out_sig <= (conv_integer(unsigned(data_block(43 downto 32))),
113 conv_integer(unsigned(data_block(59 downto 48))),
114 conv_integer(unsigned(data_block(75 downto 64))),
115 conv_integer(unsigned(data_block(91 downto 80))),
116 DEFAULT_DAC(4),
117 DEFAULT_DAC(5),
118 DEFAULT_DAC(6),
119 conv_integer(unsigned(data_block(107 downto 96)))
120 );
121 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
122 elsif (data_block(31 downto 24) = "00000001") then
123 int_new_DACs <= '0';
124 int_new_enables <= '0';
125 int_new_prescaling <= '0';
126 int_read_rates <= '0';
127 int_read_DACs <= '1';
128 int_read_enables <= '0';
129 int_read_prescaling <= '0';
130 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
131 elsif (data_block(31 downto 24) = "00000010") then
132 int_new_DACs <= '0';
133 int_new_enables <= '0';
134 int_new_prescaling <= '0';
135 int_read_rates <= '1';
136 int_read_DACs <= '0';
137 int_read_enables <= '0';
138 int_read_prescaling <= '0';
139 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
140 elsif (data_block(31 downto 24) = "00000011") then
141 int_new_DACs <= '0';
142 int_new_enables <= '1';
143 int_new_prescaling <= '0';
144 int_read_rates <= '0';
145 int_read_DACs <= '0';
146 int_read_enables <= '0';
147 int_read_prescaling <= '0';
148 enable_array_rs485_out_sig <= (data_block(47 downto 32),
149 data_block(63 downto 48),
150 data_block(79 downto 64),
151 data_block(95 downto 80)
152 );
153 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
154 elsif (data_block(31 downto 24) = "00000100") then
155 int_new_DACs <= '0';
156 int_new_enables <= '0';
157 int_new_prescaling <= '0';
158 int_read_rates <= '0';
159 int_read_DACs <= '0';
160 int_read_enables <= '1';
161 int_read_prescaling <= '0';
162 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
163 elsif (data_block(31 downto 24) = "00000110") then
164 int_new_DACs <= '0';
165 int_new_enables <= '0';
166 int_new_prescaling <= '1';
167 int_read_rates <= '0';
168 int_read_DACs <= '0';
169 int_read_enables <= '0';
170 int_read_prescaling <= '0';
171 prescaling_rs485_out_sig <= data_block(39 downto 32);
172 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
173 elsif (data_block(31 downto 24) = "00000111") then
174 int_new_DACs <= '0';
175 int_new_enables <= '0';
176 int_new_prescaling <= '0';
177 int_read_rates <= '0';
178 int_read_DACs <= '0';
179 int_read_enables <= '0';
180 int_read_prescaling <= '1';
181 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
182 else
183 int_new_DACs <= '0';
184 int_new_enables <= '0';
185 int_new_prescaling <= '0';
186 int_read_rates <= '0';
187 int_read_DACs <= '0';
188 int_read_enables <= '0';
189 int_read_prescaling <= '0';
190 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
191 end if;
192
193 end case;
194 end if;
195 end process FTU_rs485_interpreter_FSM;
196
197 dac_array_rs485_out <= dac_array_rs485_out_sig;
198 enable_array_rs485_out <= enable_array_rs485_out_sig;
199 prescaling_rs485_out <= prescaling_rs485_out_sig;
200
201end Behavioral;
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