Changeset 10058 for firmware/FTM
- Timestamp:
- 11/23/10 14:44:36 (14 years ago)
- Location:
- firmware/FTM/test_firmware/FTM_test8
- Files:
-
- 1 added
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FTM/test_firmware/FTM_test8/FTM_test8.vhd
r10046 r10058 16 16 -- Revision: 17 17 -- Revision 0.01 - File Created 18 -- Revision 0.02 - Some modifications, November 15, 2010, Q. Weitzel 18 19 -- Additional Comments: 19 20 -- … … 25 26 use IEEE.STD_LOGIC_UNSIGNED.ALL; 26 27 27 28 28 Library UNISIM; 29 29 use UNISIM.vcomponents.all; … … 34 34 --use UNISIM.VComponents.all; 35 35 36 37 36 -- library FTM_definitions_test3; 38 37 -- USE FTM_definitions_test3.ftm_array_types.all; 39 38 40 41 42 39 entity FTM_test8 is 43 40 port( 44 45 41 46 42 -- Clock 47 43 clk : IN STD_LOGIC; -- external clock from 48 44 -- oscillator U47 49 50 45 -- connection to the WIZnet W5300 ethernet controller 51 46 -- on IO-Bank 1 … … 123 118 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green 124 119 125 126 127 120 -- Clock conditioner LMK03000 128 121 -- on IO-Bank 3 … … 135 128 -- LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect 136 129 137 138 139 140 130 -- various RS-485 Interfaces 141 131 -- on IO-Bank 3 … … 280 270 end FTM_test8; 281 271 282 283 272 architecture Behavioral of FTM_test8 is 284 273 285 286 287 288 289 COMPONENT FTM_Test8_dcm 290 PORT( 291 CLKIN_IN : IN std_logic; 292 RST_IN : IN std_logic; 293 CLKFX_OUT : OUT std_logic; 294 CLK0_OUT : OUT std_logic; 295 LOCKED_OUT : OUT std_logic 296 ); 297 END COMPONENT; 298 299 274 COMPONENT FTM_Test8_dcm 275 PORT( 276 CLKIN_IN : IN std_logic; 277 RST_IN : IN std_logic; 278 CLKFX_OUT : OUT std_logic; 279 CLK0_OUT : OUT std_logic; 280 LOCKED_OUT : OUT std_logic 281 ); 282 END COMPONENT; 300 283 301 284 component FTM_test8_rs485_interface 302 285 GENERIC( 303 CLOCK_FREQUENCY : integer := 50000000; -- Hertz304 BAUD_RATE : integer := 250000-- bits / sec286 CLOCK_FREQUENCY : integer; -- Hertz 287 BAUD_RATE : integer -- bits / sec 305 288 ); 306 289 PORT( … … 313 296 -- FPGA 314 297 rx_data : OUT std_logic_vector(7 DOWNTO 0); 315 --rx_busy : OUT std_logic := '0';298 -- rx_busy : OUT std_logic := '0'; 316 299 rx_valid : OUT std_logic := '0'; 317 300 tx_data : IN std_logic_vector(7 DOWNTO 0); … … 323 306 signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up 324 307 signal clk_50M_sig : STD_LOGIC; 325 326 308 327 309 -- signal enable_sig : enable_array_type := DEFAULT_ENABLE; 328 329 310 330 311 signal rx_en_sig : STD_LOGIC := '0'; … … 339 320 signal FTM_test8_State, FTM_test8_NextState: FTM_test8_StateType; 340 321 341 342 343 344 345 322 begin 346 323 347 Inst_FTM_Test8_dcm: FTM_Test8_dcm PORT MAP( 348 CLKIN_IN => clk, 349 RST_IN => reset_sig, 350 CLKFX_OUT => clk_50M_sig, 351 CLK0_OUT => open, 352 LOCKED_OUT => open 353 ); 354 355 324 Inst_FTM_Test8_dcm: FTM_Test8_dcm PORT MAP( 325 CLKIN_IN => clk, 326 RST_IN => reset_sig, 327 CLKFX_OUT => clk_50M_sig, 328 CLK0_OUT => open, 329 LOCKED_OUT => open 330 ); 356 331 357 332 Inst_FTM_test8_rs485_interface : FTM_test8_rs485_interface … … 359 334 CLOCK_FREQUENCY => 50000000, 360 335 -- BAUD_RATE => 10000000 --simulation 361 BAUD_RATE => 25000 --implement336 BAUD_RATE => 250000 --implement 362 337 ) 363 338 port map( … … 376 351 tx_start => '0' 377 352 ); 378 379 -- enables_A <= enable_sig(0)(8 downto 0); 380 -- enables_B <= enable_sig(1)(8 downto 0); 381 -- enables_C <= enable_sig(2)(8 downto 0); 382 -- enables_D <= enable_sig(3)(8 downto 0); 383 384 353 385 354 Bus1_Rx_En <= rx_en_sig; 386 355 Bus1_Tx_En <= tx_en_sig; 387 356 Bus1_TxD_0 <= tx_sig; 388 357 rx_sig <= Bus1_RxD_0; 389 390 391 392 358 393 359 --FTM main state machine (two-process implementation) … … 405 371 case FTM_test8_State is 406 372 when INIT => 407 reset_sig <= '0'; 408 409 LED_red <= ("0000"); 410 373 reset_sig <= '0'; 374 LED_red <= "0000"; 411 375 if (rx_data_sig = "00110001" and rx_valid_sig = '1') then 412 376 FTM_test8_NextState <= RUN1; … … 422 386 when RUN1 => 423 387 reset_sig <= '0'; 424 425 -- enable_sig <= ("0000000000000000","0000000111111111","0000000111111111","0000000111111111"); 426 LED_red <= ("0001"); 427 388 LED_red <= "0001"; 428 389 if (rx_data_sig = "00110000" and rx_valid_sig = '1') then 429 390 FTM_test8_NextState <= INIT; … … 439 400 when RUN2 => 440 401 reset_sig <= '0'; 441 442 -- enable_sig <= ("0000000111111111","0000000000000000","0000000111111111","0000000111111111"); 443 LED_red <= ("0010"); 444 402 LED_red <= "0010"; 445 403 if (rx_data_sig = "00110000" and rx_valid_sig = '1') then 446 404 FTM_test8_NextState <= INIT; … … 456 414 when RUN3 => 457 415 reset_sig <= '0'; 458 459 -- enable_sig <= ("0000000111111111","0000000111111111","0000000000000000","0000000111111111"); 460 LED_red <= ("0100"); 461 416 LED_red <= "0100"; 462 417 if (rx_data_sig = "00110000" and rx_valid_sig = '1') then 463 418 FTM_test8_NextState <= INIT; … … 473 428 when RUN4 => 474 429 reset_sig <= '0'; 475 476 -- enable_sig <= ("0000000111111111","0000000111111111","0000000111111111","0000000000000000"); 477 LED_red <= ("1000"); 478 430 LED_red <= "1000"; 479 431 if (rx_data_sig = "00110000" and rx_valid_sig = '1') then 480 432 FTM_test8_NextState <= INIT; … … 491 443 end process FTM_test8_C_logic; 492 444 493 494 495 496 497 LED_ye <= ("11"); 498 LED_gn <= ("11"); 499 500 501 445 LED_ye <= "11"; 446 LED_gn <= "11"; 502 447 503 448 end Behavioral; -
firmware/FTM/test_firmware/FTM_test8/ftm_board_test8.ucf
r10046 r10058 173 173 174 174 # yellow 175 #NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0176 #NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0175 NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0 176 NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 177 177 178 178 # green 179 #NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0180 #NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0179 NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 180 NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 181 181 182 182
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