Changeset 10067

Timestamp:

12/08/10 16:14:34 (14 years ago)

Author:

weitzel

Message:

Skeleton of FTM_top and FTM_top_tb added

Location:

firmware/FTM

Files:

• FTM_top.vhd (added)
• FTM_top_tb.vhd (added)
• ftm_board.ucf (modified) (5 diffs)

firmware/FTM/ftm_board.ucf

@@ -48 +48 @@
 NET W_A<9> LOC  = V24  | IOSTANDARD=LVCMOS33; #
 
-# W5300 controll signals
+# W5300 control signals
 # the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
 # W_CS is also routed to testpoint JP7
@@ -83 +83 @@
 
 # temperature sensors
-NET SIO        LOC  = F22  | IOSTANDARD=LVCMOS33;  # serial IO
+NET SIO       LOC  = F22  | IOSTANDARD=LVCMOS33;  # serial IO
 NET TS_CS<0>  LOC  = H21  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select0
 NET TS_CS<1>  LOC  = J21  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select1
@@ -151 +151 @@
 NET ext_Trig<1>  LOC  = B1  | IOSTANDARD=LVCMOS33; #    
 NET ext_Trig<2>  LOC  = B2  | IOSTANDARD=LVCMOS33; #
-NET Veto          LOC  = E4  | IOSTANDARD=LVCMOS33; #
-NET NIM_In<0>     LOC  = D3  | IOSTANDARD=LVCMOS33; #
-NET NIM_In<1>     LOC  = F4  | IOSTANDARD=LVCMOS33; #
-NET NIM_In<2>     LOC  = E3  | IOSTANDARD=LVCMOS33; #
+NET Veto         LOC  = E4  | IOSTANDARD=LVCMOS33; #
+NET NIM_In<0>    LOC  = D3  | IOSTANDARD=LVCMOS33; #
+NET NIM_In<1>    LOC  = F4  | IOSTANDARD=LVCMOS33; #
+NET NIM_In<2>    LOC  = E3  | IOSTANDARD=LVCMOS33; #
 
 # on IO-Bank 0
-NET NIM_In3_GCLK  LOC  = K14  | IOSTANDARD=LVCMOS33; # input with global clock buffer
-                                                     # available
+# input pin with global clock buffer available
+NET NIM_In3_GCLK  LOC  = K14  | IOSTANDARD=LVCMOS33;
 
 
@@ -238 +238 @@
 NET Aux_Tx_D     LOC  = Y2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
 NET Aux_Rx_En    LOC  = W4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable 
-NET Aux_Tx_En    LOC  = V1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary
-                                                                  # Trigger-ID
+NET Aux_Tx_En    LOC  = V1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary Trigger-ID
 
 # auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
@@ -286 +285 @@
 # conversion stage
 #######################################################
-NET RES_p       LOC  = D16  | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; #  RES+   Reset
-NET RES_n       LOC  = C15  | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; #  RES-   IO-Bank 0
-
-NET TRG_p       LOC  = B15  | IOSTANDARD=LVDS_33  | DIFF_TERM="False"; #   TRG+  Trigger
-NET TRG_n      LOC  = A15  | IOSTANDARD=LVDS_33   | DIFF_TERM="False";  #   TRG- IO-Bank 0
-
-NET TIM_Run_p   LOC  = AF25 | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; #  TIM_Run+ Time Marker
-NET TIM_Run_n   LOC  = AE25 | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; #  TIM_Run-
-                                                                        #  on IO-Bank2
-NET TIM_Sel    LOC  = AD22 | IOSTANDARD=LVCMOS33;   # Time Marker selector
-                                                    # IO-Bank 2
+NET RES_p       LOC  = D16  | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset
+NET RES_n       LOC  = C15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0
+
+NET TRG_p       LOC  = B15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger
+NET TRG_n       LOC  = A15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0
+
+NET TIM_Run_p   LOC  = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker
+NET TIM_Run_n   LOC  = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- on IO-Bank2
+
+NET TIM_Sel     LOC  = AD22 | IOSTANDARD=LVCMOS33;  # Time Marker selector IO-Bank 2
+
 NET CLD_FPGA    LOC  = AA14 | IOSTANDARD=LVCMOS33;  # DRS-Clock feedback into FPGA