Changeset 10138 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Timestamp:
- 02/08/11 11:54:22 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10121 r10138 172 172 when CONFIG7 => 173 173 if (drs_srin_write_ready = '1') then 174 drs_channel_id <= DRS_ADDR_IDLE; -- to make sure not to write accidentally into DRS shift registers 174 175 roi_max_int <= roi_max; 175 176 state_generate <= WRITE_DATA_IDLE; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd
r10081 r10138 85 85 when SRIN_WRITE_END => 86 86 SRCLK_EN <= '0'; 87 srin_out <= ' 1';87 srin_out <= '0'; 88 88 srin_write_ready <= '1'; 89 89 srin_write_ack <= '0'; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10129 r10138 163 163 164 164 -- DRS Registers 165 constant DRS_ADDR_IDLE : std_logic_vector := "1001"; 165 166 constant DRS_CONFIG_REG : std_logic_vector := "1100"; 166 167 constant DRS_WRITE_SHIFT_REG : std_logic_vector := "1101"; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10137 r10138 144 144 signal local_fifo_channels : std_logic_vector (3 downto 0); 145 145 146 signal data_valid_int : std_logic := '0'; 146 147 147 148 148 … … 162 162 -- signals for synching in asynchronous input signals 163 163 ------------------------------------------------------------------------------ 164 signal w5300_interrupt_sr : std_logic_vector(1 downto 0); 164 signal w5300_interrupt_sr : std_logic_vector(1 downto 0) := "11"; 165 --?? not sure if this init value is good 166 -- but should be no problem, because interrupt_ignore is not true during the first 2 clock cycles. 167 -- I hope! 168 signal data_valid_sr : std_logic_vector(1 downto 0) := "00"; 165 169 ------------------------------------------------------------------------------ 166 170 … … 187 191 -- synch asynchronous input in: 188 192 w5300_interrupt_sr <= w5300_interrupt_sr(1) & int; 193 data_valid_sr <= data_valid_sr(1) & data_valid; 189 194 190 195 -- interrupt is handled synchronously 191 196 -- W5300 pulls low its interrpt line in case of: 192 -- ??? I don't know ... connection loss ??? 197 -- When Sockets time out and 198 -- When sockets receive disconnection request. 193 199 194 200 if (w5300_interrupt_sr = "01") and (interrupt_ignore = '0') then … … 560 566 state_init <= MAIN; 561 567 end if; 562 563 -- main "loop" 568 ----------------------------------------- 569 -- MAIN "loop" -------------------------- 570 ----------------------------------------- 571 564 572 when MAIN => 565 573 socks_waiting <= '0'; … … 573 581 data_valid_ack <= '0'; 574 582 state_init <= MAIN1; 575 data_valid_int <= data_valid;583 --data_valid_int <= data_valid; 576 584 when MAIN1 => 577 585 if (chk_recv_cntr = 1000) then … … 586 594 when MAIN2 => 587 595 busy <= '0'; 588 if (data_valid = '1') then 589 data_valid_int <= '0'; 596 --if (data_valid = '1') then 597 if (data_valid_sr = "01" or data_valid_sr = "11") then 598 --data_valid_int <= '0'; 590 599 busy <= '1'; 591 600 local_write_length <= write_length; … … 607 616 next_state <= MAIN; 608 617 state_init <= WRITE_DATA; 618 619 ----------------------------------------- 620 -- END OF MAIN ------------------ 621 ----------------------------------------- 622 609 623 610 624
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