Changeset 10138 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds
- Timestamp:
- 02/08/11 11:54:22 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd
r10129 r10138 333 333 (vvPair 334 334 variable "date" 335 value "0 4.02.2011"335 value "08.02.2011" 336 336 ) 337 337 (vvPair 338 338 variable "day" 339 value " Fr"339 value "Di" 340 340 ) 341 341 (vvPair 342 342 variable "day_long" 343 value " Freitag"343 value "Dienstag" 344 344 ) 345 345 (vvPair 346 346 variable "dd" 347 value "0 4"347 value "08" 348 348 ) 349 349 (vvPair … … 485 485 (vvPair 486 486 variable "time" 487 value "1 2:56:44"487 value "11:06:22" 488 488 ) 489 489 (vvPair … … 577 577 ) 578 578 xt "-172000,106800,-128500,107600" 579 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\"" 579 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\" 580 " 580 581 ) 581 582 ) … … 595 596 ) 596 597 xt "-172000,42800,-132000,43600" 597 st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" 598 st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) 599 " 598 600 ) 599 601 ) … … 613 615 ) 614 616 xt "-172000,62000,-139500,62800" 615 st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0)" 617 st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0) 618 " 616 619 ) 617 620 ) … … 631 634 ) 632 635 xt "-172000,80400,-132000,81200" 633 st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)" 636 st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) 637 " 634 638 ) 635 639 ) … … 649 653 ) 650 654 xt "-172000,81200,-139500,82000" 651 st "SIGNAL ram_data : std_logic_vector(15 downto 0)" 655 st "SIGNAL ram_data : std_logic_vector(15 downto 0) 656 " 652 657 ) 653 658 ) … … 667 672 ) 668 673 xt "-172000,34400,-132000,35200" 669 st "wiz_reset : std_logic := '1'" 674 st "wiz_reset : std_logic := '1' 675 " 670 676 ) 671 677 ) … … 685 691 ) 686 692 xt "-172000,32000,-143500,32800" 687 st "wiz_addr : std_logic_vector(9 DOWNTO 0)" 693 st "wiz_addr : std_logic_vector(9 DOWNTO 0) 694 " 688 695 ) 689 696 ) … … 703 710 ) 704 711 xt "-172000,36800,-143000,37600" 705 st "wiz_data : std_logic_vector(15 DOWNTO 0)" 712 st "wiz_data : std_logic_vector(15 DOWNTO 0) 713 " 706 714 ) 707 715 ) … … 721 729 ) 722 730 xt "-172000,32800,-132000,33600" 723 st "wiz_cs : std_logic := '1'" 731 st "wiz_cs : std_logic := '1' 732 " 724 733 ) 725 734 ) … … 739 748 ) 740 749 xt "-172000,35200,-132000,36000" 741 st "wiz_wr : std_logic := '1'" 750 st "wiz_wr : std_logic := '1' 751 " 742 752 ) 743 753 ) … … 757 767 ) 758 768 xt "-172000,33600,-132000,34400" 759 st "wiz_rd : std_logic := '1'" 769 st "wiz_rd : std_logic := '1' 770 " 760 771 ) 761 772 ) … … 774 785 ) 775 786 xt "-172000,13600,-153500,14400" 776 st "wiz_int : std_logic" 787 st "wiz_int : std_logic 788 " 777 789 ) 778 790 ) … … 1291 1303 fg "0,65535,0" 1292 1304 ) 1293 xt "0, 65625,750,66375"1305 xt "0,70625,750,71375" 1294 1306 ) 1295 1307 tg (CPTG … … 1301 1313 va (VaSet 1302 1314 ) 1303 xt "-17300, 65500,-1000,66500"1315 xt "-17300,70500,-1000,71500" 1304 1316 st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)" 1305 1317 ju 2 1306 blo "-1000, 66300"1318 blo "-1000,71300" 1307 1319 ) 1308 1320 ) … … 1366 1378 fg "0,65535,0" 1367 1379 ) 1368 xt "-21750, 70625,-21000,71375"1380 xt "-21750,69625,-21000,70375" 1369 1381 ) 1370 1382 tg (CPTG … … 1376 1388 va (VaSet 1377 1389 ) 1378 xt "-20000, 70500,-13200,71500"1390 xt "-20000,69500,-13200,70500" 1379 1391 st "trigger_id : (47:0)" 1380 blo "-20000,7 1300"1392 blo "-20000,70300" 1381 1393 ) 1382 1394 ) … … 1474 1486 fg "0,65535,0" 1475 1487 ) 1476 xt "0, 66625,750,67375"1488 xt "0,71625,750,72375" 1477 1489 ) 1478 1490 tg (CPTG … … 1484 1496 va (VaSet 1485 1497 ) 1486 xt "-6300, 66500,-1000,67500"1498 xt "-6300,71500,-1000,72500" 1487 1499 st "ram_write_ea" 1488 1500 ju 2 1489 blo "-1000, 67300"1501 blo "-1000,72300" 1490 1502 ) 1491 1503 ) … … 1509 1521 fg "0,65535,0" 1510 1522 ) 1511 xt "0, 67625,750,68375"1523 xt "0,72625,750,73375" 1512 1524 ) 1513 1525 tg (CPTG … … 1519 1531 va (VaSet 1520 1532 ) 1521 xt "-7300, 67500,-1000,68500"1533 xt "-7300,72500,-1000,73500" 1522 1534 st "ram_write_ready" 1523 1535 ju 2 1524 blo "-1000, 68300"1536 blo "-1000,73300" 1525 1537 ) 1526 1538 ) … … 1547 1559 fg "0,65535,0" 1548 1560 ) 1549 xt "0,7 6625,750,77375"1561 xt "0,78625,750,79375" 1550 1562 ) 1551 1563 tg (CPTG … … 1557 1569 va (VaSet 1558 1570 ) 1559 xt "-4000,7 6500,-1000,77500"1571 xt "-4000,78500,-1000,79500" 1560 1572 st "roi_max" 1561 1573 ju 2 1562 blo "-1000,7 7300"1574 blo "-1000,79300" 1563 1575 ) 1564 1576 ) … … 1617 1629 fg "0,65535,0" 1618 1630 ) 1619 xt "0,7 7625,750,78375"1631 xt "0,79625,750,80375" 1620 1632 ) 1621 1633 tg (CPTG … … 1627 1639 va (VaSet 1628 1640 ) 1629 xt "-10100,7 7500,-1000,78500"1641 xt "-10100,79500,-1000,80500" 1630 1642 st "package_length : (15:0)" 1631 1643 ju 2 1632 blo "-1000, 78300"1644 blo "-1000,80300" 1633 1645 ) 1634 1646 ) … … 2016 2028 fg "0,65535,0" 2017 2029 ) 2018 xt "0,7 4625,750,75375"2030 xt "0,77625,750,78375" 2019 2031 ) 2020 2032 tg (CPTG … … 2026 2038 va (VaSet 2027 2039 ) 2028 xt "-7700,7 4500,-1000,75500"2040 xt "-7700,77500,-1000,78500" 2029 2041 st "config_ready_mm" 2030 2042 ju 2 2031 blo "-1000,7 5300"2043 blo "-1000,78300" 2032 2044 ) 2033 2045 ) … … 2156 2168 fg "0,65535,0" 2157 2169 ) 2158 xt "0,7 2625,750,73375"2170 xt "0,75625,750,76375" 2159 2171 ) 2160 2172 tg (CPTG … … 2166 2178 va (VaSet 2167 2179 ) 2168 xt "-7400,7 2500,-1000,73500"2180 xt "-7400,75500,-1000,76500" 2169 2181 st "config_start_mm" 2170 2182 ju 2 2171 blo "-1000,7 3300"2183 blo "-1000,76300" 2172 2184 ) 2173 2185 ) … … 2344 2356 fg "0,65535,0" 2345 2357 ) 2346 xt "0,7 3625,750,74375"2358 xt "0,76625,750,77375" 2347 2359 ) 2348 2360 tg (CPTG … … 2354 2366 va (VaSet 2355 2367 ) 2356 xt "-8200,7 3500,-1000,74500"2368 xt "-8200,76500,-1000,77500" 2357 2369 st "config_started_mm" 2358 2370 ju 2 2359 blo "-1000,7 4300"2371 blo "-1000,77300" 2360 2372 ) 2361 2373 ) … … 2626 2638 fg "0,65535,0" 2627 2639 ) 2628 xt "0, 68625,750,69375"2640 xt "0,73625,750,74375" 2629 2641 ) 2630 2642 tg (CPTG … … 2636 2648 va (VaSet 2637 2649 ) 2638 xt "-8800, 68500,-1000,69500"2650 xt "-8800,73500,-1000,74500" 2639 2651 st "ram_write_ready_ack" 2640 2652 ju 2 2641 blo "-1000, 69300"2653 blo "-1000,74300" 2642 2654 ) 2643 2655 ) … … 2870 2882 ) 2871 2883 xt "-172000,9600,-143500,10400" 2872 st "board_id : std_logic_vector(3 DOWNTO 0)" 2884 st "board_id : std_logic_vector(3 DOWNTO 0) 2885 " 2873 2886 ) 2874 2887 ) … … 2889 2902 ) 2890 2903 xt "-172000,12800,-153500,13600" 2891 st "trigger : std_logic" 2904 st "trigger : std_logic 2905 " 2892 2906 ) 2893 2907 ) … … 3257 3271 fg "0,65535,0" 3258 3272 ) 3259 xt "87250,7 1625,88000,72375"3273 xt "87250,72625,88000,73375" 3260 3274 ) 3261 3275 tg (CPTG … … 3267 3281 va (VaSet 3268 3282 ) 3269 xt "89000,7 1500,96900,72500"3283 xt "89000,72500,96900,73500" 3270 3284 st "write_length : (16:0)" 3271 blo "89000,7 2300"3285 blo "89000,73300" 3272 3286 ) 3273 3287 ) … … 3294 3308 fg "0,65535,0" 3295 3309 ) 3296 xt "87250,7 2625,88000,73375"3310 xt "87250,73625,88000,74375" 3297 3311 ) 3298 3312 tg (CPTG … … 3304 3318 va (VaSet 3305 3319 ) 3306 xt "89000,7 2500,105300,73500"3320 xt "89000,73500,105300,74500" 3307 3321 st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)" 3308 blo "89000,7 3300"3322 blo "89000,74300" 3309 3323 ) 3310 3324 ) … … 3406 3420 fg "0,65535,0" 3407 3421 ) 3408 xt "87250,7 0625,88000,71375"3422 xt "87250,71625,88000,72375" 3409 3423 ) 3410 3424 tg (CPTG … … 3416 3430 va (VaSet 3417 3431 ) 3418 xt "89000,7 0500,93100,71500"3432 xt "89000,71500,93100,72500" 3419 3433 st "data_valid" 3420 blo "89000,7 1300"3434 blo "89000,72300" 3421 3435 ) 3422 3436 ) … … 3442 3456 fg "0,65535,0" 3443 3457 ) 3444 xt "87250, 69625,88000,70375"3458 xt "87250,70625,88000,71375" 3445 3459 ) 3446 3460 tg (CPTG … … 3452 3466 va (VaSet 3453 3467 ) 3454 xt "89000, 69500,90900,70500"3468 xt "89000,70500,90900,71500" 3455 3469 st "busy" 3456 blo "89000,7 0300"3470 blo "89000,71300" 3457 3471 ) 3458 3472 ) … … 3480 3494 fg "0,65535,0" 3481 3495 ) 3482 xt "87250,7 3625,88000,74375"3496 xt "87250,74625,88000,75375" 3483 3497 ) 3484 3498 tg (CPTG … … 3490 3504 va (VaSet 3491 3505 ) 3492 xt "89000,7 3500,96800,74500"3506 xt "89000,74500,96800,75500" 3493 3507 st "fifo_channels : (3:0)" 3494 blo "89000,7 4300"3508 blo "89000,75300" 3495 3509 ) 3496 3510 ) … … 3516 3530 fg "0,65535,0" 3517 3531 ) 3518 xt "87250,7 4625,88000,75375"3532 xt "87250,75625,88000,76375" 3519 3533 ) 3520 3534 tg (CPTG … … 3526 3540 va (VaSet 3527 3541 ) 3528 xt "89000,7 4500,94700,75500"3542 xt "89000,75500,94700,76500" 3529 3543 st "write_end_flag" 3530 blo "89000,7 5300"3544 blo "89000,76300" 3531 3545 ) 3532 3546 ) … … 3550 3564 fg "0,65535,0" 3551 3565 ) 3552 xt "87250,7 5625,88000,76375"3566 xt "87250,76625,88000,77375" 3553 3567 ) 3554 3568 tg (CPTG … … 3560 3574 va (VaSet 3561 3575 ) 3562 xt "89000,7 5500,95800,76500"3576 xt "89000,76500,95800,77500" 3563 3577 st "write_header_flag" 3564 blo "89000,7 6300"3578 blo "89000,77300" 3565 3579 ) 3566 3580 ) … … 3994 4008 fg "0,65535,0" 3995 4009 ) 3996 xt "87250,7 6625,88000,77375"4010 xt "87250,77625,88000,78375" 3997 4011 ) 3998 4012 tg (CPTG … … 4004 4018 va (VaSet 4005 4019 ) 4006 xt "89000,7 6500,94600,77500"4020 xt "89000,77500,94600,78500" 4007 4021 st "data_valid_ack" 4008 blo "89000,7 7300"4022 blo "89000,78300" 4009 4023 ) 4010 4024 ) … … 4687 4701 ) 4688 4702 xt "-172000,10400,-143500,11200" 4689 st "crate_id : std_logic_vector(1 DOWNTO 0)" 4703 st "crate_id : std_logic_vector(1 DOWNTO 0) 4704 " 4690 4705 ) 4691 4706 ) … … 4703 4718 fg "0,65535,0" 4704 4719 ) 4705 xt "-41000,6 7625,-40250,68375"4720 xt "-41000,68625,-40250,69375" 4706 4721 ) 4707 4722 tg (CPTG … … 4713 4728 va (VaSet 4714 4729 ) 4715 xt "-48800,6 7500,-42000,68500"4730 xt "-48800,68500,-42000,69500" 4716 4731 st "trigger_id : (47:0)" 4717 4732 ju 2 4718 blo "-42000,6 8300"4733 blo "-42000,69300" 4719 4734 ) 4720 4735 ) … … 4743 4758 fg "0,65535,0" 4744 4759 ) 4745 xt "-52750,6 7625,-52000,68375"4760 xt "-52750,68625,-52000,69375" 4746 4761 ) 4747 4762 tg (CPTG … … 4753 4768 va (VaSet 4754 4769 ) 4755 xt "-51000,6 7500,-48200,68500"4770 xt "-51000,68500,-48200,69500" 4756 4771 st "trigger" 4757 blo "-51000,6 8300"4772 blo "-51000,69300" 4758 4773 ) 4759 4774 ) … … 4780 4795 fg "0,65535,0" 4781 4796 ) 4782 xt "-52750,6 6625,-52000,67375"4797 xt "-52750,67625,-52000,68375" 4783 4798 ) 4784 4799 tg (CPTG … … 4790 4805 va (VaSet 4791 4806 ) 4792 xt "-51000,6 6500,-49700,67500"4807 xt "-51000,67500,-49700,68500" 4793 4808 st "clk" 4794 blo "-51000,6 7300"4809 blo "-51000,68300" 4795 4810 ) 4796 4811 ) … … 4814 4829 lineWidth 2 4815 4830 ) 4816 xt "-52000,6 6000,-41000,70000"4831 xt "-52000,67000,-41000,71000" 4817 4832 ) 4818 4833 oxt "32000,2000,43000,12000" … … 4828 4843 font "Arial,8,1" 4829 4844 ) 4830 xt "-50300,7 0000,-43700,71000"4845 xt "-50300,71000,-43700,72000" 4831 4846 st "FACT_FAD_LIB" 4832 blo "-50300,7 0800"4847 blo "-50300,71800" 4833 4848 tm "BdLibraryNameMgr" 4834 4849 ) … … 4839 4854 font "Arial,8,1" 4840 4855 ) 4841 xt "-50300,7 1000,-43700,72000"4856 xt "-50300,72000,-43700,73000" 4842 4857 st "trigger_counter" 4843 blo "-50300,7 1800"4858 blo "-50300,72800" 4844 4859 tm "CptNameMgr" 4845 4860 ) … … 4850 4865 font "Arial,8,1" 4851 4866 ) 4852 xt "-50300,7 1000,-42700,72000"4867 xt "-50300,72000,-42700,73000" 4853 4868 st "I_main_ext_trigger" 4854 blo "-50300,7 1800"4869 blo "-50300,72800" 4855 4870 tm "InstanceNameMgr" 4856 4871 ) … … 4867 4882 font "Courier New,8,0" 4868 4883 ) 4869 xt "-52000,6 5000,-52000,65000"4884 xt "-52000,66000,-52000,66000" 4870 4885 ) 4871 4886 header "" … … 4881 4896 fg "49152,49152,49152" 4882 4897 ) 4883 xt "-51750,6 8250,-50250,69750"4898 xt "-51750,69250,-50250,70750" 4884 4899 iconName "VhdlFileViewIcon.png" 4885 4900 iconMaskName "VhdlFileViewIcon.msk" … … 4911 4926 ) 4912 4927 xt "-172000,98800,-139500,99600" 4913 st "SIGNAL trigger_id : std_logic_vector(47 downto 0)" 4928 st "SIGNAL trigger_id : std_logic_vector(47 downto 0) 4929 " 4914 4930 ) 4915 4931 ) … … 4931 4947 ) 4932 4948 xt "-172000,82000,-132000,82800" 4933 st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" 4949 st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) 4950 " 4934 4951 ) 4935 4952 ) … … 4947 4964 fg "0,65535,0" 4948 4965 ) 4949 xt " 31250,72625,32000,73375"4966 xt "27250,70625,28000,71375" 4950 4967 ) 4951 4968 tg (CPTG … … 4958 4975 font "arial,8,0" 4959 4976 ) 4960 xt " 33000,72500,51400,73500"4977 xt "29000,70500,47400,71500" 4961 4978 st "ram_start_addr : (RAM_ADDR_WIDTH_64B-1:0)" 4962 blo " 33000,73300"4979 blo "29000,71300" 4963 4980 ) 4964 4981 ) … … 4983 5000 shape (Triangle 4984 5001 uid 2352,0 4985 ro 905002 ro 180 4986 5003 va (VaSet 4987 5004 vasetType 1 4988 5005 fg "0,65535,0" 4989 5006 ) 4990 xt " 31250,70625,32000,71375"5007 xt "28625,67250,29375,68000" 4991 5008 ) 4992 5009 tg (CPTG 4993 5010 uid 2353,0 4994 5011 ps "CptPortTextPlaceStrategy" 4995 stg " VerticalLayoutStrategy"5012 stg "RightVerticalLayoutStrategy" 4996 5013 f (Text 4997 5014 uid 2354,0 5015 ro 270 4998 5016 va (VaSet 4999 5017 font "arial,8,0" 5000 5018 ) 5001 xt " 33000,70500,34300,71500"5019 xt "28500,69000,29500,70300" 5002 5020 st "clk" 5003 blo "33000,71300" 5021 ju 2 5022 blo "29300,69000" 5004 5023 ) 5005 5024 ) … … 5024 5043 fg "0,65535,0" 5025 5044 ) 5026 xt " 31250,79625,32000,80375"5045 xt "27250,77625,28000,78375" 5027 5046 ) 5028 5047 tg (CPTG … … 5035 5054 font "arial,8,0" 5036 5055 ) 5037 xt " 33000,79500,38100,80500"5056 xt "29000,77500,34100,78500" 5038 5057 st "config_ready" 5039 blo " 33000,80300"5058 blo "29000,78300" 5040 5059 ) 5041 5060 ) … … 5062 5081 fg "0,65535,0" 5063 5082 ) 5064 xt " 31250,77625,32000,78375"5083 xt "27250,75625,28000,76375" 5065 5084 ) 5066 5085 tg (CPTG … … 5073 5092 font "arial,8,0" 5074 5093 ) 5075 xt " 33000,77500,37800,78500"5094 xt "29000,75500,33800,76500" 5076 5095 st "config_start" 5077 blo " 33000,78300"5096 blo "29000,76300" 5078 5097 ) 5079 5098 ) … … 5098 5117 fg "0,65535,0" 5099 5118 ) 5100 xt " 31250,73625,32000,74375"5119 xt "27250,71625,28000,72375" 5101 5120 ) 5102 5121 tg (CPTG … … 5109 5128 font "arial,8,0" 5110 5129 ) 5111 xt " 33000,73500,38300,74500"5130 xt "29000,71500,34300,72500" 5112 5131 st "ram_write_ea" 5113 blo " 33000,74300"5132 blo "29000,72300" 5114 5133 ) 5115 5134 ) … … 5136 5155 fg "0,65535,0" 5137 5156 ) 5138 xt " 31250,74625,32000,75375"5157 xt "27250,72625,28000,73375" 5139 5158 ) 5140 5159 tg (CPTG … … 5147 5166 font "arial,8,0" 5148 5167 ) 5149 xt " 33000,74500,39300,75500"5168 xt "29000,72500,35300,73500" 5150 5169 st "ram_write_ready" 5151 blo " 33000,75300"5170 blo "29000,73300" 5152 5171 ) 5153 5172 ) … … 5173 5192 fg "0,65535,0" 5174 5193 ) 5175 xt " 31250,80625,32000,81375"5194 xt "27250,78625,28000,79375" 5176 5195 ) 5177 5196 tg (CPTG … … 5184 5203 font "arial,8,0" 5185 5204 ) 5186 xt " 33000,80500,36000,81500"5205 xt "29000,78500,32000,79500" 5187 5206 st "roi_max" 5188 blo " 33000,81300"5207 blo "29000,79300" 5189 5208 ) 5190 5209 ) … … 5212 5231 fg "0,65535,0" 5213 5232 ) 5214 xt " 63000,70625,63750,71375"5233 xt "59000,70625,59750,71375" 5215 5234 ) 5216 5235 tg (CPTG … … 5223 5242 font "arial,8,0" 5224 5243 ) 5225 xt "5 8600,70500,62000,71500"5244 xt "54600,70500,58000,71500" 5226 5245 st "wiz_busy" 5227 5246 ju 2 5228 blo " 62000,71300"5247 blo "58000,71300" 5229 5248 ) 5230 5249 ) … … 5249 5268 fg "0,65535,0" 5250 5269 ) 5251 xt " 63000,74625,63750,75375"5270 xt "59000,74625,59750,75375" 5252 5271 ) 5253 5272 tg (CPTG … … 5260 5279 font "arial,8,0" 5261 5280 ) 5262 xt " 50200,74500,62000,75500"5281 xt "46200,74500,58000,75500" 5263 5282 st "wiz_number_of_channels : (3:0)" 5264 5283 ju 2 5265 blo " 62000,75300"5284 blo "58000,75300" 5266 5285 ) 5267 5286 ) … … 5289 5308 fg "0,65535,0" 5290 5309 ) 5291 xt " 63000,73625,63750,74375"5310 xt "59000,73625,59750,74375" 5292 5311 ) 5293 5312 tg (CPTG … … 5300 5319 font "arial,8,0" 5301 5320 ) 5302 xt " 42100,73500,62000,74500"5321 xt "38100,73500,58000,74500" 5303 5322 st "wiz_ram_start_addr : (RAM_ADDR_WIDTH_16B-1:0)" 5304 5323 ju 2 5305 blo " 62000,74300"5324 blo "58000,74300" 5306 5325 ) 5307 5326 ) … … 5330 5349 fg "0,65535,0" 5331 5350 ) 5332 xt " 63000,71625,63750,72375"5351 xt "59000,71625,59750,72375" 5333 5352 ) 5334 5353 tg (CPTG … … 5341 5360 font "arial,8,0" 5342 5361 ) 5343 xt "5 6900,71500,62000,72500"5362 xt "52900,71500,58000,72500" 5344 5363 st "wiz_write_ea" 5345 5364 ju 2 5346 blo " 62000,72300"5365 blo "58000,72300" 5347 5366 ) 5348 5367 ) … … 5369 5388 fg "0,65535,0" 5370 5389 ) 5371 xt " 63000,75625,63750,76375"5390 xt "59000,75625,59750,76375" 5372 5391 ) 5373 5392 tg (CPTG … … 5380 5399 font "arial,8,0" 5381 5400 ) 5382 xt "5 6500,75500,62000,76500"5401 xt "52500,75500,58000,76500" 5383 5402 st "wiz_write_end" 5384 5403 ju 2 5385 blo " 62000,76300"5404 blo "58000,76300" 5386 5405 ) 5387 5406 ) … … 5408 5427 fg "0,65535,0" 5409 5428 ) 5410 xt " 63000,76625,63750,77375"5429 xt "59000,76625,59750,77375" 5411 5430 ) 5412 5431 tg (CPTG … … 5419 5438 font "arial,8,0" 5420 5439 ) 5421 xt "5 5400,76500,62000,77500"5440 xt "51400,76500,58000,77500" 5422 5441 st "wiz_write_header" 5423 5442 ju 2 5424 blo " 62000,77300"5443 blo "58000,77300" 5425 5444 ) 5426 5445 ) … … 5447 5466 fg "0,65535,0" 5448 5467 ) 5449 xt " 63000,72625,63750,73375"5468 xt "59000,72625,59750,73375" 5450 5469 ) 5451 5470 tg (CPTG … … 5458 5477 font "arial,8,0" 5459 5478 ) 5460 xt " 52600,72500,62000,73500"5479 xt "48600,72500,58000,73500" 5461 5480 st "wiz_write_length : (16:0)" 5462 5481 ju 2 5463 blo " 62000,73300"5482 blo "58000,73300" 5464 5483 ) 5465 5484 ) … … 5487 5506 fg "0,65535,0" 5488 5507 ) 5489 xt " 31250,87625,32000,88375"5508 xt "27250,85625,28000,86375" 5490 5509 ) 5491 5510 tg (CPTG … … 5498 5517 font "arial,8,0" 5499 5518 ) 5500 xt " 33000,87500,36400,88500"5519 xt "29000,85500,32400,86500" 5501 5520 st "roi_array" 5502 blo " 33000,88300"5521 blo "29000,86300" 5503 5522 ) 5504 5523 ) … … 5525 5544 fg "0,65535,0" 5526 5545 ) 5527 xt " 31250,81625,32000,82375"5546 xt "27250,79625,28000,80375" 5528 5547 ) 5529 5548 tg (CPTG … … 5536 5555 font "arial,8,0" 5537 5556 ) 5538 xt " 33000,81500,42100,82500"5557 xt "29000,79500,38100,80500" 5539 5558 st "package_length : (15:0)" 5540 blo " 33000,82300"5559 blo "29000,80300" 5541 5560 ) 5542 5561 ) … … 5564 5583 fg "0,65535,0" 5565 5584 ) 5566 xt " 31250,78625,32000,79375"5585 xt "27250,76625,28000,77375" 5567 5586 ) 5568 5587 tg (CPTG … … 5575 5594 font "arial,8,0" 5576 5595 ) 5577 xt " 33000,78500,38600,79500"5596 xt "29000,76500,34600,77500" 5578 5597 st "config_started" 5579 blo " 33000,79300"5598 blo "29000,77300" 5580 5599 ) 5581 5600 ) … … 5602 5621 fg "0,65535,0" 5603 5622 ) 5604 xt " 63000,77625,63750,78375"5623 xt "59000,77625,59750,78375" 5605 5624 ) 5606 5625 tg (CPTG … … 5613 5632 font "arial,8,0" 5614 5633 ) 5615 xt "5 9000,77500,62000,78500"5634 xt "55000,77500,58000,78500" 5616 5635 st "wiz_ack" 5617 5636 ju 2 5618 blo " 62000,78300"5637 blo "58000,78300" 5619 5638 ) 5620 5639 ) … … 5639 5658 fg "0,65535,0" 5640 5659 ) 5641 xt " 31250,75625,32000,76375"5660 xt "27250,73625,28000,74375" 5642 5661 ) 5643 5662 tg (CPTG … … 5650 5669 font "arial,8,0" 5651 5670 ) 5652 xt " 33000,75500,40800,76500"5671 xt "29000,73500,36800,74500" 5653 5672 st "ram_write_ready_ack" 5654 blo " 33000,76300"5673 blo "29000,74300" 5655 5674 ) 5656 5675 ) … … 5679 5698 lineWidth 2 5680 5699 ) 5681 xt " 32000,70000,63000,90000"5700 xt "28000,68000,59000,88000" 5682 5701 ) 5683 5702 oxt "15000,6000,23000,16000" … … 5692 5711 font "arial,8,1" 5693 5712 ) 5694 xt " 32350,90000,38550,91000"5713 xt "28350,88000,34550,89000" 5695 5714 st "FACT_FAD_lib" 5696 blo " 32350,90800"5715 blo "28350,88800" 5697 5716 tm "BdLibraryNameMgr" 5698 5717 ) … … 5702 5721 font "arial,8,1" 5703 5722 ) 5704 xt " 32350,91000,39650,92000"5723 xt "28350,89000,35650,90000" 5705 5724 st "memory_manager" 5706 blo " 32350,91800"5725 blo "28350,89800" 5707 5726 tm "CptNameMgr" 5708 5727 ) … … 5712 5731 font "arial,8,1" 5713 5732 ) 5714 xt " 32350,92000,42850,93000"5733 xt "28350,90000,38850,91000" 5715 5734 st "I_main_memory_manager" 5716 blo " 32350,92800"5735 blo "28350,90800" 5717 5736 tm "InstanceNameMgr" 5718 5737 ) … … 5729 5748 font "Courier New,8,0" 5730 5749 ) 5731 xt "3 2000,68400,61500,70000"5750 xt "31000,66400,60500,68000" 5732 5751 st "RAM_ADDR_WIDTH_64B = RAMADDRWIDTH64b ( integer ) 5733 5752 RAM_ADDR_WIDTH_16B = RAMADDRWIDTH64b+2 ( integer ) " … … 5755 5774 fg "49152,49152,49152" 5756 5775 ) 5757 xt " 32250,88250,33750,89750"5776 xt "28250,86250,29750,87750" 5758 5777 iconName "VhdlFileViewIcon.png" 5759 5778 iconMaskName "VhdlFileViewIcon.msk" … … 5781 5800 ) 5782 5801 xt "-172000,101200,-149500,102000" 5783 st "SIGNAL wiz_busy : std_logic" 5802 st "SIGNAL wiz_busy : std_logic 5803 " 5784 5804 ) 5785 5805 ) … … 5800 5820 ) 5801 5821 xt "-172000,103600,-128500,104400" 5802 st "SIGNAL wiz_write_ea : std_logic := '0'" 5822 st "SIGNAL wiz_write_ea : std_logic := '0' 5823 " 5803 5824 ) 5804 5825 ) … … 5820 5841 ) 5821 5842 xt "-172000,106000,-122500,106800" 5822 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0')" 5843 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0') 5844 " 5823 5845 ) 5824 5846 ) … … 5841 5863 ) 5842 5864 xt "-172000,102800,-122500,103600" 5843 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')" 5865 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0') 5866 " 5844 5867 ) 5845 5868 ) … … 5861 5884 ) 5862 5885 xt "-172000,102000,-122500,102800" 5863 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0')" 5886 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0') 5887 " 5864 5888 ) 5865 5889 ) … … 5880 5904 ) 5881 5905 xt "-172000,104400,-128500,105200" 5882 st "SIGNAL wiz_write_end : std_logic := '0'" 5906 st "SIGNAL wiz_write_end : std_logic := '0' 5907 " 5883 5908 ) 5884 5909 ) … … 5899 5924 ) 5900 5925 xt "-172000,105200,-128500,106000" 5901 st "SIGNAL wiz_write_header : std_logic := '0'" 5926 st "SIGNAL wiz_write_header : std_logic := '0' 5927 " 5902 5928 ) 5903 5929 ) … … 5916 5942 ) 5917 5943 xt "-172000,82800,-149500,83600" 5918 st "SIGNAL ram_write_ea : std_logic" 5944 st "SIGNAL ram_write_ea : std_logic 5945 " 5919 5946 ) 5920 5947 ) … … 5934 5961 ) 5935 5962 xt "-172000,83600,-128500,84400" 5936 st "SIGNAL ram_write_ready : std_logic := '0'" 5963 st "SIGNAL ram_write_ready : std_logic := '0' 5964 " 5937 5965 ) 5938 5966 ) … … 5952 5980 ) 5953 5981 xt "-172000,54800,-128500,55600" 5954 st "SIGNAL config_start : std_logic := '0'" 5982 st "SIGNAL config_start : std_logic := '0' 5983 " 5955 5984 ) 5956 5985 ) … … 5969 5998 ) 5970 5999 xt "-172000,49200,-149500,50000" 5971 st "SIGNAL config_ready : std_logic" 6000 st "SIGNAL config_ready : std_logic 6001 " 5972 6002 ) 5973 6003 ) … … 5986 6016 ) 5987 6017 xt "-172000,86800,-148000,87600" 5988 st "SIGNAL roi_max : roi_max_type" 6018 st "SIGNAL roi_max : roi_max_type 6019 " 5989 6020 ) 5990 6021 ) … … 6004 6035 ) 6005 6036 xt "-172000,77200,-139500,78000" 6006 st "SIGNAL package_length : std_logic_vector(15 downto 0)" 6037 st "SIGNAL package_length : std_logic_vector(15 downto 0) 6038 " 6007 6039 ) 6008 6040 ) … … 6022 6054 ) 6023 6055 xt "-172000,19200,-132000,20000" 6024 st "adc_oeb : std_logic := '1'" 6056 st "adc_oeb : std_logic := '1' 6057 " 6025 6058 ) 6026 6059 ) … … 6129 6162 ) 6130 6163 xt "-172000,86000,-147000,86800" 6131 st "SIGNAL roi_array : roi_array_type" 6164 st "SIGNAL roi_array : roi_array_type 6165 " 6132 6166 ) 6133 6167 ) … … 6562 6596 ) 6563 6597 xt "-172000,14400,-153500,15200" 6564 st "CLK_25_PS : std_logic" 6598 st "CLK_25_PS : std_logic 6599 " 6565 6600 ) 6566 6601 ) … … 6624 6659 ) 6625 6660 xt "-172000,15200,-153500,16000" 6626 st "CLK_50 : std_logic" 6661 st "CLK_50 : std_logic 6662 " 6627 6663 ) 6628 6664 ) … … 6641 6677 ) 6642 6678 xt "-172000,39600,-149500,40400" 6643 st "SIGNAL CLK_25 : std_logic" 6679 st "SIGNAL CLK_25 : std_logic 6680 " 6644 6681 ) 6645 6682 ) … … 6703 6740 ) 6704 6741 xt "-172000,3200,-153500,4000" 6705 st "CLK : std_logic" 6742 st "CLK : std_logic 6743 " 6706 6744 ) 6707 6745 ) … … 6721 6759 ) 6722 6760 xt "-172000,8800,-143500,9600" 6723 st "adc_otr_array : std_logic_vector(3 DOWNTO 0)" 6761 st "adc_otr_array : std_logic_vector(3 DOWNTO 0) 6762 " 6724 6763 ) 6725 6764 ) … … 6738 6777 ) 6739 6778 xt "-172000,8000,-148000,8800" 6740 st "adc_data_array : adc_data_array_type" 6779 st "adc_data_array : adc_data_array_type 6780 " 6741 6781 ) 6742 6782 ) … … 6801 6841 ) 6802 6842 xt "-172000,66800,-128500,67600" 6803 st "SIGNAL drs_clk_en : std_logic := '0'" 6843 st "SIGNAL drs_clk_en : std_logic := '0' 6844 " 6804 6845 ) 6805 6846 ) … … 6818 6859 ) 6819 6860 xt "-172000,73200,-143500,74000" 6820 st "SIGNAL drs_s_cell_array : drs_s_cell_array_type" 6861 st "SIGNAL drs_s_cell_array : drs_s_cell_array_type 6862 " 6821 6863 ) 6822 6864 ) … … 6836 6878 ) 6837 6879 xt "-172000,67600,-128500,68400" 6838 st "SIGNAL drs_read_s_cell : std_logic := '0'" 6880 st "SIGNAL drs_read_s_cell : std_logic := '0' 6881 " 6839 6882 ) 6840 6883 ) … … 6855 6898 ) 6856 6899 xt "-172000,25600,-126000,26400" 6857 st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 6900 st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 6901 " 6858 6902 ) 6859 6903 ) … … 6873 6917 ) 6874 6918 xt "-172000,26400,-132000,27200" 6875 st "drs_dwrite : std_logic := '1'" 6919 st "drs_dwrite : std_logic := '1' 6920 " 6876 6921 ) 6877 6922 ) … … 6980 7025 ) 6981 7026 xt "-172000,4800,-153500,5600" 6982 st "SROUT_in_0 : std_logic" 7027 st "SROUT_in_0 : std_logic 7028 " 6983 7029 ) 6984 7030 ) … … 6997 7043 ) 6998 7044 xt "-172000,5600,-153500,6400" 6999 st "SROUT_in_1 : std_logic" 7045 st "SROUT_in_1 : std_logic 7046 " 7000 7047 ) 7001 7048 ) … … 7014 7061 ) 7015 7062 xt "-172000,6400,-153500,7200" 7016 st "SROUT_in_2 : std_logic" 7063 st "SROUT_in_2 : std_logic 7064 " 7017 7065 ) 7018 7066 ) … … 7031 7079 ) 7032 7080 xt "-172000,7200,-153500,8000" 7033 st "SROUT_in_3 : std_logic" 7081 st "SROUT_in_3 : std_logic 7082 " 7034 7083 ) 7035 7084 ) … … 7228 7277 ) 7229 7278 xt "-172000,68400,-149500,69200" 7230 st "SIGNAL drs_read_s_cell_ready : std_logic" 7279 st "SIGNAL drs_read_s_cell_ready : std_logic 7280 " 7231 7281 ) 7232 7282 ) … … 7883 7933 ) 7884 7934 xt "-172000,16000,-132000,16800" 7885 st "RSRLOAD : std_logic := '0'" 7935 st "RSRLOAD : std_logic := '0' 7936 " 7886 7937 ) 7887 7938 ) … … 7946 7997 ) 7947 7998 xt "-172000,16800,-132000,17600" 7948 st "SRCLK : std_logic := '0'" 7999 st "SRCLK : std_logic := '0' 8000 " 7949 8001 ) 7950 8002 ) … … 8599 8651 ) 8600 8652 xt "-172000,45200,-140000,46000" 8601 st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0)" 8653 st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0) 8654 " 8602 8655 ) 8603 8656 ) … … 8616 8669 ) 8617 8670 xt "-172000,47600,-149500,48400" 8618 st "SIGNAL config_data_valid : std_logic" 8671 st "SIGNAL config_data_valid : std_logic 8672 " 8619 8673 ) 8620 8674 ) … … 8633 8687 ) 8634 8688 xt "-172000,46000,-149500,46800" 8635 st "SIGNAL config_busy : std_logic" 8689 st "SIGNAL config_busy : std_logic 8690 " 8636 8691 ) 8637 8692 ) … … 8651 8706 ) 8652 8707 xt "-172000,46800,-139500,47600" 8653 st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0)" 8708 st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0) 8709 " 8654 8710 ) 8655 8711 ) … … 8668 8724 ) 8669 8725 xt "-172000,60400,-149500,61200" 8670 st "SIGNAL config_wr_en : std_logic" 8726 st "SIGNAL config_wr_en : std_logic 8727 " 8671 8728 ) 8672 8729 ) … … 8685 8742 ) 8686 8743 xt "-172000,48400,-149500,49200" 8687 st "SIGNAL config_rd_en : std_logic" 8744 st "SIGNAL config_rd_en : std_logic 8745 " 8688 8746 ) 8689 8747 ) … … 8702 8760 ) 8703 8761 xt "-172000,61200,-147000,62000" 8704 st "SIGNAL dac_array : dac_array_type" 8762 st "SIGNAL dac_array : dac_array_type 8763 " 8705 8764 ) 8706 8765 ) … … 8719 8778 ) 8720 8779 xt "-172000,55600,-149500,56400" 8721 st "SIGNAL config_start_cm : std_logic" 8780 st "SIGNAL config_start_cm : std_logic 8781 " 8722 8782 ) 8723 8783 ) … … 8736 8796 ) 8737 8797 xt "-172000,50000,-149500,50800" 8738 st "SIGNAL config_ready_cm : std_logic" 8798 st "SIGNAL config_ready_cm : std_logic 8799 " 8739 8800 ) 8740 8801 ) … … 8756 8817 ) 8757 8818 xt "-172000,28000,-126000,28800" 8758 st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 8819 st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 8820 " 8759 8821 ) 8760 8822 ) … … 8773 8835 ) 8774 8836 xt "-172000,91600,-149500,92400" 8775 st "SIGNAL sensor_ready : std_logic" 8837 st "SIGNAL sensor_ready : std_logic 8838 " 8776 8839 ) 8777 8840 ) … … 8790 8853 ) 8791 8854 xt "-172000,90800,-145500,91600" 8792 st "SIGNAL sensor_array : sensor_array_type" 8855 st "SIGNAL sensor_array : sensor_array_type 8856 " 8793 8857 ) 8794 8858 ) … … 8807 8871 ) 8808 8872 xt "-172000,50800,-149500,51600" 8809 st "SIGNAL config_ready_spi : std_logic" 8873 st "SIGNAL config_ready_spi : std_logic 8874 " 8810 8875 ) 8811 8876 ) … … 8826 8891 ) 8827 8892 xt "-172000,42000,-140000,42800" 8828 st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0)" 8893 st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0) 8894 " 8829 8895 ) 8830 8896 ) … … 8843 8909 ) 8844 8910 xt "-172000,41200,-144500,42000" 8845 st "SIGNAL adc_data_array_int : adc_data_array_type" 8911 st "SIGNAL adc_data_array_int : adc_data_array_type 8912 " 8846 8913 ) 8847 8914 ) … … 9133 9200 ) 9134 9201 xt "-172000,56400,-128500,57200" 9135 st "SIGNAL config_start_spi : std_logic := '0'" 9202 st "SIGNAL config_start_spi : std_logic := '0' 9203 " 9136 9204 ) 9137 9205 ) … … 9666 9734 ) 9667 9735 xt "-172000,30400,-153500,31200" 9668 st "sclk : std_logic" 9736 st "sclk : std_logic 9737 " 9669 9738 ) 9670 9739 ) … … 9685 9754 ) 9686 9755 xt "-172000,36000,-153500,36800" 9687 st "sio : std_logic" 9756 st "sio : std_logic 9757 " 9688 9758 ) 9689 9759 ) … … 9702 9772 ) 9703 9773 xt "-172000,24000,-153500,24800" 9704 st "dac_cs : std_logic" 9774 st "dac_cs : std_logic 9775 " 9705 9776 ) 9706 9777 ) … … 9720 9791 ) 9721 9792 xt "-172000,31200,-143500,32000" 9722 st "sensor_cs : std_logic_vector(3 DOWNTO 0)" 9793 st "sensor_cs : std_logic_vector(3 DOWNTO 0) 9794 " 9723 9795 ) 9724 9796 ) … … 9918 9990 ) 9919 9991 xt "-172000,76400,-128500,77200" 9920 st "SIGNAL new_config : std_logic := '0'" 9992 st "SIGNAL new_config : std_logic := '0' 9993 " 9921 9994 ) 9922 9995 ) … … 9935 10008 ) 9936 10009 xt "-172000,57200,-149500,58000" 9937 st "SIGNAL config_started : std_logic" 10010 st "SIGNAL config_started : std_logic 10011 " 9938 10012 ) 9939 10013 ) … … 9953 10027 ) 9954 10028 xt "-172000,59600,-128500,60400" 9955 st "SIGNAL config_started_spi : std_logic := '0'" 10029 st "SIGNAL config_started_spi : std_logic := '0' 10030 " 9956 10031 ) 9957 10032 ) … … 9971 10046 ) 9972 10047 xt "-172000,58000,-128500,58800" 9973 st "SIGNAL config_started_cu : std_logic := '0'" 10048 st "SIGNAL config_started_cu : std_logic := '0' 10049 " 9974 10050 ) 9975 10051 ) … … 9988 10064 ) 9989 10065 xt "-172000,58800,-149500,59600" 9990 st "SIGNAL config_started_mm : std_logic" 10066 st "SIGNAL config_started_mm : std_logic 10067 " 9991 10068 ) 9992 10069 ) … … 10006 10083 ) 10007 10084 xt "-172000,28800,-132000,29600" 10008 st "mosi : std_logic := '0'" 10085 st "mosi : std_logic := '0' 10086 " 10009 10087 ) 10010 10088 ) … … 10071 10149 ) 10072 10150 xt "-172000,24800,-118500,25600" 10073 st "denable : std_logic := '0' -- default domino wave off" 10151 st "denable : std_logic := '0' -- default domino wave off 10152 " 10074 10153 ) 10075 10154 ) … … 10133 10212 ) 10134 10213 xt "-172000,75600,-128500,76400" 10135 st "SIGNAL dwrite_enable : std_logic := '1'" 10214 st "SIGNAL dwrite_enable : std_logic := '1' 10215 " 10136 10216 ) 10137 10217 ) … … 10520 10600 ) 10521 10601 xt "-172000,74800,-128500,75600" 10522 st "SIGNAL dwrite : std_logic := '1'" 10602 st "SIGNAL dwrite : std_logic := '1' 10603 " 10523 10604 ) 10524 10605 ) … … 10894 10975 ) 10895 10976 xt "-172000,100400,-149500,101200" 10896 st "SIGNAL wiz_ack : std_logic" 10977 st "SIGNAL wiz_ack : std_logic 10978 " 10897 10979 ) 10898 10980 ) … … 11277 11359 ) 11278 11360 xt "-172000,89200,-149500,90000" 11279 st "SIGNAL sclk1 : std_logic" 11361 st "SIGNAL sclk1 : std_logic 11362 " 11280 11363 ) 11281 11364 ) … … 11294 11377 ) 11295 11378 xt "-172000,90000,-149500,90800" 11296 st "SIGNAL sclk_enable : std_logic" 11379 st "SIGNAL sclk_enable : std_logic 11380 " 11297 11381 ) 11298 11382 ) … … 11312 11396 ) 11313 11397 xt "-172000,18400,-132000,19200" 11314 st "adc_clk_en : std_logic := '0'" 11398 st "adc_clk_en : std_logic := '0' 11399 " 11315 11400 ) 11316 11401 ) … … 11766 11851 ) 11767 11852 xt "-172000,78000,-113000,78800" 11768 st "SIGNAL ps_direction : std_logic := '1' -- default phase shift upwards" 11853 st "SIGNAL ps_direction : std_logic := '1' -- default phase shift upwards 11854 " 11769 11855 ) 11770 11856 ) … … 11787 11873 ) 11788 11874 xt "-172000,78800,-112000,79600" 11789 st "SIGNAL ps_do_phase_shift : std_logic := '0' --pulse this to phase shift once" 11875 st "SIGNAL ps_do_phase_shift : std_logic := '0' --pulse this to phase shift once 11876 " 11790 11877 ) 11791 11878 ) … … 11807 11894 ) 11808 11895 xt "-172000,79600,-104500,80400" 11809 st "SIGNAL ps_reset : std_logic := '0' -- pulse this to reset the variable phase shift" 11896 st "SIGNAL ps_reset : std_logic := '0' -- pulse this to reset the variable phase shift 11897 " 11810 11898 ) 11811 11899 ) … … 11825 11913 ) 11826 11914 xt "-172000,94000,-128500,94800" 11827 st "SIGNAL srclk_enable : std_logic := '0'" 11915 st "SIGNAL srclk_enable : std_logic := '0' 11916 " 11828 11917 ) 11829 11918 ) … … 12209 12298 ) 12210 12299 xt "-172000,40400,-128500,41200" 12211 st "SIGNAL SRCLK1 : std_logic := '0'" 12300 st "SIGNAL SRCLK1 : std_logic := '0' 12301 " 12212 12302 ) 12213 12303 ) … … 12231 12321 xt "-172000,51600,-128500,53200" 12232 12322 st "-- -- 12233 SIGNAL config_rw_ack : std_logic := '0'" 12323 SIGNAL config_rw_ack : std_logic := '0' 12324 " 12234 12325 ) 12235 12326 ) … … 12253 12344 xt "-172000,53200,-128500,54800" 12254 12345 st "-- -- 12255 SIGNAL config_rw_ready : std_logic := '0'" 12346 SIGNAL config_rw_ready : std_logic := '0' 12347 " 12256 12348 ) 12257 12349 ) … … 12270 12362 ) 12271 12363 xt "-172000,87600,-149500,88400" 12272 st "SIGNAL s_trigger : std_logic" 12364 st "SIGNAL s_trigger : std_logic 12365 " 12273 12366 ) 12274 12367 ) … … 12287 12380 ) 12288 12381 xt "-172000,96400,-149500,97200" 12289 st "SIGNAL start_srin_write_8b : std_logic" 12382 st "SIGNAL start_srin_write_8b : std_logic 12383 " 12290 12384 ) 12291 12385 ) … … 12305 12399 ) 12306 12400 xt "-172000,94800,-128500,95600" 12307 st "SIGNAL srin_write_ack : std_logic := '0'" 12401 st "SIGNAL srin_write_ack : std_logic := '0' 12402 " 12308 12403 ) 12309 12404 ) … … 12323 12418 ) 12324 12419 xt "-172000,95600,-128500,96400" 12325 st "SIGNAL srin_write_ready : std_logic := '0'" 12420 st "SIGNAL srin_write_ready : std_logic := '0' 12421 " 12326 12422 ) 12327 12423 ) … … 12342 12438 ) 12343 12439 xt "-172000,74000,-122500,74800" 12344 st "SIGNAL drs_srin_data : std_logic_vector(7 downto 0) := (others => '0')" 12440 st "SIGNAL drs_srin_data : std_logic_vector(7 downto 0) := (others => '0') 12441 " 12345 12442 ) 12346 12443 ) … … 12360 12457 ) 12361 12458 xt "-172000,17600,-132000,18400" 12362 st "SRIN_out : std_logic := '0'" 12459 st "SRIN_out : std_logic := '0' 12460 " 12363 12461 ) 12364 12462 ) … … 12863 12961 ) 12864 12962 *431 (Net 12865 uid 10449,012866 decl (Decl12867 n "trigger_out"12868 t "std_logic"12869 preAdd 012870 posAdd 012871 o 12012872 suid 240,012873 )12874 declText (MLText12875 uid 10450,012876 va (VaSet12877 font "Courier New,8,0"12878 )12879 xt "-172000,99600,-149500,100400"12880 st "SIGNAL trigger_out : std_logic"12881 )12882 )12883 *432 (Net12884 12963 uid 10465,0 12885 12964 lang 2 … … 12901 12980 xt "-172000,84400,-128500,86000" 12902 12981 st "-- -- 12903 SIGNAL ram_write_ready_ack : std_logic := '0'" 12904 ) 12905 ) 12906 *433 (Net 12982 SIGNAL ram_write_ready_ack : std_logic := '0' 12983 " 12984 ) 12985 ) 12986 *432 (Net 12907 12987 uid 10627,0 12908 12988 decl (Decl … … 12918 12998 ) 12919 12999 xt "-172000,92400,-149500,93200" 12920 st "SIGNAL socks_connected : std_logic" 12921 ) 12922 ) 12923 *434 (Net 13000 st "SIGNAL socks_connected : std_logic 13001 " 13002 ) 13003 ) 13004 *433 (Net 12924 13005 uid 10635,0 12925 13006 decl (Decl … … 12935 13016 ) 12936 13017 xt "-172000,93200,-149500,94000" 12937 st "SIGNAL socks_waiting : std_logic" 12938 ) 12939 ) 12940 *435 (Net 13018 st "SIGNAL socks_waiting : std_logic 13019 " 13020 ) 13021 ) 13022 *434 (Net 12941 13023 uid 10721,0 12942 13024 decl (Decl … … 12952 13034 ) 12953 13035 xt "-172000,27200,-153500,28000" 12954 st "green : std_logic" 12955 ) 12956 ) 12957 *436 (PortIoOut 13036 st "green : std_logic 13037 " 13038 ) 13039 ) 13040 *435 (PortIoOut 12958 13041 uid 10729,0 12959 13042 shape (CompositeShape … … 12999 13082 ) 13000 13083 ) 13001 *43 7(Net13084 *436 (Net 13002 13085 uid 10735,0 13003 13086 decl (Decl … … 13013 13096 ) 13014 13097 xt "-172000,22400,-153500,23200" 13015 st "amber : std_logic" 13016 ) 13017 ) 13018 *438 (PortIoOut 13098 st "amber : std_logic 13099 " 13100 ) 13101 ) 13102 *437 (PortIoOut 13019 13103 uid 10743,0 13020 13104 shape (CompositeShape … … 13060 13144 ) 13061 13145 ) 13062 *43 9(Net13146 *438 (Net 13063 13147 uid 10749,0 13064 13148 decl (Decl … … 13074 13158 ) 13075 13159 xt "-172000,29600,-153500,30400" 13076 st "red : std_logic" 13077 ) 13078 ) 13079 *440 (PortIoOut 13160 st "red : std_logic 13161 " 13162 ) 13163 ) 13164 *439 (PortIoOut 13080 13165 uid 10757,0 13081 13166 shape (CompositeShape … … 13121 13206 ) 13122 13207 ) 13123 *44 1(SaComponent13208 *440 (SaComponent 13124 13209 uid 11209,0 13125 13210 optionalChildren [ 13126 *44 2(CptPort13211 *441 (CptPort 13127 13212 uid 11181,0 13128 13213 ps "OnEdgeStrategy" … … 13157 13242 ) 13158 13243 ) 13159 *44 3(CptPort13244 *442 (CptPort 13160 13245 uid 11185,0 13161 13246 ps "OnEdgeStrategy" … … 13192 13277 ) 13193 13278 ) 13194 *44 4(CptPort13279 *443 (CptPort 13195 13280 uid 11189,0 13196 13281 ps "OnEdgeStrategy" … … 13227 13312 ) 13228 13313 ) 13229 *44 5(CptPort13314 *444 (CptPort 13230 13315 uid 11193,0 13231 13316 ps "OnEdgeStrategy" … … 13262 13347 ) 13263 13348 ) 13264 *44 6(CptPort13349 *445 (CptPort 13265 13350 uid 11197,0 13266 13351 ps "OnEdgeStrategy" … … 13295 13380 ) 13296 13381 ) 13297 *44 7(CptPort13382 *446 (CptPort 13298 13383 uid 11201,0 13299 13384 ps "OnEdgeStrategy" … … 13328 13413 ) 13329 13414 ) 13330 *44 8(CptPort13415 *447 (CptPort 13331 13416 uid 11205,0 13332 13417 ps "OnEdgeStrategy" … … 13361 13446 ) 13362 13447 ) 13363 *44 9(CptPort13448 *448 (CptPort 13364 13449 uid 12693,0 13365 13450 ps "OnEdgeStrategy" … … 13413 13498 stg "VerticalLayoutStrategy" 13414 13499 textVec [ 13415 *4 50(Text13500 *449 (Text 13416 13501 uid 11212,0 13417 13502 va (VaSet … … 13423 13508 tm "BdLibraryNameMgr" 13424 13509 ) 13425 *45 1(Text13510 *450 (Text 13426 13511 uid 11213,0 13427 13512 va (VaSet … … 13433 13518 tm "CptNameMgr" 13434 13519 ) 13435 *45 2(Text13520 *451 (Text 13436 13521 uid 11214,0 13437 13522 va (VaSet … … 13500 13585 archFileType "UNKNOWN" 13501 13586 ) 13502 *45 3(Net13587 *452 (Net 13503 13588 uid 11403,0 13504 13589 decl (Decl … … 13514 13599 ) 13515 13600 xt "-172000,72400,-149500,73200" 13516 st "SIGNAL drs_readout_started : std_logic" 13517 ) 13518 ) 13519 *454 (Net 13601 st "SIGNAL drs_readout_started : std_logic 13602 " 13603 ) 13604 ) 13605 *453 (Net 13520 13606 uid 11856,0 13521 13607 decl (Decl … … 13531 13617 ) 13532 13618 xt "-172000,98000,-149500,98800" 13533 st "SIGNAL trigger_enable : std_logic" 13534 ) 13535 ) 13536 *455 (MWC 13619 st "SIGNAL trigger_enable : std_logic 13620 " 13621 ) 13622 ) 13623 *454 (MWC 13537 13624 uid 12295,0 13538 13625 optionalChildren [ 13539 *45 6(CptPort13626 *455 (CptPort 13540 13627 uid 12267,0 13541 13628 optionalChildren [ 13542 *45 7(Line13629 *456 (Line 13543 13630 uid 12271,0 13544 13631 layer 5 … … 13553 13640 ] 13554 13641 ) 13555 *45 8(Property13642 *457 (Property 13556 13643 uid 12272,0 13557 13644 pclass "_MW_GEOM_" … … 13600 13687 ) 13601 13688 ) 13602 *45 9(CptPort13689 *458 (CptPort 13603 13690 uid 12273,0 13604 13691 optionalChildren [ 13605 *4 60(Line13692 *459 (Line 13606 13693 uid 12277,0 13607 13694 layer 5 … … 13655 13742 ) 13656 13743 ) 13657 *46 1(CptPort13744 *460 (CptPort 13658 13745 uid 12278,0 13659 13746 optionalChildren [ 13660 *46 2(Line13747 *461 (Line 13661 13748 uid 12282,0 13662 13749 layer 5 … … 13708 13795 ) 13709 13796 ) 13710 *46 3(CommentGraphic13797 *462 (CommentGraphic 13711 13798 uid 12283,0 13712 13799 optionalChildren [ 13713 *46 4(Property13800 *463 (Property 13714 13801 uid 12285,0 13715 13802 pclass "_MW_GEOM_" … … 13735 13822 oxt "7000,10000,7000,10000" 13736 13823 ) 13737 *46 5(CommentGraphic13824 *464 (CommentGraphic 13738 13825 uid 12286,0 13739 13826 optionalChildren [ 13740 *46 6(Property13827 *465 (Property 13741 13828 uid 12288,0 13742 13829 pclass "_MW_GEOM_" … … 13762 13849 oxt "7000,6000,7000,6000" 13763 13850 ) 13764 *46 7(Grouping13851 *466 (Grouping 13765 13852 uid 12289,0 13766 13853 optionalChildren [ 13767 *46 8(CommentGraphic13854 *467 (CommentGraphic 13768 13855 uid 12291,0 13769 13856 shape (PolyLine2D … … 13786 13873 oxt "7000,6000,9000,10000" 13787 13874 ) 13788 *46 9(CommentGraphic13875 *468 (CommentGraphic 13789 13876 uid 12293,0 13790 13877 shape (Arc2D … … 13839 13926 stg "VerticalLayoutStrategy" 13840 13927 textVec [ 13841 *4 70(Text13928 *469 (Text 13842 13929 uid 12298,0 13843 13930 va (VaSet … … 13849 13936 blo "-80500,73300" 13850 13937 ) 13851 *47 1(Text13938 *470 (Text 13852 13939 uid 12299,0 13853 13940 va (VaSet … … 13858 13945 blo "-80500,74300" 13859 13946 ) 13860 *47 2(Text13947 *471 (Text 13861 13948 uid 12300,0 13862 13949 va (VaSet … … 13903 13990 ) 13904 13991 ) 13905 *47 3(Net13992 *472 (Net 13906 13993 uid 12304,0 13907 13994 decl (Decl … … 13919 14006 ) 13920 14007 xt "-172000,65200,-149500,66000" 13921 st "SIGNAL dout : std_logic" 13922 ) 13923 ) 13924 *474 (SaComponent 14008 st "SIGNAL dout : std_logic 14009 " 14010 ) 14011 ) 14012 *473 (SaComponent 13925 14013 uid 12625,0 13926 14014 optionalChildren [ 13927 *47 5(CptPort14015 *474 (CptPort 13928 14016 uid 12605,0 13929 14017 ps "OnEdgeStrategy" … … 13958 14046 ) 13959 14047 ) 13960 *47 6(CptPort14048 *475 (CptPort 13961 14049 uid 12609,0 13962 14050 ps "OnEdgeStrategy" … … 13994 14082 ) 13995 14083 ) 13996 *47 7(CptPort14084 *476 (CptPort 13997 14085 uid 12613,0 13998 14086 ps "OnEdgeStrategy" … … 14029 14117 ) 14030 14118 ) 14031 *47 8(CptPort14119 *477 (CptPort 14032 14120 uid 12617,0 14033 14121 ps "OnEdgeStrategy" … … 14063 14151 ) 14064 14152 ) 14065 *47 9(CptPort14153 *478 (CptPort 14066 14154 uid 12621,0 14067 14155 ps "OnEdgeStrategy" … … 14099 14187 ) 14100 14188 ) 14101 *4 80(CptPort14189 *479 (CptPort 14102 14190 uid 12673,0 14103 14191 ps "OnEdgeStrategy" … … 14149 14237 stg "VerticalLayoutStrategy" 14150 14238 textVec [ 14151 *48 1(Text14239 *480 (Text 14152 14240 uid 12628,0 14153 14241 va (VaSet … … 14159 14247 tm "BdLibraryNameMgr" 14160 14248 ) 14161 *48 2(Text14249 *481 (Text 14162 14250 uid 12629,0 14163 14251 va (VaSet … … 14169 14257 tm "CptNameMgr" 14170 14258 ) 14171 *48 3(Text14259 *482 (Text 14172 14260 uid 12630,0 14173 14261 va (VaSet … … 14216 14304 archFileType "UNKNOWN" 14217 14305 ) 14218 *48 4(Net14306 *483 (Net 14219 14307 uid 12641,0 14220 14308 decl (Decl … … 14232 14320 ) 14233 14321 xt "-172000,66000,-149500,66800" 14234 st "SIGNAL dout1 : std_logic" 14235 ) 14236 ) 14237 *485 (Net 14322 st "SIGNAL dout1 : std_logic 14323 " 14324 ) 14325 ) 14326 *484 (Net 14238 14327 uid 12647,0 14239 14328 decl (Decl … … 14256 14345 st "-- -- 14257 14346 -- drs_dwrite : out std_logic := '1'; 14258 SIGNAL drs_readout_ready : std_logic := '0'" 14259 ) 14260 ) 14261 *486 (Net 14347 SIGNAL drs_readout_ready : std_logic := '0' 14348 " 14349 ) 14350 ) 14351 *485 (Net 14262 14352 uid 12653,0 14263 14353 decl (Decl … … 14273 14363 ) 14274 14364 xt "-172000,71600,-149500,72400" 14275 st "SIGNAL drs_readout_ready_ack : std_logic" 14276 ) 14277 ) 14278 *487 (Net 14365 st "SIGNAL drs_readout_ready_ack : std_logic 14366 " 14367 ) 14368 ) 14369 *486 (Net 14279 14370 uid 12705,0 14280 14371 decl (Decl … … 14290 14381 ) 14291 14382 xt "-172000,20000,-153500,20800" 14292 st "additional_flasher_out : std_logic" 14293 ) 14294 ) 14295 *488 (PortIoOut 14383 st "additional_flasher_out : std_logic 14384 " 14385 ) 14386 ) 14387 *487 (PortIoOut 14296 14388 uid 12713,0 14297 14389 shape (CompositeShape … … 14337 14429 ) 14338 14430 ) 14339 *48 9(SaComponent14431 *488 (SaComponent 14340 14432 uid 13117,0 14341 14433 optionalChildren [ 14342 *4 90(CptPort14434 *489 (CptPort 14343 14435 uid 13101,0 14344 14436 ps "OnEdgeStrategy" … … 14350 14442 fg "0,65535,0" 14351 14443 ) 14352 xt " 63000,61625,63750,62375"14444 xt "72000,61625,72750,62375" 14353 14445 ) 14354 14446 tg (CPTG … … 14360 14452 va (VaSet 14361 14453 ) 14362 xt "6 0100,61500,62000,62500"14454 xt "69100,61500,71000,62500" 14363 14455 st "CLK" 14364 14456 ju 2 14365 blo " 62000,62300"14457 blo "71000,62300" 14366 14458 ) 14367 14459 ) … … 14374 14466 ) 14375 14467 ) 14376 *49 1(CptPort14468 *490 (CptPort 14377 14469 uid 13105,0 14378 14470 ps "OnEdgeStrategy" … … 14384 14476 fg "0,65535,0" 14385 14477 ) 14386 xt " 63000,62625,63750,63375"14478 xt "72000,62625,72750,63375" 14387 14479 ) 14388 14480 tg (CPTG … … 14394 14486 va (VaSet 14395 14487 ) 14396 xt " 59400,62500,62000,63500"14488 xt "68400,62500,71000,63500" 14397 14489 st "enable" 14398 14490 ju 2 14399 blo " 62000,63300"14491 blo "71000,63300" 14400 14492 ) 14401 14493 ) … … 14408 14500 ) 14409 14501 ) 14410 *49 2(CptPort14502 *491 (CptPort 14411 14503 uid 13109,0 14412 14504 ps "OnEdgeStrategy" … … 14418 14510 fg "0,65535,0" 14419 14511 ) 14420 xt " 63000,63625,63750,64375"14512 xt "72000,63625,72750,64375" 14421 14513 ) 14422 14514 tg (CPTG … … 14428 14520 va (VaSet 14429 14521 ) 14430 xt " 55900,63500,62000,64500"14522 xt "64900,63500,71000,64500" 14431 14523 st "multiplier : (7:0)" 14432 14524 ju 2 14433 blo " 62000,64300"14525 blo "71000,64300" 14434 14526 ) 14435 14527 ) … … 14443 14535 ) 14444 14536 ) 14445 *49 3(CptPort14537 *492 (CptPort 14446 14538 uid 13113,0 14447 14539 ps "OnEdgeStrategy" … … 14453 14545 fg "0,65535,0" 14454 14546 ) 14455 xt "5 0250,61625,51000,62375"14547 xt "59250,61625,60000,62375" 14456 14548 ) 14457 14549 tg (CPTG … … 14463 14555 va (VaSet 14464 14556 ) 14465 xt " 52000,61500,54800,62500"14557 xt "61000,61500,63800,62500" 14466 14558 st "trigger" 14467 blo " 52000,62300"14559 blo "61000,62300" 14468 14560 ) 14469 14561 ) … … 14486 14578 lineWidth 2 14487 14579 ) 14488 xt " 51000,61000,63000,65000"14580 xt "60000,61000,72000,65000" 14489 14581 ) 14490 14582 oxt "0,0,8000,10000" … … 14494 14586 stg "VerticalLayoutStrategy" 14495 14587 textVec [ 14588 *493 (Text 14589 uid 13120,0 14590 va (VaSet 14591 font "Arial,8,1" 14592 ) 14593 xt "62350,65000,68550,66000" 14594 st "FACT_FAD_lib" 14595 blo "62350,65800" 14596 tm "BdLibraryNameMgr" 14597 ) 14496 14598 *494 (Text 14497 uid 1312 0,014599 uid 13121,0 14498 14600 va (VaSet 14499 14601 font "Arial,8,1" 14500 14602 ) 14501 xt " 53350,65000,59550,66000"14502 st " FACT_FAD_lib"14503 blo " 53350,65800"14504 tm " BdLibraryNameMgr"14603 xt "62350,66000,69650,67000" 14604 st "continous_pulser" 14605 blo "62350,66800" 14606 tm "CptNameMgr" 14505 14607 ) 14506 14608 *495 (Text 14507 uid 1312 1,014609 uid 13122,0 14508 14610 va (VaSet 14509 14611 font "Arial,8,1" 14510 14612 ) 14511 xt "53350,66000,60650,67000" 14512 st "continous_pulser" 14513 blo "53350,66800" 14514 tm "CptNameMgr" 14515 ) 14516 *496 (Text 14517 uid 13122,0 14518 va (VaSet 14519 font "Arial,8,1" 14520 ) 14521 xt "53350,67000,55150,68000" 14613 xt "62350,67000,64150,68000" 14522 14614 st "U_3" 14523 blo " 53350,67800"14615 blo "62350,67800" 14524 14616 tm "InstanceNameMgr" 14525 14617 ) … … 14536 14628 font "Courier New,8,0" 14537 14629 ) 14538 xt " 44000,60200,71500,61000"14630 xt "53000,60200,80500,61000" 14539 14631 st "MINIMAL_TRIGGER_WAIT_TIME = 250000 ( integer ) " 14540 14632 ) … … 14556 14648 fg "49152,49152,49152" 14557 14649 ) 14558 xt " 51250,63250,52750,64750"14650 xt "60250,63250,61750,64750" 14559 14651 iconName "VhdlFileViewIcon.png" 14560 14652 iconMaskName "VhdlFileViewIcon.msk" … … 14567 14659 archFileType "UNKNOWN" 14568 14660 ) 14569 *49 7(Net14661 *496 (Net 14570 14662 uid 13157,0 14571 14663 decl (Decl … … 14582 14674 ) 14583 14675 xt "-172000,43600,-128500,44400" 14584 st "SIGNAL c_trigger_enable : std_logic := '0'" 14585 ) 14586 ) 14587 *498 (Net 14676 st "SIGNAL c_trigger_enable : std_logic := '0' 14677 " 14678 ) 14679 ) 14680 *497 (Net 14588 14681 uid 13163,0 14589 14682 decl (Decl … … 14603 14696 ) 14604 14697 xt "-172000,44400,-112000,45200" 14605 st "SIGNAL c_trigger_mult : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1') --subject to changes" 14606 ) 14607 ) 14608 *499 (Net 14698 st "SIGNAL c_trigger_mult : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1') --subject to changes 14699 " 14700 ) 14701 ) 14702 *498 (Net 14609 14703 uid 13206,0 14610 14704 decl (Decl … … 14620 14714 ) 14621 14715 xt "-172000,88400,-149500,89200" 14622 st "SIGNAL s_trigger_0 : std_logic" 14623 ) 14624 ) 14625 *500 (Net 14716 st "SIGNAL s_trigger_0 : std_logic 14717 " 14718 ) 14719 ) 14720 *499 (Net 14626 14721 uid 13208,0 14627 14722 decl (Decl … … 14637 14732 ) 14638 14733 xt "-172000,97200,-149500,98000" 14639 st "SIGNAL trigger1 : std_logic" 14640 ) 14641 ) 14642 *501 (MWC 14734 st "SIGNAL trigger1 : std_logic 14735 " 14736 ) 14737 ) 14738 *500 (MWC 14643 14739 uid 13266,0 14644 14740 optionalChildren [ 14645 *50 2(CptPort14741 *501 (CptPort 14646 14742 uid 13230,0 14647 14743 optionalChildren [ 14648 *50 3(Line14744 *502 (Line 14649 14745 uid 13234,0 14650 14746 layer 5 … … 14653 14749 vasetType 3 14654 14750 ) 14655 xt " 40408,62000,42000,62000"14656 pts [ 14657 " 42000,62000"14658 " 40408,62000"14751 xt "52408,62000,54000,62000" 14752 pts [ 14753 "54000,62000" 14754 "52408,62000" 14659 14755 ] 14660 14756 ) … … 14669 14765 fg "0,65535,65535" 14670 14766 ) 14671 xt " 42000,61625,42750,62375"14767 xt "54000,61625,54750,62375" 14672 14768 ) 14673 14769 tg (CPTG … … 14682 14778 font "arial,8,0" 14683 14779 ) 14684 xt "2 05750,61700,207550,62700"14780 xt "217750,61700,219550,62700" 14685 14781 st "din1" 14686 14782 ju 2 14687 blo "2 07550,62500"14783 blo "219550,62500" 14688 14784 ) 14689 14785 ) … … 14697 14793 ) 14698 14794 ) 14699 *50 4(CptPort14795 *503 (CptPort 14700 14796 uid 13235,0 14701 14797 optionalChildren [ 14702 *50 5(Property14798 *504 (Property 14703 14799 uid 13239,0 14704 14800 pclass "_MW_GEOM_" … … 14706 14802 ptn "String" 14707 14803 ) 14708 *50 6(Line14804 *505 (Line 14709 14805 uid 13240,0 14710 14806 layer 5 … … 14713 14809 vasetType 3 14714 14810 ) 14715 xt " 36000,61000,37000,61000"14716 pts [ 14717 " 36000,61000"14718 " 37000,61000"14811 xt "48000,61000,49000,61000" 14812 pts [ 14813 "48000,61000" 14814 "49000,61000" 14719 14815 ] 14720 14816 ) … … 14729 14825 fg "0,65535,65535" 14730 14826 ) 14731 xt " 35250,60625,36000,61375"14827 xt "47250,60625,48000,61375" 14732 14828 ) 14733 14829 tg (CPTG … … 14742 14838 font "arial,8,0" 14743 14839 ) 14744 xt "2 02500,60532,204300,61532"14840 xt "214500,60532,216300,61532" 14745 14841 st "dout" 14746 blo "2 02500,61332"14842 blo "214500,61332" 14747 14843 ) 14748 14844 ) … … 14757 14853 ) 14758 14854 ) 14759 *50 7(CptPort14855 *506 (CptPort 14760 14856 uid 13241,0 14761 14857 optionalChildren [ 14762 *50 8(Line14858 *507 (Line 14763 14859 uid 13245,0 14764 14860 layer 5 … … 14767 14863 vasetType 3 14768 14864 ) 14769 xt " 40408,60000,42000,60000"14770 pts [ 14771 " 42000,60000"14772 " 40408,60000"14865 xt "52408,60000,54000,60000" 14866 pts [ 14867 "54000,60000" 14868 "52408,60000" 14773 14869 ] 14774 14870 ) … … 14783 14879 fg "0,65535,65535" 14784 14880 ) 14785 xt " 42000,59625,42750,60375"14881 xt "54000,59625,54750,60375" 14786 14882 ) 14787 14883 tg (CPTG … … 14796 14892 font "arial,8,0" 14797 14893 ) 14798 xt "2 05635,59294,207435,60294"14894 xt "217635,59294,219435,60294" 14799 14895 st "din0" 14800 14896 ju 2 14801 blo "2 07435,60094"14897 blo "219435,60094" 14802 14898 ) 14803 14899 ) … … 14811 14907 ) 14812 14908 ) 14813 *50 9(CommentGraphic14909 *508 (CommentGraphic 14814 14910 uid 13246,0 14815 14911 shape (Arc2D 14816 14912 pts [ 14817 " 37000,61000"14818 " 38737,59521"14819 " 41000,59004"14913 "49000,61000" 14914 "50737,59521" 14915 "53000,59004" 14820 14916 ] 14821 14917 uid 13247,0 … … 14828 14924 lineColor "26368,26368,26368" 14829 14925 ) 14830 xt " 37000,59003,41000,61000"14926 xt "49000,59003,53000,61000" 14831 14927 ) 14832 14928 oxt "7000,6003,11000,8000" 14833 14929 ) 14834 *5 10(CommentGraphic14930 *509 (CommentGraphic 14835 14931 uid 13248,0 14836 14932 shape (Arc2D 14837 14933 pts [ 14838 " 41004,62998"14839 " 38551,62394"14840 " 37000,61005"14934 "53004,62998" 14935 "50551,62394" 14936 "49000,61005" 14841 14937 ] 14842 14938 uid 13249,0 … … 14849 14945 lineColor "26368,26368,26368" 14850 14946 ) 14851 xt " 37000,61005,41004,62999"14947 xt "49000,61005,53004,62999" 14852 14948 ) 14853 14949 oxt "7000,8005,11004,10000" 14854 14950 ) 14855 *51 1(Grouping14951 *510 (Grouping 14856 14952 uid 13250,0 14857 14953 optionalChildren [ 14858 *51 2(CommentGraphic14954 *511 (CommentGraphic 14859 14955 uid 13252,0 14860 14956 optionalChildren [ 14861 *51 3(Property14957 *512 (Property 14862 14958 uid 13254,0 14863 14959 pclass "_MW_GEOM_" … … 14868 14964 shape (CustomPolygon 14869 14965 pts [ 14870 " 41000,62998"14871 " 38952,62132"14872 " 37000,61000"14873 " 38048,60156"14874 " 39817,59211"14875 " 41000,59000"14876 " 41000,62998"14966 "53000,62998" 14967 "50952,62132" 14968 "49000,61000" 14969 "50048,60156" 14970 "51817,59211" 14971 "53000,59000" 14972 "53000,62998" 14877 14973 ] 14878 14974 uid 13253,0 … … 14886 14982 fillStyle 1 14887 14983 ) 14888 xt " 37000,59000,41000,62998"14984 xt "49000,59000,53000,62998" 14889 14985 ) 14890 14986 oxt "7000,6000,11000,9998" 14891 14987 ) 14892 *51 4(CommentGraphic14988 *513 (CommentGraphic 14893 14989 uid 13255,0 14894 14990 optionalChildren [ 14895 *51 5(Property14991 *514 (Property 14896 14992 uid 13257,0 14897 14993 pclass "_MW_GEOM_" … … 14902 14998 shape (Arc2D 14903 14999 pts [ 14904 " 41000,63000"14905 " 40237,61001"14906 " 41000,59000"15000 "53000,63000" 15001 "52237,61001" 15002 "53000,59000" 14907 15003 ] 14908 15004 uid 13256,0 … … 14917 15013 fillStyle 1 14918 15014 ) 14919 xt " 40236,59000,41000,63000"15015 xt "52236,59000,53000,63000" 14920 15016 ) 14921 15017 oxt "10238,6000,11000,10000" … … 14931 15027 lineWidth 2 14932 15028 ) 14933 xt " 37000,59000,41000,63000"15029 xt "49000,59000,53000,63000" 14934 15030 ) 14935 15031 oxt "7000,6000,11000,10000" 14936 15032 ) 14937 *51 6(CommentGraphic15033 *515 (CommentGraphic 14938 15034 uid 13258,0 14939 15035 shape (PolyLine2D 14940 15036 pts [ 14941 " 37000,61000"14942 " 37000,61000"15037 "49000,61000" 15038 "49000,61000" 14943 15039 ] 14944 15040 uid 13259,0 … … 14950 15046 fg "49152,49152,49152" 14951 15047 ) 14952 xt " 37000,61000,37000,61000"15048 xt "49000,61000,49000,61000" 14953 15049 ) 14954 15050 oxt "7000,8000,7000,8000" 14955 15051 ) 14956 *51 7(CommentGraphic15052 *516 (CommentGraphic 14957 15053 uid 13260,0 14958 15054 optionalChildren [ 14959 *51 8(Property15055 *517 (Property 14960 15056 uid 13262,0 14961 15057 pclass "_MW_GEOM_" … … 14966 15062 shape (PolyLine2D 14967 15063 pts [ 14968 " 41000,59000"14969 " 41000,59000"15064 "53000,59000" 15065 "53000,59000" 14970 15066 ] 14971 15067 uid 13261,0 … … 14977 15073 fg "49152,49152,49152" 14978 15074 ) 14979 xt " 41000,59000,41000,59000"15075 xt "53000,59000,53000,59000" 14980 15076 ) 14981 15077 oxt "11000,6000,11000,6000" 14982 15078 ) 14983 *51 9(CommentGraphic15079 *518 (CommentGraphic 14984 15080 uid 13263,0 14985 15081 optionalChildren [ 14986 *5 20(Property15082 *519 (Property 14987 15083 uid 13265,0 14988 15084 pclass "_MW_GEOM_" … … 14993 15089 shape (PolyLine2D 14994 15090 pts [ 14995 " 41000,63000"14996 " 41000,63000"15091 "53000,63000" 15092 "53000,63000" 14997 15093 ] 14998 15094 uid 13264,0 … … 15004 15100 fg "49152,49152,49152" 15005 15101 ) 15006 xt " 41000,63000,41000,63000"15102 xt "53000,63000,53000,63000" 15007 15103 ) 15008 15104 oxt "11000,10000,11000,10000" … … 15017 15113 lineWidth -1 15018 15114 ) 15019 xt " 36000,59000,42000,63000"15115 xt "48000,59000,54000,63000" 15020 15116 fos 1 15021 15117 ) … … 15027 15123 stg "VerticalLayoutStrategy" 15028 15124 textVec [ 15029 *52 1(Text15125 *520 (Text 15030 15126 uid 13269,0 15031 15127 va (VaSet … … 15033 15129 font "arial,8,0" 15034 15130 ) 15035 xt " 37500,61500,42300,62500"15131 xt "49500,61500,54300,62500" 15036 15132 st "moduleware" 15037 blo "37500,62300" 15133 blo "49500,62300" 15134 ) 15135 *521 (Text 15136 uid 13270,0 15137 va (VaSet 15138 font "arial,8,0" 15139 ) 15140 xt "49500,62500,50600,63500" 15141 st "or" 15142 blo "49500,63300" 15038 15143 ) 15039 15144 *522 (Text 15040 uid 1327 0,015145 uid 13271,0 15041 15146 va (VaSet 15042 15147 font "arial,8,0" 15043 15148 ) 15044 xt "37500,62500,38600,63500" 15045 st "or" 15046 blo "37500,63300" 15047 ) 15048 *523 (Text 15049 uid 13271,0 15050 va (VaSet 15051 font "arial,8,0" 15052 ) 15053 xt "37500,63500,39700,64500" 15149 xt "49500,63500,51700,64500" 15054 15150 st "U_13" 15055 blo " 37500,64300"15151 blo "49500,64300" 15056 15152 tm "InstanceNameMgr" 15057 15153 ) … … 15068 15164 font "arial,8,0" 15069 15165 ) 15070 xt " 21000,50000,21000,50000"15166 xt "33000,50000,33000,50000" 15071 15167 ) 15072 15168 header "" … … 15091 15187 ) 15092 15188 ) 15093 *52 4(PortIoIn15189 *523 (PortIoIn 15094 15190 uid 13689,0 15095 15191 shape (CompositeShape … … 15136 15232 ) 15137 15233 ) 15138 *52 5(Net15234 *524 (Net 15139 15235 uid 13701,0 15140 15236 decl (Decl … … 15151 15247 ) 15152 15248 xt "-172000,4000,-143500,4800" 15153 st "D_T_in : std_logic_vector(1 DOWNTO 0)" 15154 ) 15155 ) 15156 *526 (PortIoIn 15249 st "D_T_in : std_logic_vector(1 DOWNTO 0) 15250 " 15251 ) 15252 ) 15253 *525 (PortIoIn 15157 15254 uid 14042,0 15158 15255 shape (CompositeShape … … 15199 15296 ) 15200 15297 ) 15201 *52 7(Net15298 *526 (Net 15202 15299 uid 14054,0 15203 15300 decl (Decl … … 15214 15311 ) 15215 15312 xt "-172000,11200,-121500,12000" 15216 st "drs_refclk_in : std_logic -- used to check if DRS REFCLK exsists, if not DENABLE inhibit" 15217 ) 15218 ) 15219 *528 (PortIoIn 15313 st "drs_refclk_in : std_logic -- used to check if DRS REFCLK exsists, if not DENABLE inhibit 15314 " 15315 ) 15316 ) 15317 *527 (PortIoIn 15220 15318 uid 14165,0 15221 15319 shape (CompositeShape … … 15262 15360 ) 15263 15361 ) 15264 *52 9(Net15362 *528 (Net 15265 15363 uid 14177,0 15266 15364 decl (Decl … … 15278 15376 ) 15279 15377 xt "-172000,12000,-114000,12800" 15280 st "plllock_in : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked" 15281 ) 15282 ) 15283 *530 (SaComponent 15378 st "plllock_in : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked 15379 " 15380 ) 15381 ) 15382 *529 (SaComponent 15284 15383 uid 14417,0 15285 15384 optionalChildren [ 15286 *53 1(CptPort15385 *530 (CptPort 15287 15386 uid 14397,0 15288 15387 ps "OnEdgeStrategy" … … 15317 15416 ) 15318 15417 ) 15319 *53 2(CptPort15418 *531 (CptPort 15320 15419 uid 14401,0 15321 15420 ps "OnEdgeStrategy" … … 15350 15449 ) 15351 15450 ) 15352 *53 3(CptPort15451 *532 (CptPort 15353 15452 uid 14405,0 15354 15453 ps "OnEdgeStrategy" … … 15387 15486 ) 15388 15487 ) 15389 *53 4(CptPort15488 *533 (CptPort 15390 15489 uid 14409,0 15391 15490 ps "OnEdgeStrategy" … … 15423 15522 ) 15424 15523 ) 15425 *53 5(CptPort15524 *534 (CptPort 15426 15525 uid 14413,0 15427 15526 ps "OnEdgeStrategy" … … 15476 15575 stg "VerticalLayoutStrategy" 15477 15576 textVec [ 15478 *53 6(Text15577 *535 (Text 15479 15578 uid 14420,0 15480 15579 va (VaSet … … 15486 15585 tm "BdLibraryNameMgr" 15487 15586 ) 15488 *53 7(Text15587 *536 (Text 15489 15588 uid 14421,0 15490 15589 va (VaSet … … 15496 15595 tm "CptNameMgr" 15497 15596 ) 15498 *53 8(Text15597 *537 (Text 15499 15598 uid 14422,0 15500 15599 va (VaSet … … 15544 15643 archFileType "UNKNOWN" 15545 15644 ) 15546 *53 9(Net15645 *538 (Net 15547 15646 uid 14477,0 15548 15647 decl (Decl … … 15561 15660 ) 15562 15661 xt "-172000,20800,-118500,21600" 15563 st "alarm_refclk_too_high : std_logic := '0' -- default domino wave off" 15564 ) 15565 ) 15566 *540 (PortIoOut 15662 st "alarm_refclk_too_high : std_logic := '0' -- default domino wave off 15663 " 15664 ) 15665 ) 15666 *539 (PortIoOut 15567 15667 uid 14485,0 15568 15668 shape (CompositeShape … … 15608 15708 ) 15609 15709 ) 15610 *54 1(Net15710 *540 (Net 15611 15711 uid 14491,0 15612 15712 decl (Decl … … 15625 15725 ) 15626 15726 xt "-172000,21600,-118500,22400" 15627 st "alarm_refclk_too_low : std_logic := '0' -- default domino wave off" 15628 ) 15629 ) 15630 *542 (PortIoOut 15727 st "alarm_refclk_too_low : std_logic := '0' -- default domino wave off 15728 " 15729 ) 15730 ) 15731 *541 (PortIoOut 15631 15732 uid 14499,0 15632 15733 shape (CompositeShape … … 15672 15773 ) 15673 15774 ) 15674 *54 3(Net15775 *542 (Net 15675 15776 uid 14620,0 15676 15777 decl (Decl … … 15688 15789 ) 15689 15790 xt "-172000,23200,-126000,24000" 15690 st "counter_result : std_logic_vector(11 downto 0) := (others => '0')" 15691 ) 15692 ) 15693 *544 (PortIoOut 15791 st "counter_result : std_logic_vector(11 downto 0) := (others => '0') 15792 " 15793 ) 15794 ) 15795 *543 (PortIoOut 15694 15796 uid 14628,0 15695 15797 shape (CompositeShape … … 15735 15837 ) 15736 15838 ) 15737 *54 5(MWC15839 *544 (MWC 15738 15840 uid 14991,0 15739 15841 optionalChildren [ 15740 *54 6(CptPort15842 *545 (CptPort 15741 15843 uid 14963,0 15742 15844 optionalChildren [ 15743 *54 7(Line15845 *546 (Line 15744 15846 uid 14967,0 15745 15847 layer 5 … … 15754 15856 ] 15755 15857 ) 15756 *54 8(Property15858 *547 (Property 15757 15859 uid 14968,0 15758 15860 pclass "_MW_GEOM_" … … 15802 15904 ) 15803 15905 ) 15804 *54 9(CptPort15906 *548 (CptPort 15805 15907 uid 14969,0 15806 15908 optionalChildren [ 15807 *5 50(Line15909 *549 (Line 15808 15910 uid 14973,0 15809 15911 layer 5 … … 15858 15960 ) 15859 15961 ) 15860 *55 1(CptPort15962 *550 (CptPort 15861 15963 uid 14974,0 15862 15964 optionalChildren [ 15863 *55 2(Line15965 *551 (Line 15864 15966 uid 14978,0 15865 15967 layer 5 … … 15914 16016 ) 15915 16017 ) 15916 *55 3(CommentGraphic16018 *552 (CommentGraphic 15917 16019 uid 14979,0 15918 16020 optionalChildren [ 15919 *55 4(Property16021 *553 (Property 15920 16022 uid 14981,0 15921 16023 pclass "_MW_GEOM_" … … 15941 16043 oxt "7000,10000,7000,10000" 15942 16044 ) 15943 *55 5(CommentGraphic16045 *554 (CommentGraphic 15944 16046 uid 14982,0 15945 16047 optionalChildren [ 15946 *55 6(Property16048 *555 (Property 15947 16049 uid 14984,0 15948 16050 pclass "_MW_GEOM_" … … 15968 16070 oxt "7000,6000,7000,6000" 15969 16071 ) 15970 *55 7(Grouping16072 *556 (Grouping 15971 16073 uid 14985,0 15972 16074 optionalChildren [ 15973 *55 8(CommentGraphic16075 *557 (CommentGraphic 15974 16076 uid 14987,0 15975 16077 shape (PolyLine2D … … 15992 16094 oxt "7000,6000,9000,10000" 15993 16095 ) 15994 *55 9(CommentGraphic16096 *558 (CommentGraphic 15995 16097 uid 14989,0 15996 16098 shape (Arc2D … … 16045 16147 stg "VerticalLayoutStrategy" 16046 16148 textVec [ 16047 *5 60(Text16149 *559 (Text 16048 16150 uid 14994,0 16049 16151 va (VaSet … … 16055 16157 blo "162500,76300" 16056 16158 ) 16057 *56 1(Text16159 *560 (Text 16058 16160 uid 14995,0 16059 16161 va (VaSet … … 16064 16166 blo "162500,77300" 16065 16167 ) 16066 *56 2(Text16168 *561 (Text 16067 16169 uid 14996,0 16068 16170 va (VaSet … … 16109 16211 ) 16110 16212 ) 16111 *56 3(MWC16213 *562 (MWC 16112 16214 uid 15036,0 16113 16215 optionalChildren [ 16114 *56 4(CptPort16216 *563 (CptPort 16115 16217 uid 15005,0 16116 16218 optionalChildren [ 16117 *56 5(Property16219 *564 (Property 16118 16220 uid 15009,0 16119 16221 pclass "_MW_GEOM_" … … 16121 16223 ptn "String" 16122 16224 ) 16123 *56 6(Line16225 *565 (Line 16124 16226 uid 15010,0 16125 16227 layer 5 … … 16176 16278 ) 16177 16279 ) 16178 *56 7(CommentGraphic16280 *566 (CommentGraphic 16179 16281 uid 15016,0 16180 16282 shape (Arc2D … … 16198 16300 oxt "110003,265000,112000,269000" 16199 16301 ) 16200 *56 8(CommentGraphic16302 *567 (CommentGraphic 16201 16303 uid 15018,0 16202 16304 shape (Arc2D … … 16220 16322 oxt "112005,265000,114000,269004" 16221 16323 ) 16222 *56 9(Grouping16324 *568 (Grouping 16223 16325 uid 15020,0 16224 16326 optionalChildren [ 16225 *5 70(CommentGraphic16327 *569 (CommentGraphic 16226 16328 uid 15022,0 16227 16329 optionalChildren [ 16228 *57 1(Property16330 *570 (Property 16229 16331 uid 15024,0 16230 16332 pclass "_MW_GEOM_" … … 16258 16360 oxt "110000,265000,113998,269000" 16259 16361 ) 16260 *57 2(CommentGraphic16362 *571 (CommentGraphic 16261 16363 uid 15025,0 16262 16364 optionalChildren [ 16263 *57 3(Property16365 *572 (Property 16264 16366 uid 15027,0 16265 16367 pclass "_MW_GEOM_" … … 16305 16407 oxt "110000,265000,114000,269000" 16306 16408 ) 16307 *57 4(CommentGraphic16409 *573 (CommentGraphic 16308 16410 uid 15028,0 16309 16411 shape (PolyLine2D … … 16325 16427 oxt "112000,265000,112000,265000" 16326 16428 ) 16327 *57 5(CommentGraphic16429 *574 (CommentGraphic 16328 16430 uid 15030,0 16329 16431 optionalChildren [ 16330 *57 6(Property16432 *575 (Property 16331 16433 uid 15032,0 16332 16434 pclass "_MW_GEOM_" … … 16353 16455 oxt "110000,269000,110000,269000" 16354 16456 ) 16355 *57 7(CommentGraphic16457 *576 (CommentGraphic 16356 16458 uid 15033,0 16357 16459 optionalChildren [ 16358 *57 8(Property16460 *577 (Property 16359 16461 uid 15035,0 16360 16462 pclass "_MW_GEOM_" … … 16381 16483 oxt "114000,269000,114000,269000" 16382 16484 ) 16383 *57 9(CptPort16485 *578 (CptPort 16384 16486 uid 15160,0 16385 16487 optionalChildren [ 16386 *5 80(Line16488 *579 (Line 16387 16489 uid 15164,0 16388 16490 sl 0 … … 16436 16538 ) 16437 16539 ) 16438 *58 1(CptPort16540 *580 (CptPort 16439 16541 uid 15165,0 16440 16542 optionalChildren [ 16441 *58 2(Line16543 *581 (Line 16442 16544 uid 15169,0 16443 16545 sl 0 … … 16511 16613 stg "VerticalLayoutStrategy" 16512 16614 textVec [ 16513 *58 3(Text16615 *582 (Text 16514 16616 uid 15039,0 16515 16617 va (VaSet … … 16521 16623 blo "148500,89300" 16522 16624 ) 16523 *58 4(Text16625 *583 (Text 16524 16626 uid 15040,0 16525 16627 va (VaSet … … 16530 16632 blo "148500,90300" 16531 16633 ) 16532 *58 5(Text16634 *584 (Text 16533 16635 uid 15041,0 16534 16636 va (VaSet … … 16575 16677 ) 16576 16678 ) 16577 *58 6(MWC16679 *585 (MWC 16578 16680 uid 15058,0 16579 16681 optionalChildren [ 16580 *58 7(CptPort16682 *586 (CptPort 16581 16683 uid 15045,0 16582 16684 optionalChildren [ 16583 *58 8(Line16685 *587 (Line 16584 16686 uid 15049,0 16585 16687 layer 5 … … 16643 16745 ) 16644 16746 ) 16645 *58 9(CptPort16747 *588 (CptPort 16646 16748 uid 15050,0 16647 16749 optionalChildren [ 16648 *5 90(Line16750 *589 (Line 16649 16751 uid 15054,0 16650 16752 layer 5 … … 16659 16761 ] 16660 16762 ) 16661 *59 1(Circle16763 *590 (Circle 16662 16764 uid 15055,0 16663 16765 va (VaSet … … 16721 16823 ) 16722 16824 ) 16723 *59 2(CommentGraphic16825 *591 (CommentGraphic 16724 16826 uid 15056,0 16725 16827 shape (CustomPolygon … … 16763 16865 stg "VerticalLayoutStrategy" 16764 16866 textVec [ 16765 *59 3(Text16867 *592 (Text 16766 16868 uid 15061,0 16767 16869 va (VaSet … … 16773 16875 blo "155350,77900" 16774 16876 ) 16775 *59 4(Text16877 *593 (Text 16776 16878 uid 15062,0 16777 16879 va (VaSet … … 16782 16884 blo "155350,78900" 16783 16885 ) 16784 *59 5(Text16886 *594 (Text 16785 16887 uid 15063,0 16786 16888 va (VaSet … … 16827 16929 ) 16828 16930 ) 16829 *59 6(Net16931 *595 (Net 16830 16932 uid 15077,0 16831 16933 decl (Decl … … 16844 16946 ) 16845 16947 xt "-172000,63600,-115000,64400" 16846 st "SIGNAL denable_prim : std_logic := '0' -- default domino wave off" 16847 ) 16848 ) 16849 *597 (Net 16948 st "SIGNAL denable_prim : std_logic := '0' -- default domino wave off 16949 " 16950 ) 16951 ) 16952 *596 (Net 16850 16953 uid 15079,0 16851 16954 decl (Decl … … 16864 16967 ) 16865 16968 xt "-172000,64400,-115000,65200" 16866 st "SIGNAL din1 : std_logic := '0' -- default domino wave off" 16867 ) 16868 ) 16869 *598 (Net 16969 st "SIGNAL din1 : std_logic := '0' -- default domino wave off 16970 " 16971 ) 16972 ) 16973 *597 (Net 16870 16974 uid 15126,0 16871 16975 decl (Decl … … 16884 16988 ) 16885 16989 xt "-172000,62800,-115000,63600" 16886 st "SIGNAL denable_inhibit : std_logic := '0' -- default domino wave off" 16990 st "SIGNAL denable_inhibit : std_logic := '0' -- default domino wave off 16991 " 16992 ) 16993 ) 16994 *598 (Net 16995 uid 15492,0 16996 decl (Decl 16997 n "trigger_out" 16998 t "std_logic" 16999 o 123 17000 suid 301,0 17001 i "'0'" 17002 ) 17003 declText (MLText 17004 uid 15493,0 17005 va (VaSet 17006 font "Courier New,8,0" 17007 ) 17008 xt "-172000,99600,-128500,100400" 17009 st "SIGNAL trigger_out : std_logic := '0' 17010 " 16887 17011 ) 16888 17012 ) … … 17479 17603 lineWidth 2 17480 17604 ) 17481 xt "-40250,6 8000,-21750,71000"17482 pts [ 17483 "-40250,6 8000"17484 "-36000,6 8000"17485 "-36000,7 1000"17486 "-21750,7 1000"17605 xt "-40250,69000,-21750,70000" 17606 pts [ 17607 "-40250,69000" 17608 "-36000,69000" 17609 "-36000,70000" 17610 "-21750,70000" 17487 17611 ] 17488 17612 ) … … 17518 17642 lineWidth 2 17519 17643 ) 17520 xt "750,66000,31250,73000" 17521 pts [ 17522 "31250,73000" 17523 "27000,73000" 17524 "27000,66000" 17525 "750,66000" 17644 xt "750,71000,27250,71000" 17645 pts [ 17646 "27250,71000" 17647 "750,71000" 17526 17648 ] 17527 17649 ) … … 17542 17664 va (VaSet 17543 17665 ) 17544 xt " 2000,65000,18700,66000"17666 xt "1000,70000,17700,71000" 17545 17667 st "ram_start_addr : (RAMADDRWIDTH64b-1:0)" 17546 blo " 2000,65800"17668 blo "1000,70800" 17547 17669 tm "WireNameMgr" 17548 17670 ) … … 17557 17679 vasetType 3 17558 17680 ) 17559 xt "63750,70000,87250,71000" 17560 pts [ 17561 "63750,71000" 17562 "78000,71000" 17563 "78000,70000" 17564 "87250,70000" 17681 xt "59750,71000,87250,71000" 17682 pts [ 17683 "59750,71000" 17684 "87250,71000" 17565 17685 ] 17566 17686 ) … … 17580 17700 va (VaSet 17581 17701 ) 17582 xt "6 4000,70000,67400,71000"17702 xt "60000,70000,63400,71000" 17583 17703 st "wiz_busy" 17584 blo "6 4000,70800"17704 blo "60000,70800" 17585 17705 tm "WireNameMgr" 17586 17706 ) … … 17595 17715 vasetType 3 17596 17716 ) 17597 xt "63750,71000,87250,72000" 17598 pts [ 17599 "63750,72000" 17600 "84000,72000" 17601 "84000,71000" 17602 "87250,71000" 17717 xt "59750,72000,87250,72000" 17718 pts [ 17719 "59750,72000" 17720 "87250,72000" 17603 17721 ] 17604 17722 ) … … 17618 17736 va (VaSet 17619 17737 ) 17620 xt "6 4000,71000,69100,72000"17738 xt "60000,71000,65100,72000" 17621 17739 st "wiz_write_ea" 17622 blo "6 4000,71800"17740 blo "60000,71800" 17623 17741 tm "WireNameMgr" 17624 17742 ) … … 17634 17752 lineWidth 2 17635 17753 ) 17636 xt "63750,72000,87250,79000" 17637 pts [ 17638 "63750,73000" 17639 "67000,73000" 17640 "67000,79000" 17641 "85000,79000" 17642 "85000,72000" 17643 "87250,72000" 17754 xt "59750,73000,87250,73000" 17755 pts [ 17756 "59750,73000" 17757 "87250,73000" 17644 17758 ] 17645 17759 ) … … 17660 17774 va (VaSet 17661 17775 ) 17662 xt "6 4000,72000,73400,73000"17776 xt "60000,72000,69400,73000" 17663 17777 st "wiz_write_length : (16:0)" 17664 blo "6 4000,72800"17778 blo "60000,72800" 17665 17779 tm "WireNameMgr" 17666 17780 ) … … 17676 17790 lineWidth 2 17677 17791 ) 17678 xt "63750,73000,87250,74000" 17679 pts [ 17680 "63750,74000" 17681 "84000,74000" 17682 "84000,73000" 17683 "87250,73000" 17792 xt "59750,74000,87250,74000" 17793 pts [ 17794 "59750,74000" 17795 "87250,74000" 17684 17796 ] 17685 17797 ) … … 17700 17812 va (VaSet 17701 17813 ) 17702 xt "6 4000,73000,82800,74000"17814 xt "60000,73000,78800,74000" 17703 17815 st "wiz_ram_start_addr : (RAMADDRWIDTH64b+1:0)" 17704 blo "6 4000,73800"17816 blo "60000,73800" 17705 17817 tm "WireNameMgr" 17706 17818 ) … … 17716 17828 lineWidth 2 17717 17829 ) 17718 xt "63750,74000,87250,80000" 17719 pts [ 17720 "63750,75000" 17721 "66000,75000" 17722 "66000,80000" 17723 "86000,80000" 17724 "86000,74000" 17725 "87250,74000" 17830 xt "59750,75000,87250,75000" 17831 pts [ 17832 "59750,75000" 17833 "87250,75000" 17726 17834 ] 17727 17835 ) … … 17742 17850 va (VaSet 17743 17851 ) 17744 xt "6 4000,74000,75800,75000"17852 xt "60000,74000,71800,75000" 17745 17853 st "wiz_number_of_channels : (3:0)" 17746 blo "6 4000,74800"17854 blo "60000,74800" 17747 17855 tm "WireNameMgr" 17748 17856 ) … … 17757 17865 vasetType 3 17758 17866 ) 17759 xt "63750,75000,87250,76000" 17760 pts [ 17761 "63750,76000" 17762 "84000,76000" 17763 "84000,75000" 17764 "87250,75000" 17867 xt "59750,76000,87250,76000" 17868 pts [ 17869 "59750,76000" 17870 "87250,76000" 17765 17871 ] 17766 17872 ) … … 17780 17886 va (VaSet 17781 17887 ) 17782 xt "6 4000,75000,69500,76000"17888 xt "60000,75000,65500,76000" 17783 17889 st "wiz_write_end" 17784 blo "6 4000,75800"17890 blo "60000,75800" 17785 17891 tm "WireNameMgr" 17786 17892 ) … … 17795 17901 vasetType 3 17796 17902 ) 17797 xt "63750,76000,87250,77000" 17798 pts [ 17799 "63750,77000" 17800 "71000,77000" 17801 "71000,76000" 17802 "87250,76000" 17903 xt "59750,77000,87250,77000" 17904 pts [ 17905 "59750,77000" 17906 "87250,77000" 17803 17907 ] 17804 17908 ) … … 17818 17922 va (VaSet 17819 17923 ) 17820 xt "6 4000,76000,70600,77000"17924 xt "60000,76000,66600,77000" 17821 17925 st "wiz_write_header" 17822 blo "6 4000,76800"17926 blo "60000,76800" 17823 17927 tm "WireNameMgr" 17824 17928 ) … … 17833 17937 vasetType 3 17834 17938 ) 17835 xt "750,67000,31250,74000" 17836 pts [ 17837 "750,67000" 17838 "26000,67000" 17839 "26000,74000" 17840 "31250,74000" 17939 xt "750,72000,27250,72000" 17940 pts [ 17941 "750,72000" 17942 "27250,72000" 17841 17943 ] 17842 17944 ) … … 17856 17958 va (VaSet 17857 17959 ) 17858 xt " 2000,66000,7300,67000"17960 xt "1000,71000,6300,72000" 17859 17961 st "ram_write_ea" 17860 blo " 2000,66800"17962 blo "1000,71800" 17861 17963 tm "WireNameMgr" 17862 17964 ) … … 17871 17973 vasetType 3 17872 17974 ) 17873 xt "750,68000,31250,75000" 17874 pts [ 17875 "750,68000" 17876 "25000,68000" 17877 "25000,75000" 17878 "31250,75000" 17975 xt "750,73000,27250,73000" 17976 pts [ 17977 "750,73000" 17978 "27250,73000" 17879 17979 ] 17880 17980 ) … … 17894 17994 va (VaSet 17895 17995 ) 17896 xt " 2000,67000,8300,68000"17996 xt "1000,72000,7300,73000" 17897 17997 st "ram_write_ready" 17898 blo " 2000,67800"17998 blo "1000,72800" 17899 17999 tm "WireNameMgr" 17900 18000 ) … … 17909 18009 vasetType 3 17910 18010 ) 17911 xt "750,73000,31250,78000" 17912 pts [ 17913 "750,73000" 17914 "23000,73000" 17915 "23000,78000" 17916 "31250,78000" 18011 xt "750,76000,27250,76000" 18012 pts [ 18013 "750,76000" 18014 "27250,76000" 17917 18015 ] 17918 18016 ) … … 17933 18031 va (VaSet 17934 18032 ) 17935 xt "1000,7 2000,5800,73000"18033 xt "1000,75000,5800,76000" 17936 18034 st "config_start" 17937 blo "1000,7 2800"18035 blo "1000,75800" 17938 18036 tm "WireNameMgr" 17939 18037 ) … … 17948 18046 vasetType 3 17949 18047 ) 17950 xt "750,75000,31250,80000" 17951 pts [ 17952 "750,75000" 17953 "21000,75000" 17954 "21000,80000" 17955 "31250,80000" 18048 xt "750,78000,27250,78000" 18049 pts [ 18050 "750,78000" 18051 "27250,78000" 17956 18052 ] 17957 18053 ) … … 17971 18067 va (VaSet 17972 18068 ) 17973 xt "1000,7 4000,6100,75000"18069 xt "1000,77000,6100,78000" 17974 18070 st "config_ready" 17975 blo "1000,7 4800"18071 blo "1000,77800" 17976 18072 tm "WireNameMgr" 17977 18073 ) … … 17986 18082 vasetType 3 17987 18083 ) 17988 xt "750,77000,31250,81000" 17989 pts [ 17990 "750,77000" 17991 "20000,77000" 17992 "20000,81000" 17993 "31250,81000" 18084 xt "750,79000,27250,79000" 18085 pts [ 18086 "750,79000" 18087 "27250,79000" 17994 18088 ] 17995 18089 ) … … 18009 18103 va (VaSet 18010 18104 ) 18011 xt "1000,7 6000,4000,77000"18105 xt "1000,78000,4000,79000" 18012 18106 st "roi_max" 18013 blo "1000,7 6800"18107 blo "1000,78800" 18014 18108 tm "WireNameMgr" 18015 18109 ) … … 18025 18119 lineWidth 2 18026 18120 ) 18027 xt "750,78000,31250,82000" 18028 pts [ 18029 "750,78000" 18030 "19000,78000" 18031 "19000,82000" 18032 "31250,82000" 18121 xt "750,80000,27250,80000" 18122 pts [ 18123 "750,80000" 18124 "27250,80000" 18033 18125 ] 18034 18126 ) … … 18049 18141 va (VaSet 18050 18142 ) 18051 xt "1000,7 7000,10100,78000"18143 xt "1000,79000,10100,80000" 18052 18144 st "package_length : (15:0)" 18053 blo "1000,7 7800"18145 blo "1000,79800" 18054 18146 tm "WireNameMgr" 18055 18147 ) … … 19238 19330 vasetType 3 19239 19331 ) 19240 xt "18000,8 8000,31250,88000"19332 xt "18000,86000,27250,88000" 19241 19333 pts [ 19242 19334 "18000,88000" 19243 "31250,88000" 19335 "24000,88000" 19336 "24000,86000" 19337 "27250,86000" 19244 19338 ] 19245 19339 ) … … 19259 19353 va (VaSet 19260 19354 ) 19261 xt "2 8000,87000,31400,88000"19355 xt "24000,85000,27400,86000" 19262 19356 st "roi_array" 19263 blo "2 8000,87800"19357 blo "24000,85800" 19264 19358 tm "WireNameMgr" 19265 19359 ) … … 19531 19625 optionalChildren [ 19532 19626 &651 19533 *672 (BdJunction19534 uid 6086,019535 ps "OnConnectorStrategy"19536 shape (Circle19537 uid 6087,019538 va (VaSet19539 vasetType 119540 )19541 xt "27600,46600,28400,47400"19542 radius 40019543 )19544 )19545 19627 ] 19546 19628 shape (OrthoPolyLine … … 19584 19666 on &188 19585 19667 ) 19586 *67 3(Wire19668 *672 (Wire 19587 19669 uid 5626,0 19588 19670 shape (OrthoPolyLine … … 19620 19702 on &266 19621 19703 ) 19622 *67 4(Wire19704 *673 (Wire 19623 19705 uid 5634,0 19624 19706 shape (OrthoPolyLine … … 19658 19740 on &265 19659 19741 ) 19660 *67 5(Wire19742 *674 (Wire 19661 19743 uid 5646,0 19662 19744 shape (OrthoPolyLine … … 19694 19776 on &185 19695 19777 ) 19696 *67 6(Wire19778 *675 (Wire 19697 19779 uid 5745,0 19698 19780 shape (OrthoPolyLine … … 19732 19814 on &276 19733 19815 ) 19734 *67 7(Wire19816 *676 (Wire 19735 19817 uid 5805,0 19736 19818 shape (OrthoPolyLine … … 19766 19848 on &187 19767 19849 ) 19768 *67 8(Wire19850 *677 (Wire 19769 19851 uid 5813,0 19770 19852 shape (OrthoPolyLine … … 19804 19886 on &293 19805 19887 ) 19806 *67 9(Wire19888 *678 (Wire 19807 19889 uid 5821,0 19808 19890 shape (OrthoPolyLine … … 19842 19924 on &294 19843 19925 ) 19844 *6 80(Wire19926 *679 (Wire 19845 19927 uid 5829,0 19846 19928 shape (OrthoPolyLine … … 19880 19962 on &295 19881 19963 ) 19882 *68 1(Wire19964 *680 (Wire 19883 19965 uid 5837,0 19884 19966 shape (OrthoPolyLine … … 19920 20002 on &296 19921 20003 ) 19922 *68 2(Wire20004 *681 (Wire 19923 20005 uid 5950,0 19924 20006 shape (OrthoPolyLine … … 19958 20040 on &301 19959 20041 ) 19960 *68 3(Wire20042 *682 (Wire 19961 20043 uid 5962,0 19962 20044 shape (OrthoPolyLine … … 19996 20078 on &302 19997 20079 ) 19998 *68 4(Wire20080 *683 (Wire 19999 20081 uid 6002,0 20000 20082 shape (OrthoPolyLine … … 20034 20116 on &304 20035 20117 ) 20036 *68 5(Wire20118 *684 (Wire 20037 20119 uid 6008,0 20038 20120 shape (OrthoPolyLine … … 20072 20154 on &303 20073 20155 ) 20074 *68 6(Wire20156 *685 (Wire 20075 20157 uid 6018,0 20076 20158 shape (OrthoPolyLine … … 20079 20161 vasetType 3 20080 20162 ) 20081 xt "750,74000,31250,79000" 20082 pts [ 20083 "750,74000" 20084 "22000,74000" 20085 "22000,79000" 20086 "31250,79000" 20163 xt "750,77000,27250,77000" 20164 pts [ 20165 "750,77000" 20166 "27250,77000" 20087 20167 ] 20088 20168 ) … … 20102 20182 va (VaSet 20103 20183 ) 20104 xt "1000,7 3000,8200,74000"20184 xt "1000,76000,8200,77000" 20105 20185 st "config_started_mm" 20106 blo "1000,7 3800"20186 blo "1000,76800" 20107 20187 tm "WireNameMgr" 20108 20188 ) … … 20110 20190 on &305 20111 20191 ) 20112 *68 7(Wire20192 *686 (Wire 20113 20193 uid 6064,0 20114 20194 shape (OrthoPolyLine … … 20145 20225 on &258 20146 20226 ) 20147 *68 8(Wire20227 *687 (Wire 20148 20228 uid 6072,0 20149 20229 shape (OrthoPolyLine … … 20184 20264 on &188 20185 20265 ) 20186 *689 (Wire 20187 uid 6082,0 20188 shape (OrthoPolyLine 20189 uid 6083,0 20190 va (VaSet 20191 vasetType 3 20192 lineColor "0,32896,0" 20193 ) 20194 xt "28000,47000,31250,71000" 20195 pts [ 20196 "31250,71000" 20197 "28000,71000" 20198 "28000,47000" 20199 ] 20200 ) 20201 start &134 20202 end &672 20203 sat 32 20204 eat 32 20205 stc 0 20206 st 0 20207 sf 1 20208 si 0 20209 tg (WTG 20210 uid 6084,0 20211 ps "ConnStartEndStrategy" 20212 stg "STSignalDisplayStrategy" 20213 f (Text 20214 uid 6085,0 20215 va (VaSet 20216 ) 20217 xt "28000,70000,31100,71000" 20218 st "CLK_25" 20219 blo "28000,70800" 20220 tm "WireNameMgr" 20221 ) 20222 ) 20223 on &188 20224 ) 20225 *690 (Wire 20266 *688 (Wire 20226 20267 uid 6160,0 20227 20268 shape (OrthoPolyLine … … 20261 20302 on &306 20262 20303 ) 20263 *6 91(Wire20304 *689 (Wire 20264 20305 uid 6276,0 20265 20306 shape (OrthoPolyLine … … 20268 20309 vasetType 3 20269 20310 ) 20270 xt "-61000,6 7000,-52750,67000"20271 pts [ 20272 "-61000,6 7000"20273 "-52750,6 7000"20311 xt "-61000,68000,-52750,68000" 20312 pts [ 20313 "-61000,68000" 20314 "-52750,68000" 20274 20315 ] 20275 20316 ) … … 20287 20328 va (VaSet 20288 20329 ) 20289 xt "-58000,6 6000,-53500,67000"20330 xt "-58000,67000,-53500,68000" 20290 20331 st "CLK_25_PS" 20291 blo "-58000,6 6800"20332 blo "-58000,67800" 20292 20333 tm "WireNameMgr" 20293 20334 ) … … 20295 20336 on &185 20296 20337 ) 20297 *69 2(Wire20338 *690 (Wire 20298 20339 uid 6362,0 20299 20340 shape (OrthoPolyLine … … 20308 20349 ] 20309 20350 ) 20310 start &54 620351 start &545 20311 20352 end &309 20312 20353 ss 0 … … 20334 20375 on &308 20335 20376 ) 20336 *69 3(Wire20377 *691 (Wire 20337 20378 uid 6452,0 20338 20379 shape (OrthoPolyLine … … 20370 20411 on &310 20371 20412 ) 20372 *69 4(Wire20413 *692 (Wire 20373 20414 uid 6540,0 20374 20415 shape (OrthoPolyLine … … 20384 20425 ) 20385 20426 start &315 20386 end &47 720427 end &476 20387 20428 sat 32 20388 20429 eat 32 … … 20407 20448 on &329 20408 20449 ) 20409 *69 5(Wire20450 *693 (Wire 20410 20451 uid 6548,0 20411 20452 shape (OrthoPolyLine … … 20444 20485 on &310 20445 20486 ) 20446 *69 6(Wire20487 *694 (Wire 20447 20488 uid 8416,0 20448 20489 shape (OrthoPolyLine … … 20451 20492 vasetType 3 20452 20493 ) 20453 xt "63750,77000,87250,78000" 20454 pts [ 20455 "63750,78000" 20456 "84000,78000" 20457 "84000,77000" 20458 "87250,77000" 20494 xt "59750,78000,87250,78000" 20495 pts [ 20496 "59750,78000" 20497 "87250,78000" 20459 20498 ] 20460 20499 ) … … 20474 20513 va (VaSet 20475 20514 ) 20476 xt "6 4000,77000,67000,78000"20515 xt "60000,77000,63000,78000" 20477 20516 st "wiz_ack" 20478 blo "6 4000,77800"20517 blo "60000,77800" 20479 20518 tm "WireNameMgr" 20480 20519 ) … … 20482 20521 on &341 20483 20522 ) 20484 *69 7(Wire20523 *695 (Wire 20485 20524 uid 8732,0 20486 20525 shape (OrthoPolyLine … … 20520 20559 on &360 20521 20560 ) 20522 *69 8(Wire20561 *696 (Wire 20523 20562 uid 8738,0 20524 20563 shape (OrthoPolyLine … … 20556 20595 on &361 20557 20596 ) 20558 *69 9(Wire20597 *697 (Wire 20559 20598 uid 8752,0 20560 20599 shape (OrthoPolyLine … … 20591 20630 on &361 20592 20631 ) 20593 * 700(Wire20632 *698 (Wire 20594 20633 uid 9006,0 20595 20634 shape (OrthoPolyLine … … 20629 20668 on &362 20630 20669 ) 20631 * 701(Wire20670 *699 (Wire 20632 20671 uid 9233,0 20633 20672 shape (OrthoPolyLine … … 20664 20703 on &376 20665 20704 ) 20666 *70 2(Wire20705 *700 (Wire 20667 20706 uid 9241,0 20668 20707 shape (OrthoPolyLine … … 20699 20738 on &377 20700 20739 ) 20701 *70 3(Wire20740 *701 (Wire 20702 20741 uid 9253,0 20703 20742 shape (OrthoPolyLine … … 20733 20772 on &376 20734 20773 ) 20735 *70 4(Wire20774 *702 (Wire 20736 20775 uid 9261,0 20737 20776 shape (OrthoPolyLine … … 20767 20806 on &377 20768 20807 ) 20769 *70 5(Wire20808 *703 (Wire 20770 20809 uid 9943,0 20771 20810 shape (OrthoPolyLine … … 20802 20841 on &378 20803 20842 ) 20804 *70 6(Wire20843 *704 (Wire 20805 20844 uid 9951,0 20806 20845 shape (OrthoPolyLine … … 20837 20876 on &379 20838 20877 ) 20839 *70 7(Wire20878 *705 (Wire 20840 20879 uid 10010,0 20841 20880 shape (OrthoPolyLine … … 20875 20914 on &398 20876 20915 ) 20877 *70 8(Wire20916 *706 (Wire 20878 20917 uid 10018,0 20879 20918 shape (OrthoPolyLine … … 20911 20950 on &379 20912 20951 ) 20913 *70 9(Wire20952 *707 (Wire 20914 20953 uid 10036,0 20915 20954 shape (OrthoPolyLine … … 20945 20984 on &378 20946 20985 ) 20947 *7 10(Wire20986 *708 (Wire 20948 20987 uid 10194,0 20949 20988 shape (OrthoPolyLine … … 20985 21024 on &399 20986 21025 ) 20987 *7 11(Wire21026 *709 (Wire 20988 21027 uid 10202,0 20989 21028 shape (OrthoPolyLine … … 21023 21062 on &400 21024 21063 ) 21025 *71 2(Wire21064 *710 (Wire 21026 21065 uid 10266,0 21027 21066 shape (OrthoPolyLine … … 21056 21095 ) 21057 21096 ) 21058 on &49 921059 ) 21060 *71 3(Wire21097 on &498 21098 ) 21099 *711 (Wire 21061 21100 uid 10298,0 21062 21101 shape (OrthoPolyLine … … 21094 21133 on &402 21095 21134 ) 21096 *71 4(Wire21135 *712 (Wire 21097 21136 uid 10304,0 21098 21137 shape (OrthoPolyLine … … 21130 21169 on &403 21131 21170 ) 21132 *71 5(Wire21171 *713 (Wire 21133 21172 uid 10310,0 21134 21173 shape (OrthoPolyLine … … 21166 21205 on &404 21167 21206 ) 21168 *71 6(Wire21207 *714 (Wire 21169 21208 uid 10316,0 21170 21209 shape (OrthoPolyLine … … 21204 21243 on &405 21205 21244 ) 21206 *71 7(Wire21245 *715 (Wire 21207 21246 uid 10322,0 21208 21247 shape (OrthoPolyLine … … 21242 21281 on &406 21243 21282 ) 21244 *71 8(Wire21283 *716 (Wire 21245 21284 uid 10431,0 21246 21285 shape (OrthoPolyLine … … 21279 21318 on &401 21280 21319 ) 21281 *719 (Wire 21282 uid 10439,0 21283 optionalChildren [ 21284 *720 (BdJunction 21285 uid 12639,0 21286 ps "OnConnectorStrategy" 21287 shape (Circle 21288 uid 12640,0 21289 va (VaSet 21290 vasetType 1 21291 ) 21292 xt "-54400,71600,-53600,72400" 21293 radius 400 21294 ) 21295 ) 21296 ] 21297 shape (OrthoPolyLine 21298 uid 10440,0 21299 va (VaSet 21300 vasetType 3 21301 ) 21302 xt "-54000,68000,-21750,72000" 21303 pts [ 21304 "-21750,72000" 21305 "-54000,72000" 21306 "-54000,68000" 21307 "-52750,68000" 21308 ] 21309 ) 21310 start &30 21311 end &125 21312 sat 32 21313 eat 32 21314 st 0 21315 sf 1 21316 si 0 21317 tg (WTG 21318 uid 10441,0 21319 ps "ConnStartEndStrategy" 21320 stg "STSignalDisplayStrategy" 21321 f (Text 21322 uid 10442,0 21323 va (VaSet 21324 ) 21325 xt "-25750,71000,-21150,72000" 21326 st "trigger_out" 21327 blo "-25750,71800" 21328 tm "WireNameMgr" 21329 ) 21330 ) 21331 on &431 21332 ) 21333 *721 (Wire 21320 *717 (Wire 21334 21321 uid 10467,0 21335 21322 shape (OrthoPolyLine … … 21338 21325 vasetType 3 21339 21326 ) 21340 xt "750,69000,31250,76000" 21341 pts [ 21342 "31250,76000" 21343 "24000,76000" 21344 "24000,69000" 21345 "750,69000" 21327 xt "750,74000,27250,74000" 21328 pts [ 21329 "27250,74000" 21330 "750,74000" 21346 21331 ] 21347 21332 ) … … 21362 21347 va (VaSet 21363 21348 ) 21364 xt " 2000,68000,9800,69000"21349 xt "1000,73000,8800,74000" 21365 21350 st "ram_write_ready_ack" 21366 blo " 2000,68800"21351 blo "1000,73800" 21367 21352 tm "WireNameMgr" 21368 21353 ) 21369 21354 ) 21370 on &43 221371 ) 21372 *7 22(Wire21355 on &431 21356 ) 21357 *718 (Wire 21373 21358 uid 10629,0 21374 21359 shape (OrthoPolyLine … … 21403 21388 ) 21404 21389 ) 21405 on &43 321406 ) 21407 *7 23(Wire21390 on &432 21391 ) 21392 *719 (Wire 21408 21393 uid 10637,0 21409 21394 shape (OrthoPolyLine … … 21438 21423 ) 21439 21424 ) 21440 on &43 421441 ) 21442 *72 4(Wire21425 on &433 21426 ) 21427 *720 (Wire 21443 21428 uid 10685,0 21444 21429 shape (OrthoPolyLine … … 21453 21438 ] 21454 21439 ) 21455 end &44 721440 end &446 21456 21441 sat 16 21457 21442 eat 32 … … 21473 21458 ) 21474 21459 ) 21475 on &43 421476 ) 21477 *72 5(Wire21460 on &433 21461 ) 21462 *721 (Wire 21478 21463 uid 10691,0 21479 21464 shape (OrthoPolyLine … … 21488 21473 ] 21489 21474 ) 21490 end &44 821475 end &447 21491 21476 sat 16 21492 21477 eat 32 … … 21508 21493 ) 21509 21494 ) 21510 on &43 321511 ) 21512 *72 6(Wire21495 on &432 21496 ) 21497 *722 (Wire 21513 21498 uid 10699,0 21514 21499 shape (OrthoPolyLine … … 21524 21509 ] 21525 21510 ) 21526 end &44 221511 end &441 21527 21512 sat 16 21528 21513 eat 32 … … 21546 21531 on &187 21547 21532 ) 21548 *72 7(Wire21533 *723 (Wire 21549 21534 uid 10707,0 21550 21535 shape (OrthoPolyLine … … 21559 21544 ] 21560 21545 ) 21561 end &44 621546 end &445 21562 21547 sat 16 21563 21548 eat 32 … … 21579 21564 ) 21580 21565 ) 21581 on &45 321582 ) 21583 *72 8(Wire21566 on &452 21567 ) 21568 *724 (Wire 21584 21569 uid 10723,0 21585 21570 shape (OrthoPolyLine … … 21594 21579 ] 21595 21580 ) 21596 start &44 321597 end &43 621581 start &442 21582 end &435 21598 21583 sat 32 21599 21584 eat 32 … … 21617 21602 ) 21618 21603 ) 21619 on &43 521620 ) 21621 *72 9(Wire21604 on &434 21605 ) 21606 *725 (Wire 21622 21607 uid 10737,0 21623 21608 shape (OrthoPolyLine … … 21632 21617 ] 21633 21618 ) 21634 start &44 421635 end &43 821619 start &443 21620 end &437 21636 21621 sat 32 21637 21622 eat 32 … … 21655 21640 ) 21656 21641 ) 21657 on &43 721658 ) 21659 *7 30(Wire21642 on &436 21643 ) 21644 *726 (Wire 21660 21645 uid 10751,0 21661 21646 shape (OrthoPolyLine … … 21670 21655 ] 21671 21656 ) 21672 start &44 521673 end &4 4021657 start &444 21658 end &439 21674 21659 sat 32 21675 21660 eat 32 … … 21693 21678 ) 21694 21679 ) 21695 on &43 921696 ) 21697 *7 31(Wire21680 on &438 21681 ) 21682 *727 (Wire 21698 21683 uid 11405,0 21699 21684 shape (OrthoPolyLine … … 21729 21714 ) 21730 21715 ) 21731 on &45 321732 ) 21733 *7 32(Wire21716 on &452 21717 ) 21718 *728 (Wire 21734 21719 uid 11858,0 21735 21720 shape (OrthoPolyLine … … 21764 21749 ) 21765 21750 ) 21766 on &45 421767 ) 21768 *7 33(Wire21751 on &453 21752 ) 21753 *729 (Wire 21769 21754 uid 11952,0 21770 21755 shape (OrthoPolyLine … … 21779 21764 ] 21780 21765 ) 21781 end &46 121766 end &460 21782 21767 sat 16 21783 21768 eat 32 … … 21800 21785 ) 21801 21786 ) 21802 on &45 421803 ) 21804 *73 4(Wire21787 on &453 21788 ) 21789 *730 (Wire 21805 21790 uid 12306,0 21806 21791 shape (OrthoPolyLine … … 21816 21801 ) 21817 21802 start &411 21818 end &45 921803 end &458 21819 21804 sat 32 21820 21805 eat 32 … … 21838 21823 ) 21839 21824 ) 21840 on &473 21841 ) 21842 *735 (Wire 21843 uid 12635,0 21844 shape (OrthoPolyLine 21845 uid 12636,0 21846 va (VaSet 21847 vasetType 3 21848 ) 21849 xt "-55250,72000,-54000,72000" 21850 pts [ 21851 "-54000,72000" 21852 "-55250,72000" 21853 ] 21854 ) 21855 start &720 21856 end &476 21857 sat 32 21858 eat 32 21859 stc 0 21860 st 0 21861 sf 1 21862 si 0 21863 tg (WTG 21864 uid 12637,0 21865 ps "ConnStartEndStrategy" 21866 stg "STSignalDisplayStrategy" 21867 f (Text 21868 uid 12638,0 21869 va (VaSet 21870 ) 21871 xt "-54000,71000,-49400,72000" 21872 st "trigger_out" 21873 blo "-54000,71800" 21874 tm "WireNameMgr" 21875 ) 21876 ) 21877 on &431 21878 ) 21879 *736 (Wire 21825 on &472 21826 ) 21827 *731 (Wire 21880 21828 uid 12643,0 21881 21829 shape (OrthoPolyLine … … 21892 21840 ] 21893 21841 ) 21894 start &45 621895 end &47 521842 start &455 21843 end &474 21896 21844 sat 32 21897 21845 eat 32 … … 21915 21863 ) 21916 21864 ) 21917 on &48 421918 ) 21919 *73 7(Wire21865 on &483 21866 ) 21867 *732 (Wire 21920 21868 uid 12649,0 21921 21869 shape (OrthoPolyLine … … 21927 21875 pts [ 21928 21876 "-21750,74000" 21929 "-38000,74000"21930 21877 "-55250,74000" 21931 21878 ] 21932 21879 ) 21933 21880 start &66 21934 end &47 821881 end &477 21935 21882 sat 32 21936 21883 eat 32 … … 21952 21899 ) 21953 21900 ) 21954 on &48 521955 ) 21956 *73 8(Wire21901 on &484 21902 ) 21903 *733 (Wire 21957 21904 uid 12655,0 21958 21905 shape (OrthoPolyLine … … 21969 21916 ) 21970 21917 start &67 21971 end &47 921918 end &478 21972 21919 sat 32 21973 21920 eat 32 … … 21989 21936 ) 21990 21937 ) 21991 on &48 621992 ) 21993 *73 9(Wire21938 on &485 21939 ) 21940 *734 (Wire 21994 21941 uid 12687,0 21995 21942 shape (OrthoPolyLine … … 22007 21954 ] 22008 21955 ) 22009 end &4 8021956 end &479 22010 21957 sat 16 22011 21958 eat 32 … … 22029 21976 on &188 22030 21977 ) 22031 *7 40(Wire21978 *735 (Wire 22032 21979 uid 12707,0 22033 21980 shape (OrthoPolyLine … … 22042 21989 ] 22043 21990 ) 22044 start &44 922045 end &48 821991 start &448 21992 end &487 22046 21993 sat 32 22047 21994 eat 32 … … 22065 22012 ) 22066 22013 ) 22067 on &48 722068 ) 22069 *7 41(Wire22014 on &486 22015 ) 22016 *736 (Wire 22070 22017 uid 13143,0 22071 22018 shape (OrthoPolyLine … … 22074 22021 vasetType 3 22075 22022 ) 22076 xt " 63750,62000,69000,62000"22077 pts [ 22078 " 69000,62000"22079 " 63750,62000"22080 ] 22081 ) 22082 end &4 9022023 xt "72750,62000,78000,62000" 22024 pts [ 22025 "78000,62000" 22026 "72750,62000" 22027 ] 22028 ) 22029 end &489 22083 22030 sat 16 22084 22031 eat 32 … … 22094 22041 va (VaSet 22095 22042 ) 22096 xt " 65000,61000,68100,62000"22043 xt "74000,61000,77100,62000" 22097 22044 st "CLK_25" 22098 blo " 65000,61800"22045 blo "74000,61800" 22099 22046 tm "WireNameMgr" 22100 22047 ) … … 22102 22049 on &188 22103 22050 ) 22104 *7 42(Wire22051 *737 (Wire 22105 22052 uid 13159,0 22106 22053 shape (OrthoPolyLine … … 22109 22056 vasetType 3 22110 22057 ) 22111 xt " 63750,63000,87250,67000"22058 xt "72750,63000,87250,67000" 22112 22059 pts [ 22113 22060 "87250,67000" 22114 "7 9000,67000"22115 "7 9000,63000"22116 " 63750,63000"22061 "77000,67000" 22062 "77000,63000" 22063 "72750,63000" 22117 22064 ] 22118 22065 ) 22119 22066 start &114 22120 end &49 122067 end &490 22121 22068 sat 32 22122 22069 eat 32 … … 22138 22085 ) 22139 22086 ) 22140 on &49 722141 ) 22142 *7 43(Wire22087 on &496 22088 ) 22089 *738 (Wire 22143 22090 uid 13165,0 22144 22091 shape (OrthoPolyLine … … 22148 22095 lineWidth 2 22149 22096 ) 22150 xt " 63750,64000,87250,68000"22097 xt "72750,64000,87250,68000" 22151 22098 pts [ 22152 22099 "87250,68000" 22153 "7 8000,68000"22154 "7 8000,64000"22155 " 63750,64000"22100 "76000,68000" 22101 "76000,64000" 22102 "72750,64000" 22156 22103 ] 22157 22104 ) 22158 22105 start &115 22159 end &49 222106 end &491 22160 22107 sat 32 22161 22108 eat 32 … … 22178 22125 ) 22179 22126 ) 22180 on &49 822181 ) 22182 *7 44(Wire22127 on &497 22128 ) 22129 *739 (Wire 22183 22130 uid 13210,0 22184 22131 shape (OrthoPolyLine … … 22187 22134 vasetType 3 22188 22135 ) 22189 xt " 42000,62000,50250,62000"22190 pts [ 22191 "5 0250,62000"22192 " 42000,62000"22193 ] 22194 ) 22195 start &49 322196 end &50 222136 xt "54000,62000,59250,62000" 22137 pts [ 22138 "59250,62000" 22139 "54000,62000" 22140 ] 22141 ) 22142 start &492 22143 end &501 22197 22144 sat 32 22198 22145 eat 32 … … 22208 22155 va (VaSet 22209 22156 ) 22210 xt " 46250,61000,49450,62000"22157 xt "53250,61000,56450,62000" 22211 22158 st "trigger1" 22212 blo " 46250,61800"22159 blo "53250,61800" 22213 22160 tm "WireNameMgr" 22214 22161 ) 22215 22162 ) 22216 on & 50022217 ) 22218 *74 5(Wire22163 on &499 22164 ) 22165 *740 (Wire 22219 22166 uid 13216,0 22220 22167 shape (OrthoPolyLine … … 22223 22170 vasetType 3 22224 22171 ) 22225 xt " 42000,60000,45000,60000"22226 pts [ 22227 " 45000,60000"22228 " 42000,60000"22229 ] 22230 ) 22231 end &50 722172 xt "54000,60000,59000,60000" 22173 pts [ 22174 "59000,60000" 22175 "54000,60000" 22176 ] 22177 ) 22178 end &506 22232 22179 sat 16 22233 22180 eat 32 … … 22243 22190 uid 13221,0 22244 22191 va (VaSet 22245 isHidden 1 22246 ) 22247 xt "43000,59000,47800,60000" 22192 ) 22193 xt "54000,59000,58800,60000" 22248 22194 st "s_trigger_0" 22249 blo " 43000,59800"22195 blo "54000,59800" 22250 22196 tm "WireNameMgr" 22251 22197 ) 22252 22198 ) 22253 on &49 922254 ) 22255 *74 6(Wire22199 on &498 22200 ) 22201 *741 (Wire 22256 22202 uid 13224,0 22257 22203 shape (OrthoPolyLine … … 22260 22206 vasetType 3 22261 22207 ) 22262 xt " 33000,61000,36000,61000"22263 pts [ 22264 " 36000,61000"22265 " 33000,61000"22266 ] 22267 ) 22268 start &50 422208 xt "45000,61000,48000,61000" 22209 pts [ 22210 "48000,61000" 22211 "45000,61000" 22212 ] 22213 ) 22214 start &503 22269 22215 sat 32 22270 22216 eat 16 … … 22280 22226 uid 13229,0 22281 22227 va (VaSet 22282 isHidden 1 22283 ) 22284 xt "34000,60000,37600,61000" 22228 ) 22229 xt "45000,60000,48600,61000" 22285 22230 st "s_trigger" 22286 blo " 34000,60800"22231 blo "45000,60800" 22287 22232 tm "WireNameMgr" 22288 22233 ) … … 22290 22235 on &401 22291 22236 ) 22292 *74 7(Wire22237 *742 (Wire 22293 22238 uid 13695,0 22294 22239 shape (OrthoPolyLine … … 22304 22249 ] 22305 22250 ) 22306 start &52 422251 start &523 22307 22252 end &116 22308 22253 sat 32 … … 22327 22272 ) 22328 22273 ) 22329 on &52 522330 ) 22331 *74 8(Wire22274 on &524 22275 ) 22276 *743 (Wire 22332 22277 uid 13921,0 22333 22278 shape (OrthoPolyLine … … 22366 22311 on &71 22367 22312 ) 22368 *74 9(Wire22313 *744 (Wire 22369 22314 uid 13929,0 22370 22315 shape (OrthoPolyLine … … 22403 22348 on &122 22404 22349 ) 22405 *7 50(Wire22350 *745 (Wire 22406 22351 uid 14048,0 22407 22352 shape (OrthoPolyLine … … 22416 22361 ] 22417 22362 ) 22418 start &52 622419 end &53 222363 start &525 22364 end &531 22420 22365 sat 32 22421 22366 eat 32 … … 22438 22383 ) 22439 22384 ) 22440 on &52 722441 ) 22442 *7 51(Wire22385 on &526 22386 ) 22387 *746 (Wire 22443 22388 uid 14171,0 22444 22389 shape (OrthoPolyLine … … 22454 22399 ] 22455 22400 ) 22456 start &52 822401 start &527 22457 22402 sat 32 22458 22403 eat 16 … … 22476 22421 ) 22477 22422 ) 22478 on &52 922479 ) 22480 *7 52(Wire22423 on &528 22424 ) 22425 *747 (Wire 22481 22426 uid 14427,0 22482 22427 shape (OrthoPolyLine … … 22491 22436 ] 22492 22437 ) 22493 end &53 122438 end &530 22494 22439 sat 16 22495 22440 eat 32 … … 22513 22458 on &187 22514 22459 ) 22515 *7 53(Wire22460 *748 (Wire 22516 22461 uid 14479,0 22517 22462 shape (OrthoPolyLine … … 22526 22471 ] 22527 22472 ) 22528 start &53 422529 end &5 4022473 start &533 22474 end &539 22530 22475 sat 32 22531 22476 eat 32 … … 22549 22494 ) 22550 22495 ) 22551 on &53 922552 ) 22553 *7 54(Wire22496 on &538 22497 ) 22498 *749 (Wire 22554 22499 uid 14493,0 22555 22500 shape (OrthoPolyLine … … 22564 22509 ] 22565 22510 ) 22566 start &53 522567 end &54 222511 start &534 22512 end &541 22568 22513 sat 32 22569 22514 eat 32 … … 22587 22532 ) 22588 22533 ) 22589 on &54 122590 ) 22591 *75 5(Wire22534 on &540 22535 ) 22536 *750 (Wire 22592 22537 uid 14622,0 22593 22538 shape (OrthoPolyLine … … 22603 22548 ] 22604 22549 ) 22605 start &53 322606 end &54 422550 start &532 22551 end &543 22607 22552 sat 32 22608 22553 eat 32 … … 22627 22572 ) 22628 22573 ) 22629 on &54 322630 ) 22631 *75 6(Wire22574 on &542 22575 ) 22576 *751 (Wire 22632 22577 uid 15071,0 22633 22578 shape (OrthoPolyLine … … 22643 22588 ) 22644 22589 start &101 22645 end &54 922590 end &548 22646 22591 sat 32 22647 22592 eat 32 … … 22663 22608 ) 22664 22609 ) 22665 on &59 622666 ) 22667 *75 7(Wire22610 on &595 22611 ) 22612 *752 (Wire 22668 22613 uid 15081,0 22669 22614 shape (OrthoPolyLine … … 22678 22623 ] 22679 22624 ) 22680 start &55 122681 end &58 922625 start &550 22626 end &588 22682 22627 sat 32 22683 22628 eat 32 … … 22701 22646 ) 22702 22647 ) 22703 on &59 722704 ) 22705 *75 8(Wire22648 on &596 22649 ) 22650 *753 (Wire 22706 22651 uid 15122,0 22707 22652 shape (OrthoPolyLine … … 22717 22662 ] 22718 22663 ) 22719 start &58 722720 end &56 422664 start &586 22665 end &563 22721 22666 sat 32 22722 22667 eat 32 … … 22739 22684 ) 22740 22685 ) 22741 on &59 822742 ) 22743 *75 9(Wire22686 on &597 22687 ) 22688 *754 (Wire 22744 22689 uid 15130,0 22745 22690 shape (OrthoPolyLine … … 22754 22699 ] 22755 22700 ) 22756 end &57 922701 end &578 22757 22702 es 0 22758 22703 sat 16 … … 22777 22722 ) 22778 22723 ) 22779 on &54 122780 ) 22781 *7 60(Wire22724 on &540 22725 ) 22726 *755 (Wire 22782 22727 uid 15138,0 22783 22728 shape (OrthoPolyLine … … 22792 22737 ] 22793 22738 ) 22794 end &58 122739 end &580 22795 22740 es 0 22796 22741 sat 16 … … 22815 22760 ) 22816 22761 ) 22817 on &539 22762 on &538 22763 ) 22764 *756 (Wire 22765 uid 15379,0 22766 shape (OrthoPolyLine 22767 uid 15380,0 22768 va (VaSet 22769 vasetType 3 22770 ) 22771 xt "29000,64000,29000,67250" 22772 pts [ 22773 "29000,64000" 22774 "29000,67250" 22775 ] 22776 ) 22777 end &134 22778 sat 16 22779 eat 32 22780 st 0 22781 sf 1 22782 si 0 22783 tg (WTG 22784 uid 15383,0 22785 ps "ConnStartEndStrategy" 22786 stg "STSignalDisplayStrategy" 22787 f (Text 22788 uid 15384,0 22789 va (VaSet 22790 ) 22791 xt "29000,64000,32100,65000" 22792 st "CLK_25" 22793 blo "29000,64800" 22794 tm "WireNameMgr" 22795 ) 22796 ) 22797 on &188 22798 ) 22799 *757 (Wire 22800 uid 15494,0 22801 optionalChildren [ 22802 *758 (BdJunction 22803 uid 15502,0 22804 ps "OnConnectorStrategy" 22805 shape (Circle 22806 uid 15503,0 22807 va (VaSet 22808 vasetType 1 22809 ) 22810 xt "-54400,71600,-53600,72400" 22811 radius 400 22812 ) 22813 ) 22814 ] 22815 shape (OrthoPolyLine 22816 uid 15495,0 22817 va (VaSet 22818 vasetType 3 22819 ) 22820 xt "-55250,72000,-21750,72000" 22821 pts [ 22822 "-55250,72000" 22823 "-21750,72000" 22824 ] 22825 ) 22826 start &475 22827 end &30 22828 sat 32 22829 eat 32 22830 st 0 22831 sf 1 22832 si 0 22833 tg (WTG 22834 uid 15496,0 22835 ps "ConnStartEndStrategy" 22836 stg "STSignalDisplayStrategy" 22837 f (Text 22838 uid 15497,0 22839 va (VaSet 22840 ) 22841 xt "-53250,71000,-48650,72000" 22842 st "trigger_out" 22843 blo "-53250,71800" 22844 tm "WireNameMgr" 22845 ) 22846 ) 22847 on &598 22848 ) 22849 *759 (Wire 22850 uid 15498,0 22851 shape (OrthoPolyLine 22852 uid 15499,0 22853 va (VaSet 22854 vasetType 3 22855 ) 22856 xt "-54000,69000,-52750,72000" 22857 pts [ 22858 "-52750,69000" 22859 "-54000,69000" 22860 "-54000,72000" 22861 ] 22862 ) 22863 start &125 22864 end &758 22865 sat 32 22866 eat 32 22867 stc 0 22868 st 0 22869 sf 1 22870 si 0 22871 tg (WTG 22872 uid 15500,0 22873 ps "ConnStartEndStrategy" 22874 stg "STSignalDisplayStrategy" 22875 f (Text 22876 uid 15501,0 22877 va (VaSet 22878 ) 22879 xt "-58000,69000,-53400,70000" 22880 st "trigger_out" 22881 blo "-58000,69800" 22882 tm "WireNameMgr" 22883 ) 22884 ) 22885 on &598 22818 22886 ) 22819 22887 ] … … 22829 22897 color "26368,26368,26368" 22830 22898 ) 22831 packageList *76 1(PackageList22899 packageList *760 (PackageList 22832 22900 uid 41,0 22833 22901 stg "VerticalLayoutStrategy" 22834 22902 textVec [ 22835 *76 2(Text22903 *761 (Text 22836 22904 uid 42,0 22837 22905 va (VaSet … … 22842 22910 blo "-163000,-15200" 22843 22911 ) 22844 *76 3(MLText22912 *762 (MLText 22845 22913 uid 43,0 22846 22914 va (VaSet … … 22867 22935 stg "VerticalLayoutStrategy" 22868 22936 textVec [ 22869 *76 4(Text22937 *763 (Text 22870 22938 uid 45,0 22871 22939 va (VaSet … … 22877 22945 blo "20000,800" 22878 22946 ) 22879 *76 5(Text22947 *764 (Text 22880 22948 uid 46,0 22881 22949 va (VaSet … … 22887 22955 blo "20000,1800" 22888 22956 ) 22889 *76 6(MLText22957 *765 (MLText 22890 22958 uid 47,0 22891 22959 va (VaSet … … 22897 22965 tm "BdCompilerDirectivesTextMgr" 22898 22966 ) 22899 *76 7(Text22967 *766 (Text 22900 22968 uid 48,0 22901 22969 va (VaSet … … 22907 22975 blo "20000,4800" 22908 22976 ) 22909 *76 8(MLText22977 *767 (MLText 22910 22978 uid 49,0 22911 22979 va (VaSet … … 22915 22983 tm "BdCompilerDirectivesTextMgr" 22916 22984 ) 22917 *76 9(Text22985 *768 (Text 22918 22986 uid 50,0 22919 22987 va (VaSet … … 22925 22993 blo "20000,5800" 22926 22994 ) 22927 *7 70(MLText22995 *769 (MLText 22928 22996 uid 51,0 22929 22997 va (VaSet … … 22937 23005 ) 22938 23006 windowSize "0,0,1281,1024" 22939 viewArea "- 25598,42048,41245,97173"23007 viewArea "-65700,47500,1143,102625" 22940 23008 cachedDiagramExtent "-174000,-25425,428157,346294" 22941 23009 pageSetupInfo (PageSetupInfo … … 22963 23031 hasePageBreakOrigin 1 22964 23032 pageBreakOrigin "-73000,0" 22965 lastUid 15 275,023033 lastUid 15505,0 22966 23034 defaultCommentText (CommentText 22967 23035 shape (Rectangle … … 23025 23093 stg "VerticalLayoutStrategy" 23026 23094 textVec [ 23027 *77 1(Text23095 *770 (Text 23028 23096 va (VaSet 23029 23097 font "Arial,8,1" … … 23034 23102 tm "BdLibraryNameMgr" 23035 23103 ) 23036 *77 2(Text23104 *771 (Text 23037 23105 va (VaSet 23038 23106 font "Arial,8,1" … … 23043 23111 tm "BlkNameMgr" 23044 23112 ) 23045 *77 3(Text23113 *772 (Text 23046 23114 va (VaSet 23047 23115 font "Arial,8,1" … … 23094 23162 stg "VerticalLayoutStrategy" 23095 23163 textVec [ 23096 *77 4(Text23164 *773 (Text 23097 23165 va (VaSet 23098 23166 font "Arial,8,1" … … 23102 23170 blo "550,4300" 23103 23171 ) 23104 *77 5(Text23172 *774 (Text 23105 23173 va (VaSet 23106 23174 font "Arial,8,1" … … 23110 23178 blo "550,5300" 23111 23179 ) 23112 *77 6(Text23180 *775 (Text 23113 23181 va (VaSet 23114 23182 font "Arial,8,1" … … 23159 23227 stg "VerticalLayoutStrategy" 23160 23228 textVec [ 23161 *77 7(Text23229 *776 (Text 23162 23230 va (VaSet 23163 23231 font "Arial,8,1" … … 23168 23236 tm "BdLibraryNameMgr" 23169 23237 ) 23170 *77 8(Text23238 *777 (Text 23171 23239 va (VaSet 23172 23240 font "Arial,8,1" … … 23177 23245 tm "CptNameMgr" 23178 23246 ) 23179 *77 9(Text23247 *778 (Text 23180 23248 va (VaSet 23181 23249 font "Arial,8,1" … … 23231 23299 stg "VerticalLayoutStrategy" 23232 23300 textVec [ 23233 *7 80(Text23301 *779 (Text 23234 23302 va (VaSet 23235 23303 font "Arial,8,1" … … 23239 23307 blo "500,4300" 23240 23308 ) 23241 *78 1(Text23309 *780 (Text 23242 23310 va (VaSet 23243 23311 font "Arial,8,1" … … 23247 23315 blo "500,5300" 23248 23316 ) 23249 *78 2(Text23317 *781 (Text 23250 23318 va (VaSet 23251 23319 font "Arial,8,1" … … 23292 23360 stg "VerticalLayoutStrategy" 23293 23361 textVec [ 23294 *78 3(Text23362 *782 (Text 23295 23363 va (VaSet 23296 23364 font "Arial,8,1" … … 23300 23368 blo "50,4300" 23301 23369 ) 23302 *78 4(Text23370 *783 (Text 23303 23371 va (VaSet 23304 23372 font "Arial,8,1" … … 23308 23376 blo "50,5300" 23309 23377 ) 23310 *78 5(Text23378 *784 (Text 23311 23379 va (VaSet 23312 23380 font "Arial,8,1" … … 23349 23417 stg "VerticalLayoutStrategy" 23350 23418 textVec [ 23351 *78 6(Text23419 *785 (Text 23352 23420 va (VaSet 23353 23421 font "Arial,8,1" … … 23358 23426 tm "HdlTextNameMgr" 23359 23427 ) 23360 *78 7(Text23428 *786 (Text 23361 23429 va (VaSet 23362 23430 font "Arial,8,1" … … 23761 23829 stg "VerticalLayoutStrategy" 23762 23830 textVec [ 23763 *78 8(Text23831 *787 (Text 23764 23832 va (VaSet 23765 23833 font "Arial,8,1" … … 23769 23837 blo "14100,20800" 23770 23838 ) 23771 *78 9(MLText23839 *788 (MLText 23772 23840 va (VaSet 23773 23841 ) … … 23821 23889 stg "VerticalLayoutStrategy" 23822 23890 textVec [ 23823 *7 90(Text23891 *789 (Text 23824 23892 va (VaSet 23825 23893 font "Arial,8,1" … … 23829 23897 blo "14100,20800" 23830 23898 ) 23831 *79 1(MLText23899 *790 (MLText 23832 23900 va (VaSet 23833 23901 ) … … 23969 24037 commonDM (CommonDM 23970 24038 ldm (LogicalDM 23971 suid 299,024039 suid 301,0 23972 24040 usingSuid 1 23973 emptyRow *79 2(LEmptyRow24041 emptyRow *791 (LEmptyRow 23974 24042 ) 23975 24043 uid 54,0 23976 24044 optionalChildren [ 23977 *79 3(RefLabelRowHdr23978 ) 23979 *79 4(TitleRowHdr23980 ) 23981 *79 5(FilterRowHdr23982 ) 23983 *79 6(RefLabelColHdr24045 *792 (RefLabelRowHdr 24046 ) 24047 *793 (TitleRowHdr 24048 ) 24049 *794 (FilterRowHdr 24050 ) 24051 *795 (RefLabelColHdr 23984 24052 tm "RefLabelColHdrMgr" 23985 24053 ) 23986 *79 7(RowExpandColHdr24054 *796 (RowExpandColHdr 23987 24055 tm "RowExpandColHdrMgr" 23988 24056 ) 23989 *79 8(GroupColHdr24057 *797 (GroupColHdr 23990 24058 tm "GroupColHdrMgr" 23991 24059 ) 23992 *79 9(NameColHdr24060 *798 (NameColHdr 23993 24061 tm "BlockDiagramNameColHdrMgr" 23994 24062 ) 23995 * 800(ModeColHdr24063 *799 (ModeColHdr 23996 24064 tm "BlockDiagramModeColHdrMgr" 23997 24065 ) 23998 *80 1(TypeColHdr24066 *800 (TypeColHdr 23999 24067 tm "BlockDiagramTypeColHdrMgr" 24000 24068 ) 24001 *80 2(BoundsColHdr24069 *801 (BoundsColHdr 24002 24070 tm "BlockDiagramBoundsColHdrMgr" 24003 24071 ) 24004 *80 3(InitColHdr24072 *802 (InitColHdr 24005 24073 tm "BlockDiagramInitColHdrMgr" 24006 24074 ) 24007 *80 4(EolColHdr24075 *803 (EolColHdr 24008 24076 tm "BlockDiagramEolColHdrMgr" 24009 24077 ) 24010 *80 5(LeafLogPort24078 *804 (LeafLogPort 24011 24079 port (LogicalPort 24012 24080 m 4 … … 24022 24090 uid 516,0 24023 24091 ) 24024 *80 6(LeafLogPort24092 *805 (LeafLogPort 24025 24093 port (LogicalPort 24026 24094 m 4 … … 24035 24103 uid 518,0 24036 24104 ) 24037 *80 7(LeafLogPort24105 *806 (LeafLogPort 24038 24106 port (LogicalPort 24039 24107 m 4 … … 24048 24116 uid 520,0 24049 24117 ) 24050 *80 8(LeafLogPort24118 *807 (LeafLogPort 24051 24119 port (LogicalPort 24052 24120 m 4 … … 24061 24129 uid 530,0 24062 24130 ) 24063 *80 9(LeafLogPort24131 *808 (LeafLogPort 24064 24132 port (LogicalPort 24065 24133 m 4 … … 24074 24142 uid 532,0 24075 24143 ) 24076 *8 10(LeafLogPort24144 *809 (LeafLogPort 24077 24145 port (LogicalPort 24078 24146 m 1 … … 24087 24155 uid 534,0 24088 24156 ) 24089 *81 1(LeafLogPort24157 *810 (LeafLogPort 24090 24158 port (LogicalPort 24091 24159 m 1 … … 24100 24168 uid 536,0 24101 24169 ) 24102 *81 2(LeafLogPort24170 *811 (LeafLogPort 24103 24171 port (LogicalPort 24104 24172 m 2 … … 24113 24181 uid 538,0 24114 24182 ) 24183 *812 (LeafLogPort 24184 port (LogicalPort 24185 m 1 24186 decl (Decl 24187 n "wiz_cs" 24188 t "std_logic" 24189 o 44 24190 suid 14,0 24191 i "'1'" 24192 ) 24193 ) 24194 uid 540,0 24195 ) 24115 24196 *813 (LeafLogPort 24116 24197 port (LogicalPort 24117 24198 m 1 24118 24199 decl (Decl 24119 n "wiz_ cs"24120 t "std_logic" 24121 o 4 424122 suid 1 4,024200 n "wiz_wr" 24201 t "std_logic" 24202 o 47 24203 suid 15,0 24123 24204 i "'1'" 24124 24205 ) 24125 24206 ) 24126 uid 54 0,024207 uid 542,0 24127 24208 ) 24128 24209 *814 (LeafLogPort … … 24130 24211 m 1 24131 24212 decl (Decl 24132 n "wiz_wr"24133 t "std_logic"24134 o 4724135 suid 15,024136 i "'1'"24137 )24138 )24139 uid 542,024140 )24141 *815 (LeafLogPort24142 port (LogicalPort24143 m 124144 decl (Decl24145 24213 n "wiz_rd" 24146 24214 t "std_logic" … … 24152 24220 uid 546,0 24153 24221 ) 24154 *81 6(LeafLogPort24222 *815 (LeafLogPort 24155 24223 port (LogicalPort 24156 24224 decl (Decl … … 24163 24231 uid 548,0 24164 24232 ) 24165 *81 7(LeafLogPort24233 *816 (LeafLogPort 24166 24234 port (LogicalPort 24167 24235 decl (Decl … … 24175 24243 uid 1455,0 24176 24244 ) 24177 *81 8(LeafLogPort24245 *817 (LeafLogPort 24178 24246 port (LogicalPort 24179 24247 decl (Decl … … 24188 24256 uid 1457,0 24189 24257 ) 24190 *81 9(LeafLogPort24258 *818 (LeafLogPort 24191 24259 port (LogicalPort 24192 24260 decl (Decl … … 24200 24268 uid 1694,0 24201 24269 ) 24202 *8 20(LeafLogPort24270 *819 (LeafLogPort 24203 24271 port (LogicalPort 24204 24272 lang 2 … … 24216 24284 uid 1993,0 24217 24285 ) 24218 *82 1(LeafLogPort24286 *820 (LeafLogPort 24219 24287 port (LogicalPort 24220 24288 m 4 … … 24231 24299 uid 2305,0 24232 24300 ) 24301 *821 (LeafLogPort 24302 port (LogicalPort 24303 lang 2 24304 m 4 24305 decl (Decl 24306 n "wiz_busy" 24307 t "std_logic" 24308 o 122 24309 suid 38,0 24310 ) 24311 ) 24312 uid 2510,0 24313 ) 24233 24314 *822 (LeafLogPort 24234 24315 port (LogicalPort … … 24236 24317 m 4 24237 24318 decl (Decl 24238 n "wiz_busy"24239 t "std_logic"24240 o 12224241 suid 38,024242 )24243 )24244 uid 2510,024245 )24246 *823 (LeafLogPort24247 port (LogicalPort24248 lang 224249 m 424250 decl (Decl24251 24319 n "wiz_write_ea" 24252 24320 t "std_logic" … … 24258 24326 uid 2512,0 24259 24327 ) 24260 *82 4(LeafLogPort24328 *823 (LeafLogPort 24261 24329 port (LogicalPort 24262 24330 lang 2 … … 24273 24341 uid 2514,0 24274 24342 ) 24275 *82 5(LeafLogPort24343 *824 (LeafLogPort 24276 24344 port (LogicalPort 24277 24345 lang 2 … … 24289 24357 uid 2516,0 24290 24358 ) 24291 *82 6(LeafLogPort24359 *825 (LeafLogPort 24292 24360 port (LogicalPort 24293 24361 lang 2 … … 24304 24372 uid 2518,0 24305 24373 ) 24374 *826 (LeafLogPort 24375 port (LogicalPort 24376 lang 2 24377 m 4 24378 decl (Decl 24379 n "wiz_write_end" 24380 t "std_logic" 24381 o 126 24382 suid 43,0 24383 i "'0'" 24384 ) 24385 ) 24386 uid 2520,0 24387 ) 24306 24388 *827 (LeafLogPort 24307 24389 port (LogicalPort … … 24309 24391 m 4 24310 24392 decl (Decl 24311 n "wiz_write_end"24312 t "std_logic"24313 o 12624314 suid 43,024315 i "'0'"24316 )24317 )24318 uid 2520,024319 )24320 *828 (LeafLogPort24321 port (LogicalPort24322 lang 224323 m 424324 decl (Decl24325 24393 n "wiz_write_header" 24326 24394 t "std_logic" … … 24332 24400 uid 2522,0 24333 24401 ) 24402 *828 (LeafLogPort 24403 port (LogicalPort 24404 m 4 24405 decl (Decl 24406 n "ram_write_ea" 24407 t "std_logic" 24408 o 100 24409 suid 48,0 24410 ) 24411 ) 24412 uid 2604,0 24413 ) 24334 24414 *829 (LeafLogPort 24335 24415 port (LogicalPort 24336 24416 m 4 24337 24417 decl (Decl 24338 n "ram_write_ea" 24339 t "std_logic" 24340 o 100 24341 suid 48,0 24342 ) 24343 ) 24344 uid 2604,0 24418 n "ram_write_ready" 24419 t "std_logic" 24420 o 101 24421 suid 49,0 24422 i "'0'" 24423 ) 24424 ) 24425 uid 2606,0 24345 24426 ) 24346 24427 *830 (LeafLogPort … … 24348 24429 m 4 24349 24430 decl (Decl 24350 n " ram_write_ready"24351 t "std_logic" 24352 o 10124353 suid 49,024431 n "config_start" 24432 t "std_logic" 24433 o 67 24434 suid 50,0 24354 24435 i "'0'" 24355 24436 ) 24356 24437 ) 24357 uid 260 6,024438 uid 2608,0 24358 24439 ) 24359 24440 *831 (LeafLogPort … … 24361 24442 m 4 24362 24443 decl (Decl 24363 n "config_start"24364 t "std_logic"24365 o 6724366 suid 50,024367 i "'0'"24368 )24369 )24370 uid 2608,024371 )24372 *832 (LeafLogPort24373 port (LogicalPort24374 m 424375 decl (Decl24376 24444 n "config_ready" 24377 24445 t "std_logic" … … 24382 24450 uid 2610,0 24383 24451 ) 24384 *83 3(LeafLogPort24452 *832 (LeafLogPort 24385 24453 port (LogicalPort 24386 24454 m 4 … … 24394 24462 uid 2612,0 24395 24463 ) 24396 *83 4(LeafLogPort24464 *833 (LeafLogPort 24397 24465 port (LogicalPort 24398 24466 m 4 … … 24407 24475 uid 2646,0 24408 24476 ) 24409 *83 5(LeafLogPort24477 *834 (LeafLogPort 24410 24478 port (LogicalPort 24411 24479 m 1 … … 24420 24488 uid 2812,0 24421 24489 ) 24422 *83 6(LeafLogPort24490 *835 (LeafLogPort 24423 24491 port (LogicalPort 24424 24492 m 4 … … 24432 24500 uid 2962,0 24433 24501 ) 24502 *836 (LeafLogPort 24503 port (LogicalPort 24504 m 1 24505 decl (Decl 24506 n "CLK_25_PS" 24507 t "std_logic" 24508 o 15 24509 suid 81,0 24510 ) 24511 ) 24512 uid 3902,0 24513 ) 24434 24514 *837 (LeafLogPort 24435 24515 port (LogicalPort 24436 24516 m 1 24437 24517 decl (Decl 24438 n "CLK_ 25_PS"24439 t "std_logic" 24440 o 1 524441 suid 81,024442 ) 24443 ) 24444 uid 3902,024518 n "CLK_50" 24519 t "std_logic" 24520 o 16 24521 suid 90,0 24522 ) 24523 ) 24524 uid 4070,0 24445 24525 ) 24446 24526 *838 (LeafLogPort 24447 24527 port (LogicalPort 24448 m 124449 decl (Decl 24450 n "CLK_ 50"24451 t "std_logic" 24452 o 1624453 suid 9 0,024454 ) 24455 ) 24456 uid 4 070,024528 m 4 24529 decl (Decl 24530 n "CLK_25" 24531 t "std_logic" 24532 o 50 24533 suid 91,0 24534 ) 24535 ) 24536 uid 4212,0 24457 24537 ) 24458 24538 *839 (LeafLogPort 24459 24539 port (LogicalPort 24460 m 424461 decl (Decl24462 n "CLK_25"24463 t "std_logic"24464 o 5024465 suid 91,024466 )24467 )24468 uid 4212,024469 )24470 *840 (LeafLogPort24471 port (LogicalPort24472 24540 decl (Decl 24473 24541 n "CLK" … … 24479 24547 uid 4234,0 24480 24548 ) 24481 *84 1(LeafLogPort24549 *840 (LeafLogPort 24482 24550 port (LogicalPort 24483 24551 decl (Decl … … 24491 24559 uid 4262,0 24492 24560 ) 24493 *84 2(LeafLogPort24561 *841 (LeafLogPort 24494 24562 port (LogicalPort 24495 24563 decl (Decl … … 24502 24570 uid 4276,0 24503 24571 ) 24504 *84 3(LeafLogPort24572 *842 (LeafLogPort 24505 24573 port (LogicalPort 24506 24574 m 4 … … 24515 24583 uid 4563,0 24516 24584 ) 24517 *84 4(LeafLogPort24585 *843 (LeafLogPort 24518 24586 port (LogicalPort 24519 24587 m 4 … … 24527 24595 uid 4565,0 24528 24596 ) 24529 *84 5(LeafLogPort24597 *844 (LeafLogPort 24530 24598 port (LogicalPort 24531 24599 m 4 … … 24540 24608 uid 4569,0 24541 24609 ) 24542 *84 6(LeafLogPort24610 *845 (LeafLogPort 24543 24611 port (LogicalPort 24544 24612 m 1 … … 24554 24622 uid 4585,0 24555 24623 ) 24556 *84 7(LeafLogPort24624 *846 (LeafLogPort 24557 24625 port (LogicalPort 24558 24626 m 1 … … 24567 24635 uid 4587,0 24568 24636 ) 24637 *847 (LeafLogPort 24638 port (LogicalPort 24639 decl (Decl 24640 n "SROUT_in_0" 24641 t "std_logic" 24642 o 2 24643 suid 112,0 24644 ) 24645 ) 24646 uid 4733,0 24647 ) 24569 24648 *848 (LeafLogPort 24570 24649 port (LogicalPort 24571 24650 decl (Decl 24572 n "SROUT_in_ 0"24573 t "std_logic" 24574 o 224575 suid 11 2,024576 ) 24577 ) 24578 uid 473 3,024651 n "SROUT_in_1" 24652 t "std_logic" 24653 o 3 24654 suid 113,0 24655 ) 24656 ) 24657 uid 4735,0 24579 24658 ) 24580 24659 *849 (LeafLogPort 24581 24660 port (LogicalPort 24582 24661 decl (Decl 24583 n "SROUT_in_ 1"24584 t "std_logic" 24585 o 324586 suid 11 3,024587 ) 24588 ) 24589 uid 473 5,024662 n "SROUT_in_2" 24663 t "std_logic" 24664 o 4 24665 suid 114,0 24666 ) 24667 ) 24668 uid 4737,0 24590 24669 ) 24591 24670 *850 (LeafLogPort 24592 24671 port (LogicalPort 24593 24672 decl (Decl 24594 n "SROUT_in_ 2"24595 t "std_logic" 24596 o 424597 suid 11 4,024598 ) 24599 ) 24600 uid 473 7,024673 n "SROUT_in_3" 24674 t "std_logic" 24675 o 5 24676 suid 115,0 24677 ) 24678 ) 24679 uid 4739,0 24601 24680 ) 24602 24681 *851 (LeafLogPort 24603 24682 port (LogicalPort 24604 decl (Decl 24605 n "SROUT_in_3" 24606 t "std_logic" 24607 o 5 24608 suid 115,0 24609 ) 24610 ) 24611 uid 4739,0 24683 m 4 24684 decl (Decl 24685 n "drs_read_s_cell_ready" 24686 t "std_logic" 24687 o 84 24688 suid 116,0 24689 ) 24690 ) 24691 uid 4749,0 24612 24692 ) 24613 24693 *852 (LeafLogPort 24614 24694 port (LogicalPort 24615 m 4 24616 decl (Decl 24617 n "drs_read_s_cell_ready" 24618 t "std_logic" 24619 o 84 24620 suid 116,0 24621 ) 24622 ) 24623 uid 4749,0 24695 m 1 24696 decl (Decl 24697 n "RSRLOAD" 24698 t "std_logic" 24699 o 23 24700 suid 117,0 24701 i "'0'" 24702 ) 24703 ) 24704 uid 4974,0 24624 24705 ) 24625 24706 *853 (LeafLogPort … … 24627 24708 m 1 24628 24709 decl (Decl 24629 n "RSRLOAD"24630 t "std_logic"24631 o 2324632 suid 117,024633 i "'0'"24634 )24635 )24636 uid 4974,024637 )24638 *854 (LeafLogPort24639 port (LogicalPort24640 m 124641 decl (Decl24642 24710 n "SRCLK" 24643 24711 t "std_logic" … … 24649 24717 uid 4976,0 24650 24718 ) 24651 *85 5(LeafLogPort24719 *854 (LeafLogPort 24652 24720 port (LogicalPort 24653 24721 m 4 … … 24662 24730 uid 5198,0 24663 24731 ) 24732 *855 (LeafLogPort 24733 port (LogicalPort 24734 m 4 24735 decl (Decl 24736 n "config_data_valid" 24737 t "std_logic" 24738 o 60 24739 suid 120,0 24740 ) 24741 ) 24742 uid 5200,0 24743 ) 24664 24744 *856 (LeafLogPort 24665 24745 port (LogicalPort 24666 24746 m 4 24667 24747 decl (Decl 24668 n "config_data_valid"24669 t "std_logic"24670 o 6024671 suid 120,024672 )24673 )24674 uid 5200,024675 )24676 *857 (LeafLogPort24677 port (LogicalPort24678 m 424679 decl (Decl24680 24748 n "config_busy" 24681 24749 t "std_logic" … … 24686 24754 uid 5202,0 24687 24755 ) 24688 *85 8(LeafLogPort24756 *857 (LeafLogPort 24689 24757 port (LogicalPort 24690 24758 m 4 … … 24699 24767 uid 5204,0 24700 24768 ) 24769 *858 (LeafLogPort 24770 port (LogicalPort 24771 m 4 24772 decl (Decl 24773 n "config_wr_en" 24774 t "std_logic" 24775 o 74 24776 suid 123,0 24777 ) 24778 ) 24779 uid 5206,0 24780 ) 24701 24781 *859 (LeafLogPort 24702 24782 port (LogicalPort 24703 24783 m 4 24704 24784 decl (Decl 24705 n "config_wr_en"24706 t "std_logic"24707 o 7424708 suid 123,024709 )24710 )24711 uid 5206,024712 )24713 *860 (LeafLogPort24714 port (LogicalPort24715 m 424716 decl (Decl24717 24785 n "config_rd_en" 24718 24786 t "std_logic" … … 24723 24791 uid 5208,0 24724 24792 ) 24725 *86 1(LeafLogPort24793 *860 (LeafLogPort 24726 24794 port (LogicalPort 24727 24795 m 4 … … 24735 24803 uid 5210,0 24736 24804 ) 24805 *861 (LeafLogPort 24806 port (LogicalPort 24807 m 4 24808 decl (Decl 24809 n "config_start_cm" 24810 t "std_logic" 24811 o 68 24812 suid 131,0 24813 ) 24814 ) 24815 uid 5212,0 24816 ) 24737 24817 *862 (LeafLogPort 24738 24818 port (LogicalPort 24739 24819 m 4 24740 24820 decl (Decl 24741 n "config_start_cm"24742 t "std_logic"24743 o 6824744 suid 131,024745 )24746 )24747 uid 5212,024748 )24749 *863 (LeafLogPort24750 port (LogicalPort24751 m 424752 decl (Decl24753 24821 n "config_ready_cm" 24754 24822 t "std_logic" … … 24759 24827 uid 5214,0 24760 24828 ) 24761 *86 4(LeafLogPort24829 *863 (LeafLogPort 24762 24830 port (LogicalPort 24763 24831 m 1 … … 24774 24842 uid 5226,0 24775 24843 ) 24776 *86 5(LeafLogPort24844 *864 (LeafLogPort 24777 24845 port (LogicalPort 24778 24846 m 4 … … 24786 24854 uid 5502,0 24787 24855 ) 24788 *86 6(LeafLogPort24856 *865 (LeafLogPort 24789 24857 port (LogicalPort 24790 24858 m 4 … … 24798 24866 uid 5504,0 24799 24867 ) 24800 *86 7(LeafLogPort24868 *866 (LeafLogPort 24801 24869 port (LogicalPort 24802 24870 m 4 … … 24810 24878 uid 5600,0 24811 24879 ) 24812 *86 8(LeafLogPort24880 *867 (LeafLogPort 24813 24881 port (LogicalPort 24814 24882 lang 10 … … 24824 24892 uid 5642,0 24825 24893 ) 24826 *86 9(LeafLogPort24894 *868 (LeafLogPort 24827 24895 port (LogicalPort 24828 24896 m 4 … … 24836 24904 uid 5644,0 24837 24905 ) 24838 *8 70(LeafLogPort24906 *869 (LeafLogPort 24839 24907 port (LogicalPort 24840 24908 m 4 … … 24849 24917 uid 5751,0 24850 24918 ) 24851 *87 1(LeafLogPort24919 *870 (LeafLogPort 24852 24920 port (LogicalPort 24853 24921 m 1 … … 24861 24929 uid 5867,0 24862 24930 ) 24863 *87 2(LeafLogPort24931 *871 (LeafLogPort 24864 24932 port (LogicalPort 24865 24933 m 2 … … 24875 24943 uid 5869,0 24876 24944 ) 24877 *87 3(LeafLogPort24945 *872 (LeafLogPort 24878 24946 port (LogicalPort 24879 24947 m 1 … … 24887 24955 uid 5871,0 24888 24956 ) 24889 *87 4(LeafLogPort24957 *873 (LeafLogPort 24890 24958 port (LogicalPort 24891 24959 m 1 … … 24900 24968 uid 5873,0 24901 24969 ) 24970 *874 (LeafLogPort 24971 port (LogicalPort 24972 m 4 24973 decl (Decl 24974 n "new_config" 24975 t "std_logic" 24976 o 92 24977 suid 155,0 24978 i "'0'" 24979 ) 24980 ) 24981 uid 5966,0 24982 ) 24902 24983 *875 (LeafLogPort 24903 24984 port (LogicalPort 24904 24985 m 4 24905 24986 decl (Decl 24906 n "new_config" 24907 t "std_logic" 24908 o 92 24909 suid 155,0 24910 i "'0'" 24911 ) 24912 ) 24913 uid 5966,0 24987 n "config_started" 24988 t "std_logic" 24989 o 70 24990 suid 156,0 24991 ) 24992 ) 24993 uid 5968,0 24914 24994 ) 24915 24995 *876 (LeafLogPort … … 24917 24997 m 4 24918 24998 decl (Decl 24919 n "config_started" 24920 t "std_logic" 24921 o 70 24922 suid 156,0 24923 ) 24924 ) 24925 uid 5968,0 24999 n "config_started_spi" 25000 t "std_logic" 25001 o 73 25002 suid 159,0 25003 i "'0'" 25004 ) 25005 ) 25006 uid 6022,0 24926 25007 ) 24927 25008 *877 (LeafLogPort … … 24929 25010 m 4 24930 25011 decl (Decl 24931 n "config_started_ spi"24932 t "std_logic" 24933 o 7 324934 suid 1 59,025012 n "config_started_cu" 25013 t "std_logic" 25014 o 71 25015 suid 160,0 24935 25016 i "'0'" 24936 25017 ) 24937 25018 ) 24938 uid 602 2,025019 uid 6024,0 24939 25020 ) 24940 25021 *878 (LeafLogPort … … 24942 25023 m 4 24943 25024 decl (Decl 24944 n "config_started_cu"24945 t "std_logic"24946 o 7124947 suid 160,024948 i "'0'"24949 )24950 )24951 uid 6024,024952 )24953 *879 (LeafLogPort24954 port (LogicalPort24955 m 424956 decl (Decl24957 25025 n "config_started_mm" 24958 25026 t "std_logic" … … 24963 25031 uid 6026,0 24964 25032 ) 24965 *8 80(LeafLogPort25033 *879 (LeafLogPort 24966 25034 port (LogicalPort 24967 25035 m 1 … … 24976 25044 uid 6172,0 24977 25045 ) 24978 *88 1(LeafLogPort25046 *880 (LeafLogPort 24979 25047 port (LogicalPort 24980 25048 m 1 … … 24991 25059 uid 6374,0 24992 25060 ) 25061 *881 (LeafLogPort 25062 port (LogicalPort 25063 m 4 25064 decl (Decl 25065 n "dwrite_enable" 25066 t "std_logic" 25067 o 91 25068 suid 167,0 25069 i "'1'" 25070 ) 25071 ) 25072 uid 6464,0 25073 ) 24993 25074 *882 (LeafLogPort 24994 25075 port (LogicalPort 24995 25076 m 4 24996 25077 decl (Decl 24997 n "dwrite_enable"24998 t "std_logic"24999 o 9125000 suid 167,025001 i "'1'"25002 )25003 )25004 uid 6464,025005 )25006 *883 (LeafLogPort25007 port (LogicalPort25008 m 425009 decl (Decl25010 25078 n "dwrite" 25011 25079 t "std_logic" … … 25017 25085 uid 6554,0 25018 25086 ) 25019 *88 4(LeafLogPort25087 *883 (LeafLogPort 25020 25088 port (LogicalPort 25021 25089 lang 2 … … 25030 25098 uid 8420,0 25031 25099 ) 25100 *884 (LeafLogPort 25101 port (LogicalPort 25102 m 4 25103 decl (Decl 25104 n "sclk1" 25105 t "std_logic" 25106 o 107 25107 suid 191,0 25108 ) 25109 ) 25110 uid 8758,0 25111 ) 25032 25112 *885 (LeafLogPort 25033 25113 port (LogicalPort 25034 25114 m 4 25035 25115 decl (Decl 25036 n "sclk1"25037 t "std_logic"25038 o 10725039 suid 191,025040 )25041 )25042 uid 8758,025043 )25044 *886 (LeafLogPort25045 port (LogicalPort25046 m 425047 decl (Decl25048 25116 n "sclk_enable" 25049 25117 t "std_logic" … … 25054 25122 uid 8760,0 25055 25123 ) 25056 *88 7(LeafLogPort25124 *886 (LeafLogPort 25057 25125 port (LogicalPort 25058 25126 m 1 … … 25067 25135 uid 9018,0 25068 25136 ) 25069 *88 8(LeafLogPort25137 *887 (LeafLogPort 25070 25138 port (LogicalPort 25071 25139 m 4 … … 25082 25150 uid 9247,0 25083 25151 ) 25084 *88 9(LeafLogPort25152 *888 (LeafLogPort 25085 25153 port (LogicalPort 25086 25154 m 4 … … 25098 25166 uid 9249,0 25099 25167 ) 25100 *8 90(LeafLogPort25168 *889 (LeafLogPort 25101 25169 port (LogicalPort 25102 25170 m 4 … … 25113 25181 uid 10024,0 25114 25182 ) 25183 *890 (LeafLogPort 25184 port (LogicalPort 25185 m 4 25186 decl (Decl 25187 n "srclk_enable" 25188 t "std_logic" 25189 o 113 25190 suid 222,0 25191 i "'0'" 25192 ) 25193 ) 25194 uid 10026,0 25195 ) 25115 25196 *891 (LeafLogPort 25116 25197 port (LogicalPort 25117 25198 m 4 25118 25199 decl (Decl 25119 n "srclk_enable"25120 t "std_logic"25121 o 11325122 suid 222,025123 i "'0'"25124 )25125 )25126 uid 10026,025127 )25128 *892 (LeafLogPort25129 port (LogicalPort25130 m 425131 decl (Decl25132 25200 n "SRCLK1" 25133 25201 t "std_logic" … … 25139 25207 uid 10028,0 25140 25208 ) 25141 *89 3(LeafLogPort25209 *892 (LeafLogPort 25142 25210 port (LogicalPort 25143 25211 m 4 … … 25155 25223 uid 10208,0 25156 25224 ) 25157 *89 4(LeafLogPort25225 *893 (LeafLogPort 25158 25226 port (LogicalPort 25159 25227 m 4 … … 25171 25239 uid 10210,0 25172 25240 ) 25241 *894 (LeafLogPort 25242 port (LogicalPort 25243 m 4 25244 decl (Decl 25245 n "s_trigger" 25246 t "std_logic" 25247 o 105 25248 suid 230,0 25249 ) 25250 ) 25251 uid 10294,0 25252 ) 25173 25253 *895 (LeafLogPort 25174 25254 port (LogicalPort 25175 25255 m 4 25176 25256 decl (Decl 25177 n "s _trigger"25178 t "std_logic" 25179 o 1 0525180 suid 23 0,025181 ) 25182 ) 25183 uid 10 294,025257 n "start_srin_write_8b" 25258 t "std_logic" 25259 o 116 25260 suid 231,0 25261 ) 25262 ) 25263 uid 10334,0 25184 25264 ) 25185 25265 *896 (LeafLogPort … … 25187 25267 m 4 25188 25268 decl (Decl 25189 n "start_srin_write_8b" 25190 t "std_logic" 25191 o 116 25192 suid 231,0 25193 ) 25194 ) 25195 uid 10334,0 25269 n "srin_write_ack" 25270 t "std_logic" 25271 o 114 25272 suid 232,0 25273 i "'0'" 25274 ) 25275 ) 25276 uid 10336,0 25196 25277 ) 25197 25278 *897 (LeafLogPort … … 25199 25280 m 4 25200 25281 decl (Decl 25201 n "srin_write_ack"25202 t "std_logic"25203 o 11425204 suid 232,025205 i "'0'"25206 )25207 )25208 uid 10336,025209 )25210 *898 (LeafLogPort25211 port (LogicalPort25212 m 425213 decl (Decl25214 25282 n "srin_write_ready" 25215 25283 t "std_logic" … … 25221 25289 uid 10338,0 25222 25290 ) 25223 *89 9(LeafLogPort25291 *898 (LeafLogPort 25224 25292 port (LogicalPort 25225 25293 m 4 … … 25235 25303 uid 10340,0 25236 25304 ) 25237 * 900(LeafLogPort25305 *899 (LeafLogPort 25238 25306 port (LogicalPort 25239 25307 m 1 … … 25248 25316 uid 10342,0 25249 25317 ) 25250 *901 (LeafLogPort 25251 port (LogicalPort 25252 m 4 25253 decl (Decl 25254 n "trigger_out" 25255 t "std_logic" 25256 preAdd 0 25257 posAdd 0 25258 o 120 25259 suid 240,0 25260 ) 25261 ) 25262 uid 10473,0 25263 ) 25264 *902 (LeafLogPort 25318 *900 (LeafLogPort 25265 25319 port (LogicalPort 25266 25320 lang 2 … … 25279 25333 uid 10475,0 25280 25334 ) 25335 *901 (LeafLogPort 25336 port (LogicalPort 25337 m 4 25338 decl (Decl 25339 n "socks_connected" 25340 t "std_logic" 25341 o 111 25342 suid 243,0 25343 ) 25344 ) 25345 uid 10763,0 25346 ) 25347 *902 (LeafLogPort 25348 port (LogicalPort 25349 m 4 25350 decl (Decl 25351 n "socks_waiting" 25352 t "std_logic" 25353 o 112 25354 suid 244,0 25355 ) 25356 ) 25357 uid 10765,0 25358 ) 25281 25359 *903 (LeafLogPort 25282 25360 port (LogicalPort 25283 m 425284 decl (Decl 25285 n " socks_connected"25286 t "std_logic" 25287 o 11125288 suid 24 3,025289 ) 25290 ) 25291 uid 1076 3,025361 m 1 25362 decl (Decl 25363 n "green" 25364 t "std_logic" 25365 o 34 25366 suid 248,0 25367 ) 25368 ) 25369 uid 10767,0 25292 25370 ) 25293 25371 *904 (LeafLogPort 25294 25372 port (LogicalPort 25295 m 425296 decl (Decl 25297 n " socks_waiting"25298 t "std_logic" 25299 o 11225300 suid 24 4,025301 ) 25302 ) 25303 uid 1076 5,025373 m 1 25374 decl (Decl 25375 n "amber" 25376 t "std_logic" 25377 o 29 25378 suid 249,0 25379 ) 25380 ) 25381 uid 10769,0 25304 25382 ) 25305 25383 *905 (LeafLogPort … … 25307 25385 m 1 25308 25386 decl (Decl 25309 n " green"25310 t "std_logic" 25311 o 3 425312 suid 2 48,025313 ) 25314 ) 25315 uid 107 67,025387 n "red" 25388 t "std_logic" 25389 o 39 25390 suid 250,0 25391 ) 25392 ) 25393 uid 10771,0 25316 25394 ) 25317 25395 *906 (LeafLogPort 25318 25396 port (LogicalPort 25319 m 125320 decl (Decl 25321 n " amber"25322 t "std_logic" 25323 o 2925324 suid 2 49,025325 ) 25326 ) 25327 uid 1 0769,025397 m 4 25398 decl (Decl 25399 n "drs_readout_started" 25400 t "std_logic" 25401 o 87 25402 suid 252,0 25403 ) 25404 ) 25405 uid 11411,0 25328 25406 ) 25329 25407 *907 (LeafLogPort 25330 25408 port (LogicalPort 25331 m 125332 decl (Decl25333 n "red"25334 t "std_logic"25335 o 3925336 suid 250,025337 )25338 )25339 uid 10771,025340 )25341 *908 (LeafLogPort25342 port (LogicalPort25343 m 425344 decl (Decl25345 n "drs_readout_started"25346 t "std_logic"25347 o 8725348 suid 252,025349 )25350 )25351 uid 11411,025352 )25353 *909 (LeafLogPort25354 port (LogicalPort25355 25409 m 4 25356 25410 decl (Decl … … 25363 25417 uid 11966,0 25364 25418 ) 25365 *9 10(LeafLogPort25419 *908 (LeafLogPort 25366 25420 port (LogicalPort 25367 25421 m 4 … … 25377 25431 uid 12310,0 25378 25432 ) 25379 *9 11(LeafLogPort25433 *909 (LeafLogPort 25380 25434 port (LogicalPort 25381 25435 m 4 … … 25391 25445 uid 12659,0 25392 25446 ) 25393 *91 2(LeafLogPort25447 *910 (LeafLogPort 25394 25448 port (LogicalPort 25395 25449 m 4 … … 25408 25462 uid 12661,0 25409 25463 ) 25464 *911 (LeafLogPort 25465 port (LogicalPort 25466 m 4 25467 decl (Decl 25468 n "drs_readout_ready_ack" 25469 t "std_logic" 25470 o 86 25471 suid 267,0 25472 ) 25473 ) 25474 uid 12663,0 25475 ) 25476 *912 (LeafLogPort 25477 port (LogicalPort 25478 m 1 25479 decl (Decl 25480 n "additional_flasher_out" 25481 t "std_logic" 25482 o 28 25483 suid 272,0 25484 ) 25485 ) 25486 uid 12719,0 25487 ) 25410 25488 *913 (LeafLogPort 25411 25489 port (LogicalPort 25412 25490 m 4 25413 25491 decl (Decl 25414 n "drs_readout_ready_ack"25415 t "std_logic"25416 o 8625417 suid 267,025418 )25419 )25420 uid 12663,025421 )25422 *914 (LeafLogPort25423 port (LogicalPort25424 m 125425 decl (Decl25426 n "additional_flasher_out"25427 t "std_logic"25428 o 2825429 suid 272,025430 )25431 )25432 uid 12719,025433 )25434 *915 (LeafLogPort25435 port (LogicalPort25436 m 425437 decl (Decl25438 25492 n "c_trigger_enable" 25439 25493 t "std_logic" … … 25445 25499 uid 13275,0 25446 25500 ) 25447 *91 6(LeafLogPort25501 *914 (LeafLogPort 25448 25502 port (LogicalPort 25449 25503 m 4 … … 25461 25515 uid 13277,0 25462 25516 ) 25463 *91 7(LeafLogPort25517 *915 (LeafLogPort 25464 25518 port (LogicalPort 25465 25519 m 4 … … 25473 25527 uid 13279,0 25474 25528 ) 25475 *91 8(LeafLogPort25529 *916 (LeafLogPort 25476 25530 port (LogicalPort 25477 25531 m 4 … … 25485 25539 uid 13281,0 25486 25540 ) 25487 *91 9(LeafLogPort25541 *917 (LeafLogPort 25488 25542 port (LogicalPort 25489 25543 decl (Decl … … 25498 25552 scheme 0 25499 25553 ) 25500 *9 20(LeafLogPort25554 *918 (LeafLogPort 25501 25555 port (LogicalPort 25502 25556 decl (Decl … … 25511 25565 scheme 0 25512 25566 ) 25513 *9 21(LeafLogPort25567 *919 (LeafLogPort 25514 25568 port (LogicalPort 25515 25569 decl (Decl … … 25525 25579 scheme 0 25526 25580 ) 25527 *92 2(LeafLogPort25581 *920 (LeafLogPort 25528 25582 port (LogicalPort 25529 25583 m 1 … … 25540 25594 uid 14507,0 25541 25595 ) 25542 *92 3(LeafLogPort25596 *921 (LeafLogPort 25543 25597 port (LogicalPort 25544 25598 m 1 … … 25555 25609 uid 14509,0 25556 25610 ) 25557 *92 4(LeafLogPort25611 *922 (LeafLogPort 25558 25612 port (LogicalPort 25559 25613 m 1 … … 25569 25623 uid 14634,0 25570 25624 ) 25571 *92 5(LeafLogPort25625 *923 (LeafLogPort 25572 25626 port (LogicalPort 25573 25627 m 4 … … 25584 25638 uid 15144,0 25585 25639 ) 25586 *92 6(LeafLogPort25640 *924 (LeafLogPort 25587 25641 port (LogicalPort 25588 25642 m 4 … … 25599 25653 uid 15146,0 25600 25654 ) 25601 *92 7(LeafLogPort25655 *925 (LeafLogPort 25602 25656 port (LogicalPort 25603 25657 m 4 … … 25614 25668 uid 15148,0 25615 25669 ) 25670 *926 (LeafLogPort 25671 port (LogicalPort 25672 m 4 25673 decl (Decl 25674 n "trigger_out" 25675 t "std_logic" 25676 o 123 25677 suid 301,0 25678 i "'0'" 25679 ) 25680 ) 25681 uid 15504,0 25682 ) 25616 25683 ] 25617 25684 ) … … 25621 25688 uid 67,0 25622 25689 optionalChildren [ 25623 *92 8(Sheet25690 *927 (Sheet 25624 25691 sheetRow (SheetRow 25625 25692 headerVa (MVa … … 25638 25705 font "Tahoma,10,0" 25639 25706 ) 25640 emptyMRCItem *92 9(MRCItem25641 litem &79 225707 emptyMRCItem *928 (MRCItem 25708 litem &791 25642 25709 pos 123 25643 25710 dimension 20 … … 25645 25712 uid 69,0 25646 25713 optionalChildren [ 25647 *9 30(MRCItem25648 litem &79 325714 *929 (MRCItem 25715 litem &792 25649 25716 pos 0 25650 25717 dimension 20 25651 25718 uid 70,0 25652 25719 ) 25653 *93 1(MRCItem25654 litem &79 425720 *930 (MRCItem 25721 litem &793 25655 25722 pos 1 25656 25723 dimension 23 25657 25724 uid 71,0 25658 25725 ) 25659 *93 2(MRCItem25660 litem &79 525726 *931 (MRCItem 25727 litem &794 25661 25728 pos 2 25662 25729 hidden 1 … … 25664 25731 uid 72,0 25665 25732 ) 25666 *93 3(MRCItem25667 litem &80 525733 *932 (MRCItem 25734 litem &804 25668 25735 pos 37 25669 25736 dimension 20 25670 25737 uid 517,0 25671 25738 ) 25672 *93 4(MRCItem25673 litem &80 625739 *933 (MRCItem 25740 litem &805 25674 25741 pos 38 25675 25742 dimension 20 25676 25743 uid 519,0 25677 25744 ) 25678 *93 5(MRCItem25679 litem &80 725745 *934 (MRCItem 25746 litem &806 25680 25747 pos 39 25681 25748 dimension 20 25682 25749 uid 521,0 25683 25750 ) 25684 *93 6(MRCItem25685 litem &80 825751 *935 (MRCItem 25752 litem &807 25686 25753 pos 40 25687 25754 dimension 20 25688 25755 uid 531,0 25689 25756 ) 25690 *93 7(MRCItem25691 litem &80 925757 *936 (MRCItem 25758 litem &808 25692 25759 pos 41 25693 25760 dimension 20 25694 25761 uid 533,0 25695 25762 ) 25696 *93 8(MRCItem25697 litem &8 1025763 *937 (MRCItem 25764 litem &809 25698 25765 pos 0 25699 25766 dimension 20 25700 25767 uid 535,0 25701 25768 ) 25702 *93 9(MRCItem25703 litem &81 125769 *938 (MRCItem 25770 litem &810 25704 25771 pos 1 25705 25772 dimension 20 25706 25773 uid 537,0 25707 25774 ) 25708 *9 40(MRCItem25709 litem &81 225775 *939 (MRCItem 25776 litem &811 25710 25777 pos 2 25711 25778 dimension 20 25712 25779 uid 539,0 25713 25780 ) 25714 *94 1(MRCItem25715 litem &81 325781 *940 (MRCItem 25782 litem &812 25716 25783 pos 3 25717 25784 dimension 20 25718 25785 uid 541,0 25719 25786 ) 25720 *94 2(MRCItem25721 litem &81 425787 *941 (MRCItem 25788 litem &813 25722 25789 pos 4 25723 25790 dimension 20 25724 25791 uid 543,0 25725 25792 ) 25726 *94 3(MRCItem25727 litem &81 525793 *942 (MRCItem 25794 litem &814 25728 25795 pos 5 25729 25796 dimension 20 25730 25797 uid 547,0 25731 25798 ) 25732 *94 4(MRCItem25733 litem &81 625799 *943 (MRCItem 25800 litem &815 25734 25801 pos 6 25735 25802 dimension 20 25736 25803 uid 549,0 25737 25804 ) 25738 *94 5(MRCItem25739 litem &81 725805 *944 (MRCItem 25806 litem &816 25740 25807 pos 8 25741 25808 dimension 20 25742 25809 uid 1456,0 25743 25810 ) 25744 *94 6(MRCItem25745 litem &81 825811 *945 (MRCItem 25812 litem &817 25746 25813 pos 7 25747 25814 dimension 20 25748 25815 uid 1458,0 25749 25816 ) 25750 *94 7(MRCItem25751 litem &81 925817 *946 (MRCItem 25818 litem &818 25752 25819 pos 9 25753 25820 dimension 20 25754 25821 uid 1695,0 25755 25822 ) 25756 *94 8(MRCItem25757 litem &8 2025823 *947 (MRCItem 25824 litem &819 25758 25825 pos 42 25759 25826 dimension 20 25760 25827 uid 1994,0 25761 25828 ) 25762 *94 9(MRCItem25763 litem &82 125829 *948 (MRCItem 25830 litem &820 25764 25831 pos 43 25765 25832 dimension 20 25766 25833 uid 2306,0 25767 25834 ) 25768 *9 50(MRCItem25769 litem &82 225835 *949 (MRCItem 25836 litem &821 25770 25837 pos 44 25771 25838 dimension 20 25772 25839 uid 2511,0 25773 25840 ) 25774 *95 1(MRCItem25775 litem &82 325841 *950 (MRCItem 25842 litem &822 25776 25843 pos 45 25777 25844 dimension 20 25778 25845 uid 2513,0 25779 25846 ) 25780 *95 2(MRCItem25781 litem &82 425847 *951 (MRCItem 25848 litem &823 25782 25849 pos 46 25783 25850 dimension 20 25784 25851 uid 2515,0 25785 25852 ) 25786 *95 3(MRCItem25787 litem &82 525853 *952 (MRCItem 25854 litem &824 25788 25855 pos 47 25789 25856 dimension 20 25790 25857 uid 2517,0 25791 25858 ) 25792 *95 4(MRCItem25793 litem &82 625859 *953 (MRCItem 25860 litem &825 25794 25861 pos 48 25795 25862 dimension 20 25796 25863 uid 2519,0 25797 25864 ) 25798 *95 5(MRCItem25799 litem &82 725865 *954 (MRCItem 25866 litem &826 25800 25867 pos 49 25801 25868 dimension 20 25802 25869 uid 2521,0 25803 25870 ) 25804 *95 6(MRCItem25805 litem &82 825871 *955 (MRCItem 25872 litem &827 25806 25873 pos 50 25807 25874 dimension 20 25808 25875 uid 2523,0 25809 25876 ) 25810 *95 7(MRCItem25811 litem &82 925877 *956 (MRCItem 25878 litem &828 25812 25879 pos 51 25813 25880 dimension 20 25814 25881 uid 2605,0 25815 25882 ) 25816 *95 8(MRCItem25817 litem &8 3025883 *957 (MRCItem 25884 litem &829 25818 25885 pos 52 25819 25886 dimension 20 25820 25887 uid 2607,0 25821 25888 ) 25822 *95 9(MRCItem25823 litem &83 125889 *958 (MRCItem 25890 litem &830 25824 25891 pos 53 25825 25892 dimension 20 25826 25893 uid 2609,0 25827 25894 ) 25828 *9 60(MRCItem25829 litem &83 225895 *959 (MRCItem 25896 litem &831 25830 25897 pos 54 25831 25898 dimension 20 25832 25899 uid 2611,0 25833 25900 ) 25834 *96 1(MRCItem25835 litem &83 325901 *960 (MRCItem 25902 litem &832 25836 25903 pos 55 25837 25904 dimension 20 25838 25905 uid 2613,0 25839 25906 ) 25840 *96 2(MRCItem25841 litem &83 425907 *961 (MRCItem 25908 litem &833 25842 25909 pos 56 25843 25910 dimension 20 25844 25911 uid 2647,0 25845 25912 ) 25846 *96 3(MRCItem25847 litem &83 525913 *962 (MRCItem 25914 litem &834 25848 25915 pos 10 25849 25916 dimension 20 25850 25917 uid 2813,0 25851 25918 ) 25852 *96 4(MRCItem25853 litem &83 625919 *963 (MRCItem 25920 litem &835 25854 25921 pos 57 25855 25922 dimension 20 25856 25923 uid 2963,0 25857 25924 ) 25858 *96 5(MRCItem25859 litem &83 725925 *964 (MRCItem 25926 litem &836 25860 25927 pos 11 25861 25928 dimension 20 25862 25929 uid 3903,0 25863 25930 ) 25864 *96 6(MRCItem25865 litem &83 825931 *965 (MRCItem 25932 litem &837 25866 25933 pos 12 25867 25934 dimension 20 25868 25935 uid 4071,0 25869 25936 ) 25870 *96 7(MRCItem25871 litem &83 925937 *966 (MRCItem 25938 litem &838 25872 25939 pos 58 25873 25940 dimension 20 25874 25941 uid 4213,0 25875 25942 ) 25876 *96 8(MRCItem25877 litem &8 4025943 *967 (MRCItem 25944 litem &839 25878 25945 pos 13 25879 25946 dimension 20 25880 25947 uid 4235,0 25881 25948 ) 25882 *96 9(MRCItem25883 litem &84 125949 *968 (MRCItem 25950 litem &840 25884 25951 pos 14 25885 25952 dimension 20 25886 25953 uid 4263,0 25887 25954 ) 25888 *9 70(MRCItem25889 litem &84 225955 *969 (MRCItem 25956 litem &841 25890 25957 pos 15 25891 25958 dimension 20 25892 25959 uid 4277,0 25893 25960 ) 25894 *97 1(MRCItem25895 litem &84 325961 *970 (MRCItem 25962 litem &842 25896 25963 pos 59 25897 25964 dimension 20 25898 25965 uid 4564,0 25899 25966 ) 25900 *97 2(MRCItem25901 litem &84 425967 *971 (MRCItem 25968 litem &843 25902 25969 pos 60 25903 25970 dimension 20 25904 25971 uid 4566,0 25905 25972 ) 25906 *97 3(MRCItem25907 litem &84 525973 *972 (MRCItem 25974 litem &844 25908 25975 pos 61 25909 25976 dimension 20 25910 25977 uid 4570,0 25911 25978 ) 25912 *97 4(MRCItem25913 litem &84 625979 *973 (MRCItem 25980 litem &845 25914 25981 pos 16 25915 25982 dimension 20 25916 25983 uid 4586,0 25917 25984 ) 25918 *97 5(MRCItem25919 litem &84 725985 *974 (MRCItem 25986 litem &846 25920 25987 pos 17 25921 25988 dimension 20 25922 25989 uid 4588,0 25923 25990 ) 25924 *97 6(MRCItem25925 litem &84 825991 *975 (MRCItem 25992 litem &847 25926 25993 pos 18 25927 25994 dimension 20 25928 25995 uid 4734,0 25929 25996 ) 25930 *97 7(MRCItem25931 litem &84 925997 *976 (MRCItem 25998 litem &848 25932 25999 pos 19 25933 26000 dimension 20 25934 26001 uid 4736,0 25935 26002 ) 25936 *97 8(MRCItem25937 litem &8 5026003 *977 (MRCItem 26004 litem &849 25938 26005 pos 20 25939 26006 dimension 20 25940 26007 uid 4738,0 25941 26008 ) 25942 *97 9(MRCItem25943 litem &85 126009 *978 (MRCItem 26010 litem &850 25944 26011 pos 21 25945 26012 dimension 20 25946 26013 uid 4740,0 25947 26014 ) 25948 *9 80(MRCItem25949 litem &85 226015 *979 (MRCItem 26016 litem &851 25950 26017 pos 62 25951 26018 dimension 20 25952 26019 uid 4750,0 25953 26020 ) 25954 *98 1(MRCItem25955 litem &85 326021 *980 (MRCItem 26022 litem &852 25956 26023 pos 22 25957 26024 dimension 20 25958 26025 uid 4975,0 25959 26026 ) 25960 *98 2(MRCItem25961 litem &85 426027 *981 (MRCItem 26028 litem &853 25962 26029 pos 23 25963 26030 dimension 20 25964 26031 uid 4977,0 25965 26032 ) 25966 *98 3(MRCItem25967 litem &85 526033 *982 (MRCItem 26034 litem &854 25968 26035 pos 63 25969 26036 dimension 20 25970 26037 uid 5199,0 25971 26038 ) 25972 *98 4(MRCItem25973 litem &85 626039 *983 (MRCItem 26040 litem &855 25974 26041 pos 64 25975 26042 dimension 20 25976 26043 uid 5201,0 25977 26044 ) 25978 *98 5(MRCItem25979 litem &85 726045 *984 (MRCItem 26046 litem &856 25980 26047 pos 65 25981 26048 dimension 20 25982 26049 uid 5203,0 25983 26050 ) 25984 *98 6(MRCItem25985 litem &85 826051 *985 (MRCItem 26052 litem &857 25986 26053 pos 66 25987 26054 dimension 20 25988 26055 uid 5205,0 25989 26056 ) 25990 *98 7(MRCItem25991 litem &85 926057 *986 (MRCItem 26058 litem &858 25992 26059 pos 67 25993 26060 dimension 20 25994 26061 uid 5207,0 25995 26062 ) 25996 *98 8(MRCItem25997 litem &8 6026063 *987 (MRCItem 26064 litem &859 25998 26065 pos 68 25999 26066 dimension 20 26000 26067 uid 5209,0 26001 26068 ) 26002 *98 9(MRCItem26003 litem &86 126069 *988 (MRCItem 26070 litem &860 26004 26071 pos 69 26005 26072 dimension 20 26006 26073 uid 5211,0 26007 26074 ) 26008 *9 90(MRCItem26009 litem &86 226075 *989 (MRCItem 26076 litem &861 26010 26077 pos 70 26011 26078 dimension 20 26012 26079 uid 5213,0 26013 26080 ) 26014 *99 1(MRCItem26015 litem &86 326081 *990 (MRCItem 26082 litem &862 26016 26083 pos 71 26017 26084 dimension 20 26018 26085 uid 5215,0 26019 26086 ) 26020 *99 2(MRCItem26021 litem &86 426087 *991 (MRCItem 26088 litem &863 26022 26089 pos 24 26023 26090 dimension 20 26024 26091 uid 5227,0 26025 26092 ) 26026 *99 3(MRCItem26027 litem &86 526093 *992 (MRCItem 26094 litem &864 26028 26095 pos 72 26029 26096 dimension 20 26030 26097 uid 5503,0 26031 26098 ) 26032 *99 4(MRCItem26033 litem &86 626099 *993 (MRCItem 26100 litem &865 26034 26101 pos 73 26035 26102 dimension 20 26036 26103 uid 5505,0 26037 26104 ) 26038 *99 5(MRCItem26039 litem &86 726105 *994 (MRCItem 26106 litem &866 26040 26107 pos 74 26041 26108 dimension 20 26042 26109 uid 5601,0 26043 26110 ) 26044 *99 6(MRCItem26045 litem &86 826111 *995 (MRCItem 26112 litem &867 26046 26113 pos 75 26047 26114 dimension 20 26048 26115 uid 5643,0 26049 26116 ) 26050 *99 7(MRCItem26051 litem &86 926117 *996 (MRCItem 26118 litem &868 26052 26119 pos 76 26053 26120 dimension 20 26054 26121 uid 5645,0 26055 26122 ) 26056 *99 8(MRCItem26057 litem &8 7026123 *997 (MRCItem 26124 litem &869 26058 26125 pos 77 26059 26126 dimension 20 26060 26127 uid 5752,0 26061 26128 ) 26062 *99 9(MRCItem26063 litem &87 126129 *998 (MRCItem 26130 litem &870 26064 26131 pos 25 26065 26132 dimension 20 26066 26133 uid 5868,0 26067 26134 ) 26068 * 1000(MRCItem26069 litem &87 226135 *999 (MRCItem 26136 litem &871 26070 26137 pos 26 26071 26138 dimension 20 26072 26139 uid 5870,0 26073 26140 ) 26074 *100 1(MRCItem26075 litem &87 326141 *1000 (MRCItem 26142 litem &872 26076 26143 pos 27 26077 26144 dimension 20 26078 26145 uid 5872,0 26079 26146 ) 26080 *100 2(MRCItem26081 litem &87 426147 *1001 (MRCItem 26148 litem &873 26082 26149 pos 28 26083 26150 dimension 20 26084 26151 uid 5874,0 26085 26152 ) 26086 *100 3(MRCItem26087 litem &87 526153 *1002 (MRCItem 26154 litem &874 26088 26155 pos 78 26089 26156 dimension 20 26090 26157 uid 5967,0 26091 26158 ) 26092 *100 4(MRCItem26093 litem &87 626159 *1003 (MRCItem 26160 litem &875 26094 26161 pos 79 26095 26162 dimension 20 26096 26163 uid 5969,0 26097 26164 ) 26098 *100 5(MRCItem26099 litem &87 726165 *1004 (MRCItem 26166 litem &876 26100 26167 pos 80 26101 26168 dimension 20 26102 26169 uid 6023,0 26103 26170 ) 26104 *100 6(MRCItem26105 litem &87 826171 *1005 (MRCItem 26172 litem &877 26106 26173 pos 81 26107 26174 dimension 20 26108 26175 uid 6025,0 26109 26176 ) 26110 *100 7(MRCItem26111 litem &87 926177 *1006 (MRCItem 26178 litem &878 26112 26179 pos 82 26113 26180 dimension 20 26114 26181 uid 6027,0 26115 26182 ) 26116 *100 8(MRCItem26117 litem &8 8026183 *1007 (MRCItem 26184 litem &879 26118 26185 pos 29 26119 26186 dimension 20 26120 26187 uid 6173,0 26121 26188 ) 26122 *100 9(MRCItem26123 litem &88 126189 *1008 (MRCItem 26190 litem &880 26124 26191 pos 30 26125 26192 dimension 20 26126 26193 uid 6375,0 26127 26194 ) 26128 *10 10(MRCItem26129 litem &88 226195 *1009 (MRCItem 26196 litem &881 26130 26197 pos 83 26131 26198 dimension 20 26132 26199 uid 6465,0 26133 26200 ) 26134 *101 1(MRCItem26135 litem &88 326201 *1010 (MRCItem 26202 litem &882 26136 26203 pos 84 26137 26204 dimension 20 26138 26205 uid 6555,0 26139 26206 ) 26140 *101 2(MRCItem26141 litem &88 426207 *1011 (MRCItem 26208 litem &883 26142 26209 pos 85 26143 26210 dimension 20 26144 26211 uid 8421,0 26145 26212 ) 26146 *101 3(MRCItem26147 litem &88 526213 *1012 (MRCItem 26214 litem &884 26148 26215 pos 86 26149 26216 dimension 20 26150 26217 uid 8759,0 26151 26218 ) 26152 *101 4(MRCItem26153 litem &88 626219 *1013 (MRCItem 26220 litem &885 26154 26221 pos 87 26155 26222 dimension 20 26156 26223 uid 8761,0 26157 26224 ) 26158 *101 5(MRCItem26159 litem &88 726225 *1014 (MRCItem 26226 litem &886 26160 26227 pos 31 26161 26228 dimension 20 26162 26229 uid 9019,0 26163 26230 ) 26164 *101 6(MRCItem26165 litem &88 826231 *1015 (MRCItem 26232 litem &887 26166 26233 pos 88 26167 26234 dimension 20 26168 26235 uid 9248,0 26169 26236 ) 26170 *101 7(MRCItem26171 litem &88 926237 *1016 (MRCItem 26238 litem &888 26172 26239 pos 89 26173 26240 dimension 20 26174 26241 uid 9250,0 26175 26242 ) 26176 *101 8(MRCItem26177 litem &8 9026243 *1017 (MRCItem 26244 litem &889 26178 26245 pos 90 26179 26246 dimension 20 26180 26247 uid 10025,0 26181 26248 ) 26182 *101 9(MRCItem26183 litem &89 126249 *1018 (MRCItem 26250 litem &890 26184 26251 pos 91 26185 26252 dimension 20 26186 26253 uid 10027,0 26187 26254 ) 26188 *10 20(MRCItem26189 litem &89 226255 *1019 (MRCItem 26256 litem &891 26190 26257 pos 92 26191 26258 dimension 20 26192 26259 uid 10029,0 26193 26260 ) 26194 *102 1(MRCItem26195 litem &89 326261 *1020 (MRCItem 26262 litem &892 26196 26263 pos 93 26197 26264 dimension 20 26198 26265 uid 10209,0 26199 26266 ) 26200 *102 2(MRCItem26201 litem &89 426267 *1021 (MRCItem 26268 litem &893 26202 26269 pos 94 26203 26270 dimension 20 26204 26271 uid 10211,0 26205 26272 ) 26206 *102 3(MRCItem26207 litem &89 526273 *1022 (MRCItem 26274 litem &894 26208 26275 pos 95 26209 26276 dimension 20 26210 26277 uid 10295,0 26211 26278 ) 26212 *102 4(MRCItem26213 litem &89 626279 *1023 (MRCItem 26280 litem &895 26214 26281 pos 96 26215 26282 dimension 20 26216 26283 uid 10335,0 26217 26284 ) 26218 *102 5(MRCItem26219 litem &89 726285 *1024 (MRCItem 26286 litem &896 26220 26287 pos 97 26221 26288 dimension 20 26222 26289 uid 10337,0 26223 26290 ) 26224 *102 6(MRCItem26225 litem &89 826291 *1025 (MRCItem 26292 litem &897 26226 26293 pos 98 26227 26294 dimension 20 26228 26295 uid 10339,0 26229 26296 ) 26230 *102 7(MRCItem26231 litem &89 926297 *1026 (MRCItem 26298 litem &898 26232 26299 pos 99 26233 26300 dimension 20 26234 26301 uid 10341,0 26235 26302 ) 26236 *102 8(MRCItem26237 litem & 90026303 *1027 (MRCItem 26304 litem &899 26238 26305 pos 32 26239 26306 dimension 20 26240 26307 uid 10343,0 26241 26308 ) 26309 *1028 (MRCItem 26310 litem &900 26311 pos 100 26312 dimension 20 26313 uid 10476,0 26314 ) 26242 26315 *1029 (MRCItem 26243 26316 litem &901 26244 pos 10 026317 pos 101 26245 26318 dimension 20 26246 uid 10 474,026319 uid 10764,0 26247 26320 ) 26248 26321 *1030 (MRCItem 26249 26322 litem &902 26250 pos 10 126323 pos 102 26251 26324 dimension 20 26252 uid 10 476,026325 uid 10766,0 26253 26326 ) 26254 26327 *1031 (MRCItem 26255 26328 litem &903 26256 pos 10226257 dimension 2026258 uid 10764,026259 )26260 *1032 (MRCItem26261 litem &90426262 pos 10326263 dimension 2026264 uid 10766,026265 )26266 *1033 (MRCItem26267 litem &90526268 26329 pos 33 26269 26330 dimension 20 26270 26331 uid 10768,0 26271 26332 ) 26272 *103 4(MRCItem26273 litem &90 626333 *1032 (MRCItem 26334 litem &904 26274 26335 pos 34 26275 26336 dimension 20 26276 26337 uid 10770,0 26277 26338 ) 26278 *103 5(MRCItem26279 litem &90 726339 *1033 (MRCItem 26340 litem &905 26280 26341 pos 35 26281 26342 dimension 20 26282 26343 uid 10772,0 26283 26344 ) 26345 *1034 (MRCItem 26346 litem &906 26347 pos 103 26348 dimension 20 26349 uid 11412,0 26350 ) 26351 *1035 (MRCItem 26352 litem &907 26353 pos 104 26354 dimension 20 26355 uid 11967,0 26356 ) 26284 26357 *1036 (MRCItem 26285 26358 litem &908 26286 pos 10 426359 pos 105 26287 26360 dimension 20 26288 uid 1 1412,026361 uid 12311,0 26289 26362 ) 26290 26363 *1037 (MRCItem 26291 26364 litem &909 26292 pos 10 526365 pos 106 26293 26366 dimension 20 26294 uid 1 1967,026367 uid 12660,0 26295 26368 ) 26296 26369 *1038 (MRCItem 26297 26370 litem &910 26298 pos 10 626371 pos 107 26299 26372 dimension 20 26300 uid 12 311,026373 uid 12662,0 26301 26374 ) 26302 26375 *1039 (MRCItem 26303 26376 litem &911 26304 pos 10 726377 pos 108 26305 26378 dimension 20 26306 uid 1266 0,026379 uid 12664,0 26307 26380 ) 26308 26381 *1040 (MRCItem 26309 26382 litem &912 26310 pos 10826383 pos 36 26311 26384 dimension 20 26312 uid 12 662,026385 uid 12720,0 26313 26386 ) 26314 26387 *1041 (MRCItem … … 26316 26389 pos 109 26317 26390 dimension 20 26318 uid 1 2664,026391 uid 13276,0 26319 26392 ) 26320 26393 *1042 (MRCItem 26321 26394 litem &914 26322 pos 3626395 pos 110 26323 26396 dimension 20 26324 uid 1 2720,026397 uid 13278,0 26325 26398 ) 26326 26399 *1043 (MRCItem 26327 26400 litem &915 26328 pos 11 026401 pos 111 26329 26402 dimension 20 26330 uid 132 76,026403 uid 13280,0 26331 26404 ) 26332 26405 *1044 (MRCItem 26333 26406 litem &916 26334 pos 11 126407 pos 112 26335 26408 dimension 20 26336 uid 132 78,026409 uid 13282,0 26337 26410 ) 26338 26411 *1045 (MRCItem 26339 26412 litem &917 26340 pos 11 226413 pos 113 26341 26414 dimension 20 26342 uid 13 280,026415 uid 13688,0 26343 26416 ) 26344 26417 *1046 (MRCItem 26345 26418 litem &918 26346 pos 11 326419 pos 114 26347 26420 dimension 20 26348 uid 1 3282,026421 uid 14041,0 26349 26422 ) 26350 26423 *1047 (MRCItem 26351 26424 litem &919 26352 pos 11 426425 pos 115 26353 26426 dimension 20 26354 uid 1 3688,026427 uid 14164,0 26355 26428 ) 26356 26429 *1048 (MRCItem 26357 26430 litem &920 26358 pos 11 526431 pos 116 26359 26432 dimension 20 26360 uid 14 041,026433 uid 14508,0 26361 26434 ) 26362 26435 *1049 (MRCItem 26363 26436 litem &921 26364 pos 11 626437 pos 117 26365 26438 dimension 20 26366 uid 14 164,026439 uid 14510,0 26367 26440 ) 26368 26441 *1050 (MRCItem 26369 26442 litem &922 26370 pos 11 726443 pos 118 26371 26444 dimension 20 26372 uid 14 508,026445 uid 14635,0 26373 26446 ) 26374 26447 *1051 (MRCItem 26375 26448 litem &923 26376 pos 11 826449 pos 119 26377 26450 dimension 20 26378 uid 1 4510,026451 uid 15145,0 26379 26452 ) 26380 26453 *1052 (MRCItem 26381 26454 litem &924 26382 pos 1 1926455 pos 120 26383 26456 dimension 20 26384 uid 1 4635,026457 uid 15147,0 26385 26458 ) 26386 26459 *1053 (MRCItem 26387 26460 litem &925 26388 pos 12 026461 pos 121 26389 26462 dimension 20 26390 uid 1514 5,026463 uid 15149,0 26391 26464 ) 26392 26465 *1054 (MRCItem 26393 26466 litem &926 26394 pos 12126395 dimension 2026396 uid 15147,026397 )26398 *1055 (MRCItem26399 litem &92726400 26467 pos 122 26401 26468 dimension 20 26402 uid 15 149,026469 uid 15505,0 26403 26470 ) 26404 26471 ] … … 26413 26480 uid 73,0 26414 26481 optionalChildren [ 26415 *105 6(MRCItem26416 litem &79 626482 *1055 (MRCItem 26483 litem &795 26417 26484 pos 0 26418 26485 dimension 20 26419 26486 uid 74,0 26420 26487 ) 26421 *105 7(MRCItem26422 litem &79 826488 *1056 (MRCItem 26489 litem &797 26423 26490 pos 1 26424 26491 dimension 50 26425 26492 uid 75,0 26426 26493 ) 26427 *105 8(MRCItem26428 litem &79 926494 *1057 (MRCItem 26495 litem &798 26429 26496 pos 2 26430 26497 dimension 100 26431 26498 uid 76,0 26432 26499 ) 26433 *105 9(MRCItem26434 litem & 80026500 *1058 (MRCItem 26501 litem &799 26435 26502 pos 3 26436 26503 dimension 50 26437 26504 uid 77,0 26438 26505 ) 26439 *10 60(MRCItem26440 litem &80 126506 *1059 (MRCItem 26507 litem &800 26441 26508 pos 4 26442 26509 dimension 100 26443 26510 uid 78,0 26444 26511 ) 26445 *106 1(MRCItem26446 litem &80 226512 *1060 (MRCItem 26513 litem &801 26447 26514 pos 5 26448 26515 dimension 100 26449 26516 uid 79,0 26450 26517 ) 26451 *106 2(MRCItem26452 litem &80 326518 *1061 (MRCItem 26519 litem &802 26453 26520 pos 6 26454 26521 dimension 50 26455 26522 uid 80,0 26456 26523 ) 26457 *106 3(MRCItem26458 litem &80 426524 *1062 (MRCItem 26525 litem &803 26459 26526 pos 7 26460 26527 dimension 290 … … 26476 26543 genericsCommonDM (CommonDM 26477 26544 ldm (LogicalDM 26478 emptyRow *106 4(LEmptyRow26545 emptyRow *1063 (LEmptyRow 26479 26546 ) 26480 26547 uid 83,0 26481 26548 optionalChildren [ 26482 *106 5(RefLabelRowHdr26483 ) 26484 *106 6(TitleRowHdr26485 ) 26486 *106 7(FilterRowHdr26487 ) 26488 *106 8(RefLabelColHdr26549 *1064 (RefLabelRowHdr 26550 ) 26551 *1065 (TitleRowHdr 26552 ) 26553 *1066 (FilterRowHdr 26554 ) 26555 *1067 (RefLabelColHdr 26489 26556 tm "RefLabelColHdrMgr" 26490 26557 ) 26491 *106 9(RowExpandColHdr26558 *1068 (RowExpandColHdr 26492 26559 tm "RowExpandColHdrMgr" 26493 26560 ) 26494 *10 70(GroupColHdr26561 *1069 (GroupColHdr 26495 26562 tm "GroupColHdrMgr" 26496 26563 ) 26497 *107 1(NameColHdr26564 *1070 (NameColHdr 26498 26565 tm "GenericNameColHdrMgr" 26499 26566 ) 26500 *107 2(TypeColHdr26567 *1071 (TypeColHdr 26501 26568 tm "GenericTypeColHdrMgr" 26502 26569 ) 26503 *107 3(InitColHdr26570 *1072 (InitColHdr 26504 26571 tm "GenericValueColHdrMgr" 26505 26572 ) 26506 *107 4(PragmaColHdr26573 *1073 (PragmaColHdr 26507 26574 tm "GenericPragmaColHdrMgr" 26508 26575 ) 26509 *107 5(EolColHdr26576 *1074 (EolColHdr 26510 26577 tm "GenericEolColHdrMgr" 26511 26578 ) 26512 *107 6(LogGeneric26579 *1075 (LogGeneric 26513 26580 generic (GiElement 26514 26581 name "RAMADDRWIDTH64b" … … 26525 26592 uid 95,0 26526 26593 optionalChildren [ 26527 *107 7(Sheet26594 *1076 (Sheet 26528 26595 sheetRow (SheetRow 26529 26596 headerVa (MVa … … 26542 26609 font "Tahoma,10,0" 26543 26610 ) 26544 emptyMRCItem *107 8(MRCItem26545 litem &106 426611 emptyMRCItem *1077 (MRCItem 26612 litem &1063 26546 26613 pos 1 26547 26614 dimension 20 … … 26549 26616 uid 97,0 26550 26617 optionalChildren [ 26551 *107 9(MRCItem26552 litem &106 526618 *1078 (MRCItem 26619 litem &1064 26553 26620 pos 0 26554 26621 dimension 20 26555 26622 uid 98,0 26556 26623 ) 26557 *10 80(MRCItem26558 litem &106 626624 *1079 (MRCItem 26625 litem &1065 26559 26626 pos 1 26560 26627 dimension 23 26561 26628 uid 99,0 26562 26629 ) 26563 *108 1(MRCItem26564 litem &106 726630 *1080 (MRCItem 26631 litem &1066 26565 26632 pos 2 26566 26633 hidden 1 … … 26568 26635 uid 100,0 26569 26636 ) 26570 *108 2(MRCItem26571 litem &107 626637 *1081 (MRCItem 26638 litem &1075 26572 26639 pos 0 26573 26640 dimension 20 … … 26585 26652 uid 101,0 26586 26653 optionalChildren [ 26587 *108 3(MRCItem26588 litem &106 826654 *1082 (MRCItem 26655 litem &1067 26589 26656 pos 0 26590 26657 dimension 20 26591 26658 uid 102,0 26592 26659 ) 26593 *108 4(MRCItem26594 litem &10 7026660 *1083 (MRCItem 26661 litem &1069 26595 26662 pos 1 26596 26663 dimension 50 26597 26664 uid 103,0 26598 26665 ) 26599 *108 5(MRCItem26600 litem &107 126666 *1084 (MRCItem 26667 litem &1070 26601 26668 pos 2 26602 26669 dimension 186 26603 26670 uid 104,0 26604 26671 ) 26605 *108 6(MRCItem26606 litem &107 226672 *1085 (MRCItem 26673 litem &1071 26607 26674 pos 3 26608 26675 dimension 96 26609 26676 uid 105,0 26610 26677 ) 26611 *108 7(MRCItem26612 litem &107 326678 *1086 (MRCItem 26679 litem &1072 26613 26680 pos 4 26614 26681 dimension 50 26615 26682 uid 106,0 26616 26683 ) 26617 *108 8(MRCItem26618 litem &107 426684 *1087 (MRCItem 26685 litem &1073 26619 26686 pos 5 26620 26687 dimension 50 26621 26688 uid 107,0 26622 26689 ) 26623 *108 9(MRCItem26624 litem &107 526690 *1088 (MRCItem 26691 litem &1074 26625 26692 pos 6 26626 26693 dimension 80 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak
r10129 r10138 333 333 (vvPair 334 334 variable "date" 335 value "0 4.02.2011"335 value "08.02.2011" 336 336 ) 337 337 (vvPair 338 338 variable "day" 339 value " Fr"339 value "Di" 340 340 ) 341 341 (vvPair 342 342 variable "day_long" 343 value " Freitag"343 value "Dienstag" 344 344 ) 345 345 (vvPair 346 346 variable "dd" 347 value "0 4"347 value "08" 348 348 ) 349 349 (vvPair … … 485 485 (vvPair 486 486 variable "time" 487 value "11: 32:44"487 value "11:05:26" 488 488 ) 489 489 (vvPair … … 576 576 font "Courier New,8,0" 577 577 ) 578 xt "-172000,106 800,-128500,107600"578 xt "-172000,106000,-128500,106800" 579 579 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\" 580 580 " … … 1303 1303 fg "0,65535,0" 1304 1304 ) 1305 xt "0, 65625,750,66375"1305 xt "0,70625,750,71375" 1306 1306 ) 1307 1307 tg (CPTG … … 1313 1313 va (VaSet 1314 1314 ) 1315 xt "-17300, 65500,-1000,66500"1315 xt "-17300,70500,-1000,71500" 1316 1316 st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)" 1317 1317 ju 2 1318 blo "-1000, 66300"1318 blo "-1000,71300" 1319 1319 ) 1320 1320 ) … … 1378 1378 fg "0,65535,0" 1379 1379 ) 1380 xt "-21750, 70625,-21000,71375"1380 xt "-21750,69625,-21000,70375" 1381 1381 ) 1382 1382 tg (CPTG … … 1388 1388 va (VaSet 1389 1389 ) 1390 xt "-20000, 70500,-13200,71500"1390 xt "-20000,69500,-13200,70500" 1391 1391 st "trigger_id : (47:0)" 1392 blo "-20000,7 1300"1392 blo "-20000,70300" 1393 1393 ) 1394 1394 ) … … 1486 1486 fg "0,65535,0" 1487 1487 ) 1488 xt "0, 66625,750,67375"1488 xt "0,71625,750,72375" 1489 1489 ) 1490 1490 tg (CPTG … … 1496 1496 va (VaSet 1497 1497 ) 1498 xt "-6300, 66500,-1000,67500"1498 xt "-6300,71500,-1000,72500" 1499 1499 st "ram_write_ea" 1500 1500 ju 2 1501 blo "-1000, 67300"1501 blo "-1000,72300" 1502 1502 ) 1503 1503 ) … … 1521 1521 fg "0,65535,0" 1522 1522 ) 1523 xt "0, 67625,750,68375"1523 xt "0,72625,750,73375" 1524 1524 ) 1525 1525 tg (CPTG … … 1531 1531 va (VaSet 1532 1532 ) 1533 xt "-7300, 67500,-1000,68500"1533 xt "-7300,72500,-1000,73500" 1534 1534 st "ram_write_ready" 1535 1535 ju 2 1536 blo "-1000, 68300"1536 blo "-1000,73300" 1537 1537 ) 1538 1538 ) … … 1559 1559 fg "0,65535,0" 1560 1560 ) 1561 xt "0,7 6625,750,77375"1561 xt "0,78625,750,79375" 1562 1562 ) 1563 1563 tg (CPTG … … 1569 1569 va (VaSet 1570 1570 ) 1571 xt "-4000,7 6500,-1000,77500"1571 xt "-4000,78500,-1000,79500" 1572 1572 st "roi_max" 1573 1573 ju 2 1574 blo "-1000,7 7300"1574 blo "-1000,79300" 1575 1575 ) 1576 1576 ) … … 1629 1629 fg "0,65535,0" 1630 1630 ) 1631 xt "0,7 7625,750,78375"1631 xt "0,79625,750,80375" 1632 1632 ) 1633 1633 tg (CPTG … … 1639 1639 va (VaSet 1640 1640 ) 1641 xt "-10100,7 7500,-1000,78500"1641 xt "-10100,79500,-1000,80500" 1642 1642 st "package_length : (15:0)" 1643 1643 ju 2 1644 blo "-1000, 78300"1644 blo "-1000,80300" 1645 1645 ) 1646 1646 ) … … 2028 2028 fg "0,65535,0" 2029 2029 ) 2030 xt "0,7 4625,750,75375"2030 xt "0,77625,750,78375" 2031 2031 ) 2032 2032 tg (CPTG … … 2038 2038 va (VaSet 2039 2039 ) 2040 xt "-7700,7 4500,-1000,75500"2040 xt "-7700,77500,-1000,78500" 2041 2041 st "config_ready_mm" 2042 2042 ju 2 2043 blo "-1000,7 5300"2043 blo "-1000,78300" 2044 2044 ) 2045 2045 ) … … 2168 2168 fg "0,65535,0" 2169 2169 ) 2170 xt "0,7 2625,750,73375"2170 xt "0,75625,750,76375" 2171 2171 ) 2172 2172 tg (CPTG … … 2178 2178 va (VaSet 2179 2179 ) 2180 xt "-7400,7 2500,-1000,73500"2180 xt "-7400,75500,-1000,76500" 2181 2181 st "config_start_mm" 2182 2182 ju 2 2183 blo "-1000,7 3300"2183 blo "-1000,76300" 2184 2184 ) 2185 2185 ) … … 2356 2356 fg "0,65535,0" 2357 2357 ) 2358 xt "0,7 3625,750,74375"2358 xt "0,76625,750,77375" 2359 2359 ) 2360 2360 tg (CPTG … … 2366 2366 va (VaSet 2367 2367 ) 2368 xt "-8200,7 3500,-1000,74500"2368 xt "-8200,76500,-1000,77500" 2369 2369 st "config_started_mm" 2370 2370 ju 2 2371 blo "-1000,7 4300"2371 blo "-1000,77300" 2372 2372 ) 2373 2373 ) … … 2638 2638 fg "0,65535,0" 2639 2639 ) 2640 xt "0, 68625,750,69375"2640 xt "0,73625,750,74375" 2641 2641 ) 2642 2642 tg (CPTG … … 2648 2648 va (VaSet 2649 2649 ) 2650 xt "-8800, 68500,-1000,69500"2650 xt "-8800,73500,-1000,74500" 2651 2651 st "ram_write_ready_ack" 2652 2652 ju 2 2653 blo "-1000, 69300"2653 blo "-1000,74300" 2654 2654 ) 2655 2655 ) … … 2799 2799 font "Arial,8,1" 2800 2800 ) 2801 xt "-20700,9 7000,-14500,98000"2801 xt "-20700,98000,-14500,99000" 2802 2802 st "FACT_FAD_lib" 2803 blo "-20700,9 7800"2803 blo "-20700,98800" 2804 2804 tm "BdLibraryNameMgr" 2805 2805 ) … … 2809 2809 font "Arial,8,1" 2810 2810 ) 2811 xt "-20700,9 8000,-14300,99000"2811 xt "-20700,99000,-14300,100000" 2812 2812 st "data_generator" 2813 blo "-20700,9 8800"2813 blo "-20700,99800" 2814 2814 tm "CptNameMgr" 2815 2815 ) … … 2819 2819 font "Arial,8,1" 2820 2820 ) 2821 xt "-20700, 99000,-11100,100000"2821 xt "-20700,100000,-11100,101000" 2822 2822 st "I_main_data_generator" 2823 blo "-20700, 99800"2823 blo "-20700,100800" 2824 2824 tm "InstanceNameMgr" 2825 2825 ) … … 3271 3271 fg "0,65535,0" 3272 3272 ) 3273 xt "87250,7 1625,88000,72375"3273 xt "87250,72625,88000,73375" 3274 3274 ) 3275 3275 tg (CPTG … … 3281 3281 va (VaSet 3282 3282 ) 3283 xt "89000,7 1500,96900,72500"3283 xt "89000,72500,96900,73500" 3284 3284 st "write_length : (16:0)" 3285 blo "89000,7 2300"3285 blo "89000,73300" 3286 3286 ) 3287 3287 ) … … 3308 3308 fg "0,65535,0" 3309 3309 ) 3310 xt "87250,7 2625,88000,73375"3310 xt "87250,73625,88000,74375" 3311 3311 ) 3312 3312 tg (CPTG … … 3318 3318 va (VaSet 3319 3319 ) 3320 xt "89000,7 2500,105300,73500"3320 xt "89000,73500,105300,74500" 3321 3321 st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)" 3322 blo "89000,7 3300"3322 blo "89000,74300" 3323 3323 ) 3324 3324 ) … … 3420 3420 fg "0,65535,0" 3421 3421 ) 3422 xt "87250,7 0625,88000,71375"3422 xt "87250,71625,88000,72375" 3423 3423 ) 3424 3424 tg (CPTG … … 3430 3430 va (VaSet 3431 3431 ) 3432 xt "89000,7 0500,93100,71500"3432 xt "89000,71500,93100,72500" 3433 3433 st "data_valid" 3434 blo "89000,7 1300"3434 blo "89000,72300" 3435 3435 ) 3436 3436 ) … … 3456 3456 fg "0,65535,0" 3457 3457 ) 3458 xt "87250, 69625,88000,70375"3458 xt "87250,70625,88000,71375" 3459 3459 ) 3460 3460 tg (CPTG … … 3466 3466 va (VaSet 3467 3467 ) 3468 xt "89000, 69500,90900,70500"3468 xt "89000,70500,90900,71500" 3469 3469 st "busy" 3470 blo "89000,7 0300"3470 blo "89000,71300" 3471 3471 ) 3472 3472 ) … … 3494 3494 fg "0,65535,0" 3495 3495 ) 3496 xt "87250,7 3625,88000,74375"3496 xt "87250,74625,88000,75375" 3497 3497 ) 3498 3498 tg (CPTG … … 3504 3504 va (VaSet 3505 3505 ) 3506 xt "89000,7 3500,96800,74500"3506 xt "89000,74500,96800,75500" 3507 3507 st "fifo_channels : (3:0)" 3508 blo "89000,7 4300"3508 blo "89000,75300" 3509 3509 ) 3510 3510 ) … … 3530 3530 fg "0,65535,0" 3531 3531 ) 3532 xt "87250,7 4625,88000,75375"3532 xt "87250,75625,88000,76375" 3533 3533 ) 3534 3534 tg (CPTG … … 3540 3540 va (VaSet 3541 3541 ) 3542 xt "89000,7 4500,94700,75500"3542 xt "89000,75500,94700,76500" 3543 3543 st "write_end_flag" 3544 blo "89000,7 5300"3544 blo "89000,76300" 3545 3545 ) 3546 3546 ) … … 3564 3564 fg "0,65535,0" 3565 3565 ) 3566 xt "87250,7 5625,88000,76375"3566 xt "87250,76625,88000,77375" 3567 3567 ) 3568 3568 tg (CPTG … … 3574 3574 va (VaSet 3575 3575 ) 3576 xt "89000,7 5500,95800,76500"3576 xt "89000,76500,95800,77500" 3577 3577 st "write_header_flag" 3578 blo "89000,7 6300"3578 blo "89000,77300" 3579 3579 ) 3580 3580 ) … … 4008 4008 fg "0,65535,0" 4009 4009 ) 4010 xt "87250,7 6625,88000,77375"4010 xt "87250,77625,88000,78375" 4011 4011 ) 4012 4012 tg (CPTG … … 4018 4018 va (VaSet 4019 4019 ) 4020 xt "89000,7 6500,94600,77500"4020 xt "89000,77500,94600,78500" 4021 4021 st "data_valid_ack" 4022 blo "89000,7 7300"4022 blo "89000,78300" 4023 4023 ) 4024 4024 ) … … 4718 4718 fg "0,65535,0" 4719 4719 ) 4720 xt "-41000,6 7625,-40250,68375"4720 xt "-41000,68625,-40250,69375" 4721 4721 ) 4722 4722 tg (CPTG … … 4728 4728 va (VaSet 4729 4729 ) 4730 xt "-48800,6 7500,-42000,68500"4730 xt "-48800,68500,-42000,69500" 4731 4731 st "trigger_id : (47:0)" 4732 4732 ju 2 4733 blo "-42000,6 8300"4733 blo "-42000,69300" 4734 4734 ) 4735 4735 ) … … 4758 4758 fg "0,65535,0" 4759 4759 ) 4760 xt "-52750,6 7625,-52000,68375"4760 xt "-52750,68625,-52000,69375" 4761 4761 ) 4762 4762 tg (CPTG … … 4768 4768 va (VaSet 4769 4769 ) 4770 xt "-51000,6 7500,-48200,68500"4770 xt "-51000,68500,-48200,69500" 4771 4771 st "trigger" 4772 blo "-51000,6 8300"4772 blo "-51000,69300" 4773 4773 ) 4774 4774 ) … … 4795 4795 fg "0,65535,0" 4796 4796 ) 4797 xt "-52750,6 6625,-52000,67375"4797 xt "-52750,67625,-52000,68375" 4798 4798 ) 4799 4799 tg (CPTG … … 4805 4805 va (VaSet 4806 4806 ) 4807 xt "-51000,6 6500,-49700,67500"4807 xt "-51000,67500,-49700,68500" 4808 4808 st "clk" 4809 blo "-51000,6 7300"4809 blo "-51000,68300" 4810 4810 ) 4811 4811 ) … … 4829 4829 lineWidth 2 4830 4830 ) 4831 xt "-52000,6 6000,-41000,70000"4831 xt "-52000,67000,-41000,71000" 4832 4832 ) 4833 4833 oxt "32000,2000,43000,12000" … … 4843 4843 font "Arial,8,1" 4844 4844 ) 4845 xt "-50300,7 0000,-43700,71000"4845 xt "-50300,71000,-43700,72000" 4846 4846 st "FACT_FAD_LIB" 4847 blo "-50300,7 0800"4847 blo "-50300,71800" 4848 4848 tm "BdLibraryNameMgr" 4849 4849 ) … … 4854 4854 font "Arial,8,1" 4855 4855 ) 4856 xt "-50300,7 1000,-43700,72000"4856 xt "-50300,72000,-43700,73000" 4857 4857 st "trigger_counter" 4858 blo "-50300,7 1800"4858 blo "-50300,72800" 4859 4859 tm "CptNameMgr" 4860 4860 ) … … 4865 4865 font "Arial,8,1" 4866 4866 ) 4867 xt "-50300,7 1000,-42700,72000"4867 xt "-50300,72000,-42700,73000" 4868 4868 st "I_main_ext_trigger" 4869 blo "-50300,7 1800"4869 blo "-50300,72800" 4870 4870 tm "InstanceNameMgr" 4871 4871 ) … … 4882 4882 font "Courier New,8,0" 4883 4883 ) 4884 xt "-52000,6 5000,-52000,65000"4884 xt "-52000,66000,-52000,66000" 4885 4885 ) 4886 4886 header "" … … 4896 4896 fg "49152,49152,49152" 4897 4897 ) 4898 xt "-51750,6 8250,-50250,69750"4898 xt "-51750,69250,-50250,70750" 4899 4899 iconName "VhdlFileViewIcon.png" 4900 4900 iconMaskName "VhdlFileViewIcon.msk" … … 4964 4964 fg "0,65535,0" 4965 4965 ) 4966 xt " 31250,72625,32000,73375"4966 xt "27250,70625,28000,71375" 4967 4967 ) 4968 4968 tg (CPTG … … 4975 4975 font "arial,8,0" 4976 4976 ) 4977 xt " 33000,72500,51400,73500"4977 xt "29000,70500,47400,71500" 4978 4978 st "ram_start_addr : (RAM_ADDR_WIDTH_64B-1:0)" 4979 blo " 33000,73300"4979 blo "29000,71300" 4980 4980 ) 4981 4981 ) … … 5000 5000 shape (Triangle 5001 5001 uid 2352,0 5002 ro 905002 ro 180 5003 5003 va (VaSet 5004 5004 vasetType 1 5005 5005 fg "0,65535,0" 5006 5006 ) 5007 xt " 31250,70625,32000,71375"5007 xt "28625,67250,29375,68000" 5008 5008 ) 5009 5009 tg (CPTG 5010 5010 uid 2353,0 5011 5011 ps "CptPortTextPlaceStrategy" 5012 stg " VerticalLayoutStrategy"5012 stg "RightVerticalLayoutStrategy" 5013 5013 f (Text 5014 5014 uid 2354,0 5015 ro 270 5015 5016 va (VaSet 5016 5017 font "arial,8,0" 5017 5018 ) 5018 xt " 33000,70500,34300,71500"5019 xt "28500,69000,29500,70300" 5019 5020 st "clk" 5020 blo "33000,71300" 5021 ju 2 5022 blo "29300,69000" 5021 5023 ) 5022 5024 ) … … 5041 5043 fg "0,65535,0" 5042 5044 ) 5043 xt " 31250,79625,32000,80375"5045 xt "27250,77625,28000,78375" 5044 5046 ) 5045 5047 tg (CPTG … … 5052 5054 font "arial,8,0" 5053 5055 ) 5054 xt " 33000,79500,38100,80500"5056 xt "29000,77500,34100,78500" 5055 5057 st "config_ready" 5056 blo " 33000,80300"5058 blo "29000,78300" 5057 5059 ) 5058 5060 ) … … 5079 5081 fg "0,65535,0" 5080 5082 ) 5081 xt " 31250,77625,32000,78375"5083 xt "27250,75625,28000,76375" 5082 5084 ) 5083 5085 tg (CPTG … … 5090 5092 font "arial,8,0" 5091 5093 ) 5092 xt " 33000,77500,37800,78500"5094 xt "29000,75500,33800,76500" 5093 5095 st "config_start" 5094 blo " 33000,78300"5096 blo "29000,76300" 5095 5097 ) 5096 5098 ) … … 5115 5117 fg "0,65535,0" 5116 5118 ) 5117 xt " 31250,73625,32000,74375"5119 xt "27250,71625,28000,72375" 5118 5120 ) 5119 5121 tg (CPTG … … 5126 5128 font "arial,8,0" 5127 5129 ) 5128 xt " 33000,73500,38300,74500"5130 xt "29000,71500,34300,72500" 5129 5131 st "ram_write_ea" 5130 blo " 33000,74300"5132 blo "29000,72300" 5131 5133 ) 5132 5134 ) … … 5153 5155 fg "0,65535,0" 5154 5156 ) 5155 xt " 31250,74625,32000,75375"5157 xt "27250,72625,28000,73375" 5156 5158 ) 5157 5159 tg (CPTG … … 5164 5166 font "arial,8,0" 5165 5167 ) 5166 xt " 33000,74500,39300,75500"5168 xt "29000,72500,35300,73500" 5167 5169 st "ram_write_ready" 5168 blo " 33000,75300"5170 blo "29000,73300" 5169 5171 ) 5170 5172 ) … … 5190 5192 fg "0,65535,0" 5191 5193 ) 5192 xt " 31250,80625,32000,81375"5194 xt "27250,78625,28000,79375" 5193 5195 ) 5194 5196 tg (CPTG … … 5201 5203 font "arial,8,0" 5202 5204 ) 5203 xt " 33000,80500,36000,81500"5205 xt "29000,78500,32000,79500" 5204 5206 st "roi_max" 5205 blo " 33000,81300"5207 blo "29000,79300" 5206 5208 ) 5207 5209 ) … … 5229 5231 fg "0,65535,0" 5230 5232 ) 5231 xt " 63000,70625,63750,71375"5233 xt "59000,70625,59750,71375" 5232 5234 ) 5233 5235 tg (CPTG … … 5240 5242 font "arial,8,0" 5241 5243 ) 5242 xt "5 8600,70500,62000,71500"5244 xt "54600,70500,58000,71500" 5243 5245 st "wiz_busy" 5244 5246 ju 2 5245 blo " 62000,71300"5247 blo "58000,71300" 5246 5248 ) 5247 5249 ) … … 5266 5268 fg "0,65535,0" 5267 5269 ) 5268 xt " 63000,74625,63750,75375"5270 xt "59000,74625,59750,75375" 5269 5271 ) 5270 5272 tg (CPTG … … 5277 5279 font "arial,8,0" 5278 5280 ) 5279 xt " 50200,74500,62000,75500"5281 xt "46200,74500,58000,75500" 5280 5282 st "wiz_number_of_channels : (3:0)" 5281 5283 ju 2 5282 blo " 62000,75300"5284 blo "58000,75300" 5283 5285 ) 5284 5286 ) … … 5306 5308 fg "0,65535,0" 5307 5309 ) 5308 xt " 63000,73625,63750,74375"5310 xt "59000,73625,59750,74375" 5309 5311 ) 5310 5312 tg (CPTG … … 5317 5319 font "arial,8,0" 5318 5320 ) 5319 xt " 42100,73500,62000,74500"5321 xt "38100,73500,58000,74500" 5320 5322 st "wiz_ram_start_addr : (RAM_ADDR_WIDTH_16B-1:0)" 5321 5323 ju 2 5322 blo " 62000,74300"5324 blo "58000,74300" 5323 5325 ) 5324 5326 ) … … 5347 5349 fg "0,65535,0" 5348 5350 ) 5349 xt " 63000,71625,63750,72375"5351 xt "59000,71625,59750,72375" 5350 5352 ) 5351 5353 tg (CPTG … … 5358 5360 font "arial,8,0" 5359 5361 ) 5360 xt "5 6900,71500,62000,72500"5362 xt "52900,71500,58000,72500" 5361 5363 st "wiz_write_ea" 5362 5364 ju 2 5363 blo " 62000,72300"5365 blo "58000,72300" 5364 5366 ) 5365 5367 ) … … 5386 5388 fg "0,65535,0" 5387 5389 ) 5388 xt " 63000,75625,63750,76375"5390 xt "59000,75625,59750,76375" 5389 5391 ) 5390 5392 tg (CPTG … … 5397 5399 font "arial,8,0" 5398 5400 ) 5399 xt "5 6500,75500,62000,76500"5401 xt "52500,75500,58000,76500" 5400 5402 st "wiz_write_end" 5401 5403 ju 2 5402 blo " 62000,76300"5404 blo "58000,76300" 5403 5405 ) 5404 5406 ) … … 5425 5427 fg "0,65535,0" 5426 5428 ) 5427 xt " 63000,76625,63750,77375"5429 xt "59000,76625,59750,77375" 5428 5430 ) 5429 5431 tg (CPTG … … 5436 5438 font "arial,8,0" 5437 5439 ) 5438 xt "5 5400,76500,62000,77500"5440 xt "51400,76500,58000,77500" 5439 5441 st "wiz_write_header" 5440 5442 ju 2 5441 blo " 62000,77300"5443 blo "58000,77300" 5442 5444 ) 5443 5445 ) … … 5464 5466 fg "0,65535,0" 5465 5467 ) 5466 xt " 63000,72625,63750,73375"5468 xt "59000,72625,59750,73375" 5467 5469 ) 5468 5470 tg (CPTG … … 5475 5477 font "arial,8,0" 5476 5478 ) 5477 xt " 52600,72500,62000,73500"5479 xt "48600,72500,58000,73500" 5478 5480 st "wiz_write_length : (16:0)" 5479 5481 ju 2 5480 blo " 62000,73300"5482 blo "58000,73300" 5481 5483 ) 5482 5484 ) … … 5504 5506 fg "0,65535,0" 5505 5507 ) 5506 xt " 31250,87625,32000,88375"5508 xt "27250,85625,28000,86375" 5507 5509 ) 5508 5510 tg (CPTG … … 5515 5517 font "arial,8,0" 5516 5518 ) 5517 xt " 33000,87500,36400,88500"5519 xt "29000,85500,32400,86500" 5518 5520 st "roi_array" 5519 blo " 33000,88300"5521 blo "29000,86300" 5520 5522 ) 5521 5523 ) … … 5542 5544 fg "0,65535,0" 5543 5545 ) 5544 xt " 31250,81625,32000,82375"5546 xt "27250,79625,28000,80375" 5545 5547 ) 5546 5548 tg (CPTG … … 5553 5555 font "arial,8,0" 5554 5556 ) 5555 xt " 33000,81500,42100,82500"5557 xt "29000,79500,38100,80500" 5556 5558 st "package_length : (15:0)" 5557 blo " 33000,82300"5559 blo "29000,80300" 5558 5560 ) 5559 5561 ) … … 5581 5583 fg "0,65535,0" 5582 5584 ) 5583 xt " 31250,78625,32000,79375"5585 xt "27250,76625,28000,77375" 5584 5586 ) 5585 5587 tg (CPTG … … 5592 5594 font "arial,8,0" 5593 5595 ) 5594 xt " 33000,78500,38600,79500"5596 xt "29000,76500,34600,77500" 5595 5597 st "config_started" 5596 blo " 33000,79300"5598 blo "29000,77300" 5597 5599 ) 5598 5600 ) … … 5619 5621 fg "0,65535,0" 5620 5622 ) 5621 xt " 63000,77625,63750,78375"5623 xt "59000,77625,59750,78375" 5622 5624 ) 5623 5625 tg (CPTG … … 5630 5632 font "arial,8,0" 5631 5633 ) 5632 xt "5 9000,77500,62000,78500"5634 xt "55000,77500,58000,78500" 5633 5635 st "wiz_ack" 5634 5636 ju 2 5635 blo " 62000,78300"5637 blo "58000,78300" 5636 5638 ) 5637 5639 ) … … 5656 5658 fg "0,65535,0" 5657 5659 ) 5658 xt " 31250,75625,32000,76375"5660 xt "27250,73625,28000,74375" 5659 5661 ) 5660 5662 tg (CPTG … … 5667 5669 font "arial,8,0" 5668 5670 ) 5669 xt " 33000,75500,40800,76500"5671 xt "29000,73500,36800,74500" 5670 5672 st "ram_write_ready_ack" 5671 blo " 33000,76300"5673 blo "29000,74300" 5672 5674 ) 5673 5675 ) … … 5696 5698 lineWidth 2 5697 5699 ) 5698 xt " 32000,70000,63000,90000"5700 xt "28000,68000,59000,88000" 5699 5701 ) 5700 5702 oxt "15000,6000,23000,16000" … … 5709 5711 font "arial,8,1" 5710 5712 ) 5711 xt " 32350,90000,38550,91000"5713 xt "28350,88000,34550,89000" 5712 5714 st "FACT_FAD_lib" 5713 blo " 32350,90800"5715 blo "28350,88800" 5714 5716 tm "BdLibraryNameMgr" 5715 5717 ) … … 5719 5721 font "arial,8,1" 5720 5722 ) 5721 xt " 32350,91000,39650,92000"5723 xt "28350,89000,35650,90000" 5722 5724 st "memory_manager" 5723 blo " 32350,91800"5725 blo "28350,89800" 5724 5726 tm "CptNameMgr" 5725 5727 ) … … 5729 5731 font "arial,8,1" 5730 5732 ) 5731 xt " 32350,92000,42850,93000"5733 xt "28350,90000,38850,91000" 5732 5734 st "I_main_memory_manager" 5733 blo " 32350,92800"5735 blo "28350,90800" 5734 5736 tm "InstanceNameMgr" 5735 5737 ) … … 5746 5748 font "Courier New,8,0" 5747 5749 ) 5748 xt "3 2000,68400,61500,70000"5750 xt "31000,66400,60500,68000" 5749 5751 st "RAM_ADDR_WIDTH_64B = RAMADDRWIDTH64b ( integer ) 5750 5752 RAM_ADDR_WIDTH_16B = RAMADDRWIDTH64b+2 ( integer ) " … … 5772 5774 fg "49152,49152,49152" 5773 5775 ) 5774 xt " 32250,88250,33750,89750"5776 xt "28250,86250,29750,87750" 5775 5777 iconName "VhdlFileViewIcon.png" 5776 5778 iconMaskName "VhdlFileViewIcon.msk" … … 5797 5799 font "Courier New,8,0" 5798 5800 ) 5799 xt "-172000,10 1200,-149500,102000"5801 xt "-172000,100400,-149500,101200" 5800 5802 st "SIGNAL wiz_busy : std_logic 5801 5803 " … … 5817 5819 font "Courier New,8,0" 5818 5820 ) 5819 xt "-172000,10 3600,-128500,104400"5821 xt "-172000,102800,-128500,103600" 5820 5822 st "SIGNAL wiz_write_ea : std_logic := '0' 5821 5823 " … … 5838 5840 font "Courier New,8,0" 5839 5841 ) 5840 xt "-172000,10 6000,-122500,106800"5842 xt "-172000,105200,-122500,106000" 5841 5843 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0') 5842 5844 " … … 5860 5862 font "Courier New,8,0" 5861 5863 ) 5862 xt "-172000,102 800,-122500,103600"5864 xt "-172000,102000,-122500,102800" 5863 5865 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0') 5864 5866 " … … 5881 5883 font "Courier New,8,0" 5882 5884 ) 5883 xt "-172000,10 2000,-122500,102800"5885 xt "-172000,101200,-122500,102000" 5884 5886 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0') 5885 5887 " … … 5901 5903 font "Courier New,8,0" 5902 5904 ) 5903 xt "-172000,10 4400,-128500,105200"5905 xt "-172000,103600,-128500,104400" 5904 5906 st "SIGNAL wiz_write_end : std_logic := '0' 5905 5907 " … … 5921 5923 font "Courier New,8,0" 5922 5924 ) 5923 xt "-172000,10 5200,-128500,106000"5925 xt "-172000,104400,-128500,105200" 5924 5926 st "SIGNAL wiz_write_header : std_logic := '0' 5925 5927 " … … 6932 6934 sl 0 6933 6935 ro 90 6934 xt "-2 9000,65625,-27500,66375"6936 xt "-28000,66625,-26500,67375" 6935 6937 ) 6936 6938 (Line … … 6938 6940 sl 0 6939 6941 ro 90 6940 xt "-2 7500,66000,-27000,66000"6941 pts [ 6942 "-2 7000,66000"6943 "-2 7500,66000"6942 xt "-26500,67000,-26000,67000" 6943 pts [ 6944 "-26000,67000" 6945 "-26500,67000" 6944 6946 ] 6945 6947 ) … … 6956 6958 va (VaSet 6957 6959 ) 6958 xt "-3 5900,65500,-30000,66500"6960 xt "-34900,66500,-29000,67500" 6959 6961 st "drs_channel_id" 6960 6962 ju 2 6961 blo "- 30000,66300"6963 blo "-29000,67300" 6962 6964 tm "WireNameMgr" 6963 6965 ) … … 10972 10974 font "Courier New,8,0" 10973 10975 ) 10974 xt "-172000, 100400,-149500,101200"10976 xt "-172000,99600,-149500,100400" 10975 10977 st "SIGNAL wiz_ack : std_logic 10976 10978 " … … 12959 12961 ) 12960 12962 *431 (Net 12961 uid 10449,012962 decl (Decl12963 n "trigger_out"12964 t "std_logic"12965 preAdd 012966 posAdd 012967 o 12012968 suid 240,012969 )12970 declText (MLText12971 uid 10450,012972 va (VaSet12973 font "Courier New,8,0"12974 )12975 xt "-172000,99600,-149500,100400"12976 st "SIGNAL trigger_out : std_logic12977 "12978 )12979 )12980 *432 (Net12981 12963 uid 10465,0 12982 12964 lang 2 … … 13002 12984 ) 13003 12985 ) 13004 *43 3(Net12986 *432 (Net 13005 12987 uid 10627,0 13006 12988 decl (Decl … … 13020 13002 ) 13021 13003 ) 13022 *43 4(Net13004 *433 (Net 13023 13005 uid 10635,0 13024 13006 decl (Decl … … 13038 13020 ) 13039 13021 ) 13040 *43 5(Net13022 *434 (Net 13041 13023 uid 10721,0 13042 13024 decl (Decl … … 13056 13038 ) 13057 13039 ) 13058 *43 6(PortIoOut13040 *435 (PortIoOut 13059 13041 uid 10729,0 13060 13042 shape (CompositeShape … … 13100 13082 ) 13101 13083 ) 13102 *43 7(Net13084 *436 (Net 13103 13085 uid 10735,0 13104 13086 decl (Decl … … 13118 13100 ) 13119 13101 ) 13120 *43 8(PortIoOut13102 *437 (PortIoOut 13121 13103 uid 10743,0 13122 13104 shape (CompositeShape … … 13162 13144 ) 13163 13145 ) 13164 *43 9(Net13146 *438 (Net 13165 13147 uid 10749,0 13166 13148 decl (Decl … … 13180 13162 ) 13181 13163 ) 13182 *4 40(PortIoOut13164 *439 (PortIoOut 13183 13165 uid 10757,0 13184 13166 shape (CompositeShape … … 13224 13206 ) 13225 13207 ) 13226 *44 1(SaComponent13208 *440 (SaComponent 13227 13209 uid 11209,0 13228 13210 optionalChildren [ 13229 *44 2(CptPort13211 *441 (CptPort 13230 13212 uid 11181,0 13231 13213 ps "OnEdgeStrategy" … … 13260 13242 ) 13261 13243 ) 13262 *44 3(CptPort13244 *442 (CptPort 13263 13245 uid 11185,0 13264 13246 ps "OnEdgeStrategy" … … 13295 13277 ) 13296 13278 ) 13297 *44 4(CptPort13279 *443 (CptPort 13298 13280 uid 11189,0 13299 13281 ps "OnEdgeStrategy" … … 13330 13312 ) 13331 13313 ) 13332 *44 5(CptPort13314 *444 (CptPort 13333 13315 uid 11193,0 13334 13316 ps "OnEdgeStrategy" … … 13365 13347 ) 13366 13348 ) 13367 *44 6(CptPort13349 *445 (CptPort 13368 13350 uid 11197,0 13369 13351 ps "OnEdgeStrategy" … … 13398 13380 ) 13399 13381 ) 13400 *44 7(CptPort13382 *446 (CptPort 13401 13383 uid 11201,0 13402 13384 ps "OnEdgeStrategy" … … 13431 13413 ) 13432 13414 ) 13433 *44 8(CptPort13415 *447 (CptPort 13434 13416 uid 11205,0 13435 13417 ps "OnEdgeStrategy" … … 13464 13446 ) 13465 13447 ) 13466 *44 9(CptPort13448 *448 (CptPort 13467 13449 uid 12693,0 13468 13450 ps "OnEdgeStrategy" … … 13516 13498 stg "VerticalLayoutStrategy" 13517 13499 textVec [ 13518 *4 50(Text13500 *449 (Text 13519 13501 uid 11212,0 13520 13502 va (VaSet … … 13526 13508 tm "BdLibraryNameMgr" 13527 13509 ) 13528 *45 1(Text13510 *450 (Text 13529 13511 uid 11213,0 13530 13512 va (VaSet … … 13536 13518 tm "CptNameMgr" 13537 13519 ) 13538 *45 2(Text13520 *451 (Text 13539 13521 uid 11214,0 13540 13522 va (VaSet … … 13603 13585 archFileType "UNKNOWN" 13604 13586 ) 13605 *45 3(Net13587 *452 (Net 13606 13588 uid 11403,0 13607 13589 decl (Decl … … 13621 13603 ) 13622 13604 ) 13623 *45 4(Net13605 *453 (Net 13624 13606 uid 11856,0 13625 13607 decl (Decl … … 13639 13621 ) 13640 13622 ) 13641 *45 5(MWC13623 *454 (MWC 13642 13624 uid 12295,0 13643 13625 optionalChildren [ 13644 *45 6(CptPort13626 *455 (CptPort 13645 13627 uid 12267,0 13646 13628 optionalChildren [ 13647 *45 7(Line13629 *456 (Line 13648 13630 uid 12271,0 13649 13631 layer 5 … … 13658 13640 ] 13659 13641 ) 13660 *45 8(Property13642 *457 (Property 13661 13643 uid 12272,0 13662 13644 pclass "_MW_GEOM_" … … 13705 13687 ) 13706 13688 ) 13707 *45 9(CptPort13689 *458 (CptPort 13708 13690 uid 12273,0 13709 13691 optionalChildren [ 13710 *4 60(Line13692 *459 (Line 13711 13693 uid 12277,0 13712 13694 layer 5 … … 13760 13742 ) 13761 13743 ) 13762 *46 1(CptPort13744 *460 (CptPort 13763 13745 uid 12278,0 13764 13746 optionalChildren [ 13765 *46 2(Line13747 *461 (Line 13766 13748 uid 12282,0 13767 13749 layer 5 … … 13813 13795 ) 13814 13796 ) 13815 *46 3(CommentGraphic13797 *462 (CommentGraphic 13816 13798 uid 12283,0 13817 13799 optionalChildren [ 13818 *46 4(Property13800 *463 (Property 13819 13801 uid 12285,0 13820 13802 pclass "_MW_GEOM_" … … 13840 13822 oxt "7000,10000,7000,10000" 13841 13823 ) 13842 *46 5(CommentGraphic13824 *464 (CommentGraphic 13843 13825 uid 12286,0 13844 13826 optionalChildren [ 13845 *46 6(Property13827 *465 (Property 13846 13828 uid 12288,0 13847 13829 pclass "_MW_GEOM_" … … 13867 13849 oxt "7000,6000,7000,6000" 13868 13850 ) 13869 *46 7(Grouping13851 *466 (Grouping 13870 13852 uid 12289,0 13871 13853 optionalChildren [ 13872 *46 8(CommentGraphic13854 *467 (CommentGraphic 13873 13855 uid 12291,0 13874 13856 shape (PolyLine2D … … 13891 13873 oxt "7000,6000,9000,10000" 13892 13874 ) 13893 *46 9(CommentGraphic13875 *468 (CommentGraphic 13894 13876 uid 12293,0 13895 13877 shape (Arc2D … … 13944 13926 stg "VerticalLayoutStrategy" 13945 13927 textVec [ 13946 *4 70(Text13928 *469 (Text 13947 13929 uid 12298,0 13948 13930 va (VaSet … … 13954 13936 blo "-80500,73300" 13955 13937 ) 13956 *47 1(Text13938 *470 (Text 13957 13939 uid 12299,0 13958 13940 va (VaSet … … 13963 13945 blo "-80500,74300" 13964 13946 ) 13965 *47 2(Text13947 *471 (Text 13966 13948 uid 12300,0 13967 13949 va (VaSet … … 14008 13990 ) 14009 13991 ) 14010 *47 3(Net13992 *472 (Net 14011 13993 uid 12304,0 14012 13994 decl (Decl … … 14028 14010 ) 14029 14011 ) 14030 *47 4(SaComponent14012 *473 (SaComponent 14031 14013 uid 12625,0 14032 14014 optionalChildren [ 14033 *47 5(CptPort14015 *474 (CptPort 14034 14016 uid 12605,0 14035 14017 ps "OnEdgeStrategy" … … 14064 14046 ) 14065 14047 ) 14066 *47 6(CptPort14048 *475 (CptPort 14067 14049 uid 12609,0 14068 14050 ps "OnEdgeStrategy" … … 14100 14082 ) 14101 14083 ) 14102 *47 7(CptPort14084 *476 (CptPort 14103 14085 uid 12613,0 14104 14086 ps "OnEdgeStrategy" … … 14135 14117 ) 14136 14118 ) 14137 *47 8(CptPort14119 *477 (CptPort 14138 14120 uid 12617,0 14139 14121 ps "OnEdgeStrategy" … … 14169 14151 ) 14170 14152 ) 14171 *47 9(CptPort14153 *478 (CptPort 14172 14154 uid 12621,0 14173 14155 ps "OnEdgeStrategy" … … 14205 14187 ) 14206 14188 ) 14207 *4 80(CptPort14189 *479 (CptPort 14208 14190 uid 12673,0 14209 14191 ps "OnEdgeStrategy" … … 14255 14237 stg "VerticalLayoutStrategy" 14256 14238 textVec [ 14257 *48 1(Text14239 *480 (Text 14258 14240 uid 12628,0 14259 14241 va (VaSet … … 14265 14247 tm "BdLibraryNameMgr" 14266 14248 ) 14267 *48 2(Text14249 *481 (Text 14268 14250 uid 12629,0 14269 14251 va (VaSet … … 14275 14257 tm "CptNameMgr" 14276 14258 ) 14277 *48 3(Text14259 *482 (Text 14278 14260 uid 12630,0 14279 14261 va (VaSet … … 14322 14304 archFileType "UNKNOWN" 14323 14305 ) 14324 *48 4(Net14306 *483 (Net 14325 14307 uid 12641,0 14326 14308 decl (Decl … … 14342 14324 ) 14343 14325 ) 14344 *48 5(Net14326 *484 (Net 14345 14327 uid 12647,0 14346 14328 decl (Decl … … 14367 14349 ) 14368 14350 ) 14369 *48 6(Net14351 *485 (Net 14370 14352 uid 12653,0 14371 14353 decl (Decl … … 14385 14367 ) 14386 14368 ) 14387 *48 7(Net14369 *486 (Net 14388 14370 uid 12705,0 14389 14371 decl (Decl … … 14403 14385 ) 14404 14386 ) 14405 *48 8(PortIoOut14387 *487 (PortIoOut 14406 14388 uid 12713,0 14407 14389 shape (CompositeShape … … 14447 14429 ) 14448 14430 ) 14449 *48 9(SaComponent14431 *488 (SaComponent 14450 14432 uid 13117,0 14451 14433 optionalChildren [ 14452 *4 90(CptPort14434 *489 (CptPort 14453 14435 uid 13101,0 14454 14436 ps "OnEdgeStrategy" … … 14460 14442 fg "0,65535,0" 14461 14443 ) 14462 xt " 63000,61625,63750,62375"14444 xt "72000,61625,72750,62375" 14463 14445 ) 14464 14446 tg (CPTG … … 14470 14452 va (VaSet 14471 14453 ) 14472 xt "6 0100,61500,62000,62500"14454 xt "69100,61500,71000,62500" 14473 14455 st "CLK" 14474 14456 ju 2 14475 blo " 62000,62300"14457 blo "71000,62300" 14476 14458 ) 14477 14459 ) … … 14484 14466 ) 14485 14467 ) 14486 *49 1(CptPort14468 *490 (CptPort 14487 14469 uid 13105,0 14488 14470 ps "OnEdgeStrategy" … … 14494 14476 fg "0,65535,0" 14495 14477 ) 14496 xt " 63000,62625,63750,63375"14478 xt "72000,62625,72750,63375" 14497 14479 ) 14498 14480 tg (CPTG … … 14504 14486 va (VaSet 14505 14487 ) 14506 xt " 59400,62500,62000,63500"14488 xt "68400,62500,71000,63500" 14507 14489 st "enable" 14508 14490 ju 2 14509 blo " 62000,63300"14491 blo "71000,63300" 14510 14492 ) 14511 14493 ) … … 14518 14500 ) 14519 14501 ) 14520 *49 2(CptPort14502 *491 (CptPort 14521 14503 uid 13109,0 14522 14504 ps "OnEdgeStrategy" … … 14528 14510 fg "0,65535,0" 14529 14511 ) 14530 xt " 63000,63625,63750,64375"14512 xt "72000,63625,72750,64375" 14531 14513 ) 14532 14514 tg (CPTG … … 14538 14520 va (VaSet 14539 14521 ) 14540 xt " 55900,63500,62000,64500"14522 xt "64900,63500,71000,64500" 14541 14523 st "multiplier : (7:0)" 14542 14524 ju 2 14543 blo " 62000,64300"14525 blo "71000,64300" 14544 14526 ) 14545 14527 ) … … 14553 14535 ) 14554 14536 ) 14555 *49 3(CptPort14537 *492 (CptPort 14556 14538 uid 13113,0 14557 14539 ps "OnEdgeStrategy" … … 14563 14545 fg "0,65535,0" 14564 14546 ) 14565 xt "5 0250,61625,51000,62375"14547 xt "59250,61625,60000,62375" 14566 14548 ) 14567 14549 tg (CPTG … … 14573 14555 va (VaSet 14574 14556 ) 14575 xt " 52000,61500,54800,62500"14557 xt "61000,61500,63800,62500" 14576 14558 st "trigger" 14577 blo " 52000,62300"14559 blo "61000,62300" 14578 14560 ) 14579 14561 ) … … 14596 14578 lineWidth 2 14597 14579 ) 14598 xt " 51000,61000,63000,65000"14580 xt "60000,61000,72000,65000" 14599 14581 ) 14600 14582 oxt "0,0,8000,10000" … … 14604 14586 stg "VerticalLayoutStrategy" 14605 14587 textVec [ 14588 *493 (Text 14589 uid 13120,0 14590 va (VaSet 14591 font "Arial,8,1" 14592 ) 14593 xt "62350,65000,68550,66000" 14594 st "FACT_FAD_lib" 14595 blo "62350,65800" 14596 tm "BdLibraryNameMgr" 14597 ) 14606 14598 *494 (Text 14607 uid 1312 0,014599 uid 13121,0 14608 14600 va (VaSet 14609 14601 font "Arial,8,1" 14610 14602 ) 14611 xt " 53350,65000,59550,66000"14612 st " FACT_FAD_lib"14613 blo " 53350,65800"14614 tm " BdLibraryNameMgr"14603 xt "62350,66000,69650,67000" 14604 st "continous_pulser" 14605 blo "62350,66800" 14606 tm "CptNameMgr" 14615 14607 ) 14616 14608 *495 (Text 14617 uid 1312 1,014609 uid 13122,0 14618 14610 va (VaSet 14619 14611 font "Arial,8,1" 14620 14612 ) 14621 xt "53350,66000,60650,67000" 14622 st "continous_pulser" 14623 blo "53350,66800" 14624 tm "CptNameMgr" 14625 ) 14626 *496 (Text 14627 uid 13122,0 14628 va (VaSet 14629 font "Arial,8,1" 14630 ) 14631 xt "53350,67000,55150,68000" 14613 xt "62350,67000,64150,68000" 14632 14614 st "U_3" 14633 blo " 53350,67800"14615 blo "62350,67800" 14634 14616 tm "InstanceNameMgr" 14635 14617 ) … … 14646 14628 font "Courier New,8,0" 14647 14629 ) 14648 xt " 44000,60200,71500,61000"14630 xt "53000,60200,80500,61000" 14649 14631 st "MINIMAL_TRIGGER_WAIT_TIME = 250000 ( integer ) " 14650 14632 ) … … 14666 14648 fg "49152,49152,49152" 14667 14649 ) 14668 xt " 51250,63250,52750,64750"14650 xt "60250,63250,61750,64750" 14669 14651 iconName "VhdlFileViewIcon.png" 14670 14652 iconMaskName "VhdlFileViewIcon.msk" … … 14677 14659 archFileType "UNKNOWN" 14678 14660 ) 14679 *49 7(Net14661 *496 (Net 14680 14662 uid 13157,0 14681 14663 decl (Decl … … 14696 14678 ) 14697 14679 ) 14698 *49 8(Net14680 *497 (Net 14699 14681 uid 13163,0 14700 14682 decl (Decl … … 14718 14700 ) 14719 14701 ) 14720 *49 9(Net14702 *498 (Net 14721 14703 uid 13206,0 14722 14704 decl (Decl … … 14736 14718 ) 14737 14719 ) 14738 * 500(Net14720 *499 (Net 14739 14721 uid 13208,0 14740 14722 decl (Decl … … 14754 14736 ) 14755 14737 ) 14756 *50 1(MWC14738 *500 (MWC 14757 14739 uid 13266,0 14758 14740 optionalChildren [ 14759 *50 2(CptPort14741 *501 (CptPort 14760 14742 uid 13230,0 14761 14743 optionalChildren [ 14762 *50 3(Line14744 *502 (Line 14763 14745 uid 13234,0 14764 14746 layer 5 … … 14767 14749 vasetType 3 14768 14750 ) 14769 xt " 40408,62000,42000,62000"14770 pts [ 14771 " 42000,62000"14772 " 40408,62000"14751 xt "52408,62000,54000,62000" 14752 pts [ 14753 "54000,62000" 14754 "52408,62000" 14773 14755 ] 14774 14756 ) … … 14783 14765 fg "0,65535,65535" 14784 14766 ) 14785 xt " 42000,61625,42750,62375"14767 xt "54000,61625,54750,62375" 14786 14768 ) 14787 14769 tg (CPTG … … 14796 14778 font "arial,8,0" 14797 14779 ) 14798 xt "2 05750,61700,207550,62700"14780 xt "217750,61700,219550,62700" 14799 14781 st "din1" 14800 14782 ju 2 14801 blo "2 07550,62500"14783 blo "219550,62500" 14802 14784 ) 14803 14785 ) … … 14811 14793 ) 14812 14794 ) 14813 *50 4(CptPort14795 *503 (CptPort 14814 14796 uid 13235,0 14815 14797 optionalChildren [ 14816 *50 5(Property14798 *504 (Property 14817 14799 uid 13239,0 14818 14800 pclass "_MW_GEOM_" … … 14820 14802 ptn "String" 14821 14803 ) 14822 *50 6(Line14804 *505 (Line 14823 14805 uid 13240,0 14824 14806 layer 5 … … 14827 14809 vasetType 3 14828 14810 ) 14829 xt " 36000,61000,37000,61000"14830 pts [ 14831 " 36000,61000"14832 " 37000,61000"14811 xt "48000,61000,49000,61000" 14812 pts [ 14813 "48000,61000" 14814 "49000,61000" 14833 14815 ] 14834 14816 ) … … 14843 14825 fg "0,65535,65535" 14844 14826 ) 14845 xt " 35250,60625,36000,61375"14827 xt "47250,60625,48000,61375" 14846 14828 ) 14847 14829 tg (CPTG … … 14856 14838 font "arial,8,0" 14857 14839 ) 14858 xt "2 02500,60532,204300,61532"14840 xt "214500,60532,216300,61532" 14859 14841 st "dout" 14860 blo "2 02500,61332"14842 blo "214500,61332" 14861 14843 ) 14862 14844 ) … … 14871 14853 ) 14872 14854 ) 14873 *50 7(CptPort14855 *506 (CptPort 14874 14856 uid 13241,0 14875 14857 optionalChildren [ 14876 *50 8(Line14858 *507 (Line 14877 14859 uid 13245,0 14878 14860 layer 5 … … 14881 14863 vasetType 3 14882 14864 ) 14883 xt " 40408,60000,42000,60000"14884 pts [ 14885 " 42000,60000"14886 " 40408,60000"14865 xt "52408,60000,54000,60000" 14866 pts [ 14867 "54000,60000" 14868 "52408,60000" 14887 14869 ] 14888 14870 ) … … 14897 14879 fg "0,65535,65535" 14898 14880 ) 14899 xt " 42000,59625,42750,60375"14881 xt "54000,59625,54750,60375" 14900 14882 ) 14901 14883 tg (CPTG … … 14910 14892 font "arial,8,0" 14911 14893 ) 14912 xt "2 05635,59294,207435,60294"14894 xt "217635,59294,219435,60294" 14913 14895 st "din0" 14914 14896 ju 2 14915 blo "2 07435,60094"14897 blo "219435,60094" 14916 14898 ) 14917 14899 ) … … 14925 14907 ) 14926 14908 ) 14927 *50 9(CommentGraphic14909 *508 (CommentGraphic 14928 14910 uid 13246,0 14929 14911 shape (Arc2D 14930 14912 pts [ 14931 " 37000,61000"14932 " 38737,59521"14933 " 41000,59004"14913 "49000,61000" 14914 "50737,59521" 14915 "53000,59004" 14934 14916 ] 14935 14917 uid 13247,0 … … 14942 14924 lineColor "26368,26368,26368" 14943 14925 ) 14944 xt " 37000,59003,41000,61000"14926 xt "49000,59003,53000,61000" 14945 14927 ) 14946 14928 oxt "7000,6003,11000,8000" 14947 14929 ) 14948 *5 10(CommentGraphic14930 *509 (CommentGraphic 14949 14931 uid 13248,0 14950 14932 shape (Arc2D 14951 14933 pts [ 14952 " 41004,62998"14953 " 38551,62394"14954 " 37000,61005"14934 "53004,62998" 14935 "50551,62394" 14936 "49000,61005" 14955 14937 ] 14956 14938 uid 13249,0 … … 14963 14945 lineColor "26368,26368,26368" 14964 14946 ) 14965 xt " 37000,61005,41004,62999"14947 xt "49000,61005,53004,62999" 14966 14948 ) 14967 14949 oxt "7000,8005,11004,10000" 14968 14950 ) 14969 *51 1(Grouping14951 *510 (Grouping 14970 14952 uid 13250,0 14971 14953 optionalChildren [ 14972 *51 2(CommentGraphic14954 *511 (CommentGraphic 14973 14955 uid 13252,0 14974 14956 optionalChildren [ 14975 *51 3(Property14957 *512 (Property 14976 14958 uid 13254,0 14977 14959 pclass "_MW_GEOM_" … … 14982 14964 shape (CustomPolygon 14983 14965 pts [ 14984 " 41000,62998"14985 " 38952,62132"14986 " 37000,61000"14987 " 38048,60156"14988 " 39817,59211"14989 " 41000,59000"14990 " 41000,62998"14966 "53000,62998" 14967 "50952,62132" 14968 "49000,61000" 14969 "50048,60156" 14970 "51817,59211" 14971 "53000,59000" 14972 "53000,62998" 14991 14973 ] 14992 14974 uid 13253,0 … … 15000 14982 fillStyle 1 15001 14983 ) 15002 xt " 37000,59000,41000,62998"14984 xt "49000,59000,53000,62998" 15003 14985 ) 15004 14986 oxt "7000,6000,11000,9998" 15005 14987 ) 15006 *51 4(CommentGraphic14988 *513 (CommentGraphic 15007 14989 uid 13255,0 15008 14990 optionalChildren [ 15009 *51 5(Property14991 *514 (Property 15010 14992 uid 13257,0 15011 14993 pclass "_MW_GEOM_" … … 15016 14998 shape (Arc2D 15017 14999 pts [ 15018 " 41000,63000"15019 " 40237,61001"15020 " 41000,59000"15000 "53000,63000" 15001 "52237,61001" 15002 "53000,59000" 15021 15003 ] 15022 15004 uid 13256,0 … … 15031 15013 fillStyle 1 15032 15014 ) 15033 xt " 40236,59000,41000,63000"15015 xt "52236,59000,53000,63000" 15034 15016 ) 15035 15017 oxt "10238,6000,11000,10000" … … 15045 15027 lineWidth 2 15046 15028 ) 15047 xt " 37000,59000,41000,63000"15029 xt "49000,59000,53000,63000" 15048 15030 ) 15049 15031 oxt "7000,6000,11000,10000" 15050 15032 ) 15051 *51 6(CommentGraphic15033 *515 (CommentGraphic 15052 15034 uid 13258,0 15053 15035 shape (PolyLine2D 15054 15036 pts [ 15055 " 37000,61000"15056 " 37000,61000"15037 "49000,61000" 15038 "49000,61000" 15057 15039 ] 15058 15040 uid 13259,0 … … 15064 15046 fg "49152,49152,49152" 15065 15047 ) 15066 xt " 37000,61000,37000,61000"15048 xt "49000,61000,49000,61000" 15067 15049 ) 15068 15050 oxt "7000,8000,7000,8000" 15069 15051 ) 15070 *51 7(CommentGraphic15052 *516 (CommentGraphic 15071 15053 uid 13260,0 15072 15054 optionalChildren [ 15073 *51 8(Property15055 *517 (Property 15074 15056 uid 13262,0 15075 15057 pclass "_MW_GEOM_" … … 15080 15062 shape (PolyLine2D 15081 15063 pts [ 15082 " 41000,59000"15083 " 41000,59000"15064 "53000,59000" 15065 "53000,59000" 15084 15066 ] 15085 15067 uid 13261,0 … … 15091 15073 fg "49152,49152,49152" 15092 15074 ) 15093 xt " 41000,59000,41000,59000"15075 xt "53000,59000,53000,59000" 15094 15076 ) 15095 15077 oxt "11000,6000,11000,6000" 15096 15078 ) 15097 *51 9(CommentGraphic15079 *518 (CommentGraphic 15098 15080 uid 13263,0 15099 15081 optionalChildren [ 15100 *5 20(Property15082 *519 (Property 15101 15083 uid 13265,0 15102 15084 pclass "_MW_GEOM_" … … 15107 15089 shape (PolyLine2D 15108 15090 pts [ 15109 " 41000,63000"15110 " 41000,63000"15091 "53000,63000" 15092 "53000,63000" 15111 15093 ] 15112 15094 uid 13264,0 … … 15118 15100 fg "49152,49152,49152" 15119 15101 ) 15120 xt " 41000,63000,41000,63000"15102 xt "53000,63000,53000,63000" 15121 15103 ) 15122 15104 oxt "11000,10000,11000,10000" … … 15131 15113 lineWidth -1 15132 15114 ) 15133 xt " 36000,59000,42000,63000"15115 xt "48000,59000,54000,63000" 15134 15116 fos 1 15135 15117 ) … … 15141 15123 stg "VerticalLayoutStrategy" 15142 15124 textVec [ 15143 *52 1(Text15125 *520 (Text 15144 15126 uid 13269,0 15145 15127 va (VaSet … … 15147 15129 font "arial,8,0" 15148 15130 ) 15149 xt " 37500,61500,42300,62500"15131 xt "49500,61500,54300,62500" 15150 15132 st "moduleware" 15151 blo "37500,62300" 15133 blo "49500,62300" 15134 ) 15135 *521 (Text 15136 uid 13270,0 15137 va (VaSet 15138 font "arial,8,0" 15139 ) 15140 xt "49500,62500,50600,63500" 15141 st "or" 15142 blo "49500,63300" 15152 15143 ) 15153 15144 *522 (Text 15154 uid 1327 0,015145 uid 13271,0 15155 15146 va (VaSet 15156 15147 font "arial,8,0" 15157 15148 ) 15158 xt "37500,62500,38600,63500" 15159 st "or" 15160 blo "37500,63300" 15161 ) 15162 *523 (Text 15163 uid 13271,0 15164 va (VaSet 15165 font "arial,8,0" 15166 ) 15167 xt "37500,63500,39700,64500" 15149 xt "49500,63500,51700,64500" 15168 15150 st "U_13" 15169 blo " 37500,64300"15151 blo "49500,64300" 15170 15152 tm "InstanceNameMgr" 15171 15153 ) … … 15182 15164 font "arial,8,0" 15183 15165 ) 15184 xt " 21000,50000,21000,50000"15166 xt "33000,50000,33000,50000" 15185 15167 ) 15186 15168 header "" … … 15205 15187 ) 15206 15188 ) 15207 *52 4(PortIoIn15189 *523 (PortIoIn 15208 15190 uid 13689,0 15209 15191 shape (CompositeShape … … 15250 15232 ) 15251 15233 ) 15252 *52 5(Net15234 *524 (Net 15253 15235 uid 13701,0 15254 15236 decl (Decl … … 15269 15251 ) 15270 15252 ) 15271 *52 6(PortIoIn15253 *525 (PortIoIn 15272 15254 uid 14042,0 15273 15255 shape (CompositeShape … … 15314 15296 ) 15315 15297 ) 15316 *52 7(Net15298 *526 (Net 15317 15299 uid 14054,0 15318 15300 decl (Decl … … 15333 15315 ) 15334 15316 ) 15335 *52 8(PortIoIn15317 *527 (PortIoIn 15336 15318 uid 14165,0 15337 15319 shape (CompositeShape … … 15378 15360 ) 15379 15361 ) 15380 *52 9(Net15362 *528 (Net 15381 15363 uid 14177,0 15382 15364 decl (Decl … … 15398 15380 ) 15399 15381 ) 15400 *5 30(SaComponent15382 *529 (SaComponent 15401 15383 uid 14417,0 15402 15384 optionalChildren [ 15403 *53 1(CptPort15385 *530 (CptPort 15404 15386 uid 14397,0 15405 15387 ps "OnEdgeStrategy" … … 15434 15416 ) 15435 15417 ) 15436 *53 2(CptPort15418 *531 (CptPort 15437 15419 uid 14401,0 15438 15420 ps "OnEdgeStrategy" … … 15467 15449 ) 15468 15450 ) 15469 *53 3(CptPort15451 *532 (CptPort 15470 15452 uid 14405,0 15471 15453 ps "OnEdgeStrategy" … … 15504 15486 ) 15505 15487 ) 15506 *53 4(CptPort15488 *533 (CptPort 15507 15489 uid 14409,0 15508 15490 ps "OnEdgeStrategy" … … 15540 15522 ) 15541 15523 ) 15542 *53 5(CptPort15524 *534 (CptPort 15543 15525 uid 14413,0 15544 15526 ps "OnEdgeStrategy" … … 15593 15575 stg "VerticalLayoutStrategy" 15594 15576 textVec [ 15595 *53 6(Text15577 *535 (Text 15596 15578 uid 14420,0 15597 15579 va (VaSet … … 15603 15585 tm "BdLibraryNameMgr" 15604 15586 ) 15605 *53 7(Text15587 *536 (Text 15606 15588 uid 14421,0 15607 15589 va (VaSet … … 15613 15595 tm "CptNameMgr" 15614 15596 ) 15615 *53 8(Text15597 *537 (Text 15616 15598 uid 14422,0 15617 15599 va (VaSet … … 15661 15643 archFileType "UNKNOWN" 15662 15644 ) 15663 *53 9(Net15645 *538 (Net 15664 15646 uid 14477,0 15665 15647 decl (Decl … … 15682 15664 ) 15683 15665 ) 15684 *5 40(PortIoOut15666 *539 (PortIoOut 15685 15667 uid 14485,0 15686 15668 shape (CompositeShape … … 15726 15708 ) 15727 15709 ) 15728 *54 1(Net15710 *540 (Net 15729 15711 uid 14491,0 15730 15712 decl (Decl … … 15747 15729 ) 15748 15730 ) 15749 *54 2(PortIoOut15731 *541 (PortIoOut 15750 15732 uid 14499,0 15751 15733 shape (CompositeShape … … 15791 15773 ) 15792 15774 ) 15793 *54 3(Net15775 *542 (Net 15794 15776 uid 14620,0 15795 15777 decl (Decl … … 15811 15793 ) 15812 15794 ) 15813 *54 4(PortIoOut15795 *543 (PortIoOut 15814 15796 uid 14628,0 15815 15797 shape (CompositeShape … … 15855 15837 ) 15856 15838 ) 15857 *54 5(MWC15839 *544 (MWC 15858 15840 uid 14991,0 15859 15841 optionalChildren [ 15860 *54 6(CptPort15842 *545 (CptPort 15861 15843 uid 14963,0 15862 15844 optionalChildren [ 15863 *54 7(Line15845 *546 (Line 15864 15846 uid 14967,0 15865 15847 layer 5 … … 15874 15856 ] 15875 15857 ) 15876 *54 8(Property15858 *547 (Property 15877 15859 uid 14968,0 15878 15860 pclass "_MW_GEOM_" … … 15922 15904 ) 15923 15905 ) 15924 *54 9(CptPort15906 *548 (CptPort 15925 15907 uid 14969,0 15926 15908 optionalChildren [ 15927 *5 50(Line15909 *549 (Line 15928 15910 uid 14973,0 15929 15911 layer 5 … … 15978 15960 ) 15979 15961 ) 15980 *55 1(CptPort15962 *550 (CptPort 15981 15963 uid 14974,0 15982 15964 optionalChildren [ 15983 *55 2(Line15965 *551 (Line 15984 15966 uid 14978,0 15985 15967 layer 5 … … 16034 16016 ) 16035 16017 ) 16036 *55 3(CommentGraphic16018 *552 (CommentGraphic 16037 16019 uid 14979,0 16038 16020 optionalChildren [ 16039 *55 4(Property16021 *553 (Property 16040 16022 uid 14981,0 16041 16023 pclass "_MW_GEOM_" … … 16061 16043 oxt "7000,10000,7000,10000" 16062 16044 ) 16063 *55 5(CommentGraphic16045 *554 (CommentGraphic 16064 16046 uid 14982,0 16065 16047 optionalChildren [ 16066 *55 6(Property16048 *555 (Property 16067 16049 uid 14984,0 16068 16050 pclass "_MW_GEOM_" … … 16088 16070 oxt "7000,6000,7000,6000" 16089 16071 ) 16090 *55 7(Grouping16072 *556 (Grouping 16091 16073 uid 14985,0 16092 16074 optionalChildren [ 16093 *55 8(CommentGraphic16075 *557 (CommentGraphic 16094 16076 uid 14987,0 16095 16077 shape (PolyLine2D … … 16112 16094 oxt "7000,6000,9000,10000" 16113 16095 ) 16114 *55 9(CommentGraphic16096 *558 (CommentGraphic 16115 16097 uid 14989,0 16116 16098 shape (Arc2D … … 16165 16147 stg "VerticalLayoutStrategy" 16166 16148 textVec [ 16167 *5 60(Text16149 *559 (Text 16168 16150 uid 14994,0 16169 16151 va (VaSet … … 16175 16157 blo "162500,76300" 16176 16158 ) 16177 *56 1(Text16159 *560 (Text 16178 16160 uid 14995,0 16179 16161 va (VaSet … … 16184 16166 blo "162500,77300" 16185 16167 ) 16186 *56 2(Text16168 *561 (Text 16187 16169 uid 14996,0 16188 16170 va (VaSet … … 16229 16211 ) 16230 16212 ) 16231 *56 3(MWC16213 *562 (MWC 16232 16214 uid 15036,0 16233 16215 optionalChildren [ 16234 *56 4(CptPort16216 *563 (CptPort 16235 16217 uid 15005,0 16236 16218 optionalChildren [ 16237 *56 5(Property16219 *564 (Property 16238 16220 uid 15009,0 16239 16221 pclass "_MW_GEOM_" … … 16241 16223 ptn "String" 16242 16224 ) 16243 *56 6(Line16225 *565 (Line 16244 16226 uid 15010,0 16245 16227 layer 5 … … 16296 16278 ) 16297 16279 ) 16298 *56 7(CommentGraphic16280 *566 (CommentGraphic 16299 16281 uid 15016,0 16300 16282 shape (Arc2D … … 16318 16300 oxt "110003,265000,112000,269000" 16319 16301 ) 16320 *56 8(CommentGraphic16302 *567 (CommentGraphic 16321 16303 uid 15018,0 16322 16304 shape (Arc2D … … 16340 16322 oxt "112005,265000,114000,269004" 16341 16323 ) 16342 *56 9(Grouping16324 *568 (Grouping 16343 16325 uid 15020,0 16344 16326 optionalChildren [ 16345 *5 70(CommentGraphic16327 *569 (CommentGraphic 16346 16328 uid 15022,0 16347 16329 optionalChildren [ 16348 *57 1(Property16330 *570 (Property 16349 16331 uid 15024,0 16350 16332 pclass "_MW_GEOM_" … … 16378 16360 oxt "110000,265000,113998,269000" 16379 16361 ) 16380 *57 2(CommentGraphic16362 *571 (CommentGraphic 16381 16363 uid 15025,0 16382 16364 optionalChildren [ 16383 *57 3(Property16365 *572 (Property 16384 16366 uid 15027,0 16385 16367 pclass "_MW_GEOM_" … … 16425 16407 oxt "110000,265000,114000,269000" 16426 16408 ) 16427 *57 4(CommentGraphic16409 *573 (CommentGraphic 16428 16410 uid 15028,0 16429 16411 shape (PolyLine2D … … 16445 16427 oxt "112000,265000,112000,265000" 16446 16428 ) 16447 *57 5(CommentGraphic16429 *574 (CommentGraphic 16448 16430 uid 15030,0 16449 16431 optionalChildren [ 16450 *57 6(Property16432 *575 (Property 16451 16433 uid 15032,0 16452 16434 pclass "_MW_GEOM_" … … 16473 16455 oxt "110000,269000,110000,269000" 16474 16456 ) 16475 *57 7(CommentGraphic16457 *576 (CommentGraphic 16476 16458 uid 15033,0 16477 16459 optionalChildren [ 16478 *57 8(Property16460 *577 (Property 16479 16461 uid 15035,0 16480 16462 pclass "_MW_GEOM_" … … 16501 16483 oxt "114000,269000,114000,269000" 16502 16484 ) 16503 *57 9(CptPort16485 *578 (CptPort 16504 16486 uid 15160,0 16505 16487 optionalChildren [ 16506 *5 80(Line16488 *579 (Line 16507 16489 uid 15164,0 16508 16490 sl 0 … … 16556 16538 ) 16557 16539 ) 16558 *58 1(CptPort16540 *580 (CptPort 16559 16541 uid 15165,0 16560 16542 optionalChildren [ 16561 *58 2(Line16543 *581 (Line 16562 16544 uid 15169,0 16563 16545 sl 0 … … 16631 16613 stg "VerticalLayoutStrategy" 16632 16614 textVec [ 16633 *58 3(Text16615 *582 (Text 16634 16616 uid 15039,0 16635 16617 va (VaSet … … 16641 16623 blo "148500,89300" 16642 16624 ) 16643 *58 4(Text16625 *583 (Text 16644 16626 uid 15040,0 16645 16627 va (VaSet … … 16650 16632 blo "148500,90300" 16651 16633 ) 16652 *58 5(Text16634 *584 (Text 16653 16635 uid 15041,0 16654 16636 va (VaSet … … 16695 16677 ) 16696 16678 ) 16697 *58 6(MWC16679 *585 (MWC 16698 16680 uid 15058,0 16699 16681 optionalChildren [ 16700 *58 7(CptPort16682 *586 (CptPort 16701 16683 uid 15045,0 16702 16684 optionalChildren [ 16703 *58 8(Line16685 *587 (Line 16704 16686 uid 15049,0 16705 16687 layer 5 … … 16763 16745 ) 16764 16746 ) 16765 *58 9(CptPort16747 *588 (CptPort 16766 16748 uid 15050,0 16767 16749 optionalChildren [ 16768 *5 90(Line16750 *589 (Line 16769 16751 uid 15054,0 16770 16752 layer 5 … … 16779 16761 ] 16780 16762 ) 16781 *59 1(Circle16763 *590 (Circle 16782 16764 uid 15055,0 16783 16765 va (VaSet … … 16841 16823 ) 16842 16824 ) 16843 *59 2(CommentGraphic16825 *591 (CommentGraphic 16844 16826 uid 15056,0 16845 16827 shape (CustomPolygon … … 16883 16865 stg "VerticalLayoutStrategy" 16884 16866 textVec [ 16885 *59 3(Text16867 *592 (Text 16886 16868 uid 15061,0 16887 16869 va (VaSet … … 16893 16875 blo "155350,77900" 16894 16876 ) 16895 *59 4(Text16877 *593 (Text 16896 16878 uid 15062,0 16897 16879 va (VaSet … … 16902 16884 blo "155350,78900" 16903 16885 ) 16904 *59 5(Text16886 *594 (Text 16905 16887 uid 15063,0 16906 16888 va (VaSet … … 16947 16929 ) 16948 16930 ) 16949 *59 6(Net16931 *595 (Net 16950 16932 uid 15077,0 16951 16933 decl (Decl … … 16968 16950 ) 16969 16951 ) 16970 *59 7(Net16952 *596 (Net 16971 16953 uid 15079,0 16972 16954 decl (Decl … … 16989 16971 ) 16990 16972 ) 16991 *59 8(Net16973 *597 (Net 16992 16974 uid 15126,0 16993 16975 decl (Decl … … 17010 16992 ) 17011 16993 ) 17012 *59 9(Wire16994 *598 (Wire 17013 16995 uid 322,0 17014 16996 shape (OrthoPolyLine … … 17049 17031 on &2 17050 17032 ) 17051 * 600(Wire17033 *599 (Wire 17052 17034 uid 328,0 17053 17035 shape (OrthoPolyLine … … 17088 17070 on &3 17089 17071 ) 17090 *60 1(Wire17072 *600 (Wire 17091 17073 uid 334,0 17092 17074 shape (OrthoPolyLine … … 17127 17109 on &4 17128 17110 ) 17129 *60 2(Wire17111 *601 (Wire 17130 17112 uid 364,0 17131 17113 shape (OrthoPolyLine … … 17167 17149 on &5 17168 17150 ) 17169 *60 3(Wire17151 *602 (Wire 17170 17152 uid 370,0 17171 17153 shape (OrthoPolyLine … … 17207 17189 on &6 17208 17190 ) 17209 *60 4(Wire17191 *603 (Wire 17210 17192 uid 376,0 17211 17193 shape (OrthoPolyLine … … 17245 17227 on &7 17246 17228 ) 17247 *60 5(Wire17229 *604 (Wire 17248 17230 uid 384,0 17249 17231 shape (OrthoPolyLine … … 17285 17267 on &8 17286 17268 ) 17287 *60 6(Wire17269 *605 (Wire 17288 17270 uid 392,0 17289 17271 shape (OrthoPolyLine … … 17325 17307 on &9 17326 17308 ) 17327 *60 7(Wire17309 *606 (Wire 17328 17310 uid 400,0 17329 17311 shape (OrthoPolyLine … … 17363 17345 on &10 17364 17346 ) 17365 *60 8(Wire17347 *607 (Wire 17366 17348 uid 408,0 17367 17349 shape (OrthoPolyLine … … 17401 17383 on &11 17402 17384 ) 17403 *60 9(Wire17385 *608 (Wire 17404 17386 uid 424,0 17405 17387 shape (OrthoPolyLine … … 17439 17421 on &12 17440 17422 ) 17441 *6 10(Wire17423 *609 (Wire 17442 17424 uid 432,0 17443 17425 shape (OrthoPolyLine … … 17477 17459 on &13 17478 17460 ) 17479 *61 1(Wire17461 *610 (Wire 17480 17462 uid 1411,0 17481 17463 shape (OrthoPolyLine … … 17516 17498 on &71 17517 17499 ) 17518 *61 2(Wire17500 *611 (Wire 17519 17501 uid 1425,0 17520 17502 shape (OrthoPolyLine … … 17555 17537 on &72 17556 17538 ) 17557 *61 3(Wire17539 *612 (Wire 17558 17540 uid 1682,0 17559 17541 shape (OrthoPolyLine … … 17594 17576 on &122 17595 17577 ) 17596 *61 4(Wire17578 *613 (Wire 17597 17579 uid 1983,0 17598 17580 shape (OrthoPolyLine … … 17602 17584 lineWidth 2 17603 17585 ) 17604 xt "-40250,6 8000,-21750,71000"17605 pts [ 17606 "-40250,6 8000"17607 "-36000,6 8000"17608 "-36000,7 1000"17609 "-21750,7 1000"17586 xt "-40250,69000,-21750,70000" 17587 pts [ 17588 "-40250,69000" 17589 "-36000,69000" 17590 "-36000,70000" 17591 "-21750,70000" 17610 17592 ] 17611 17593 ) … … 17633 17615 on &130 17634 17616 ) 17635 *61 5(Wire17617 *614 (Wire 17636 17618 uid 2299,0 17637 17619 shape (OrthoPolyLine … … 17641 17623 lineWidth 2 17642 17624 ) 17643 xt "750,66000,31250,73000" 17644 pts [ 17645 "31250,73000" 17646 "27000,73000" 17647 "27000,66000" 17648 "750,66000" 17625 xt "750,71000,27250,71000" 17626 pts [ 17627 "27250,71000" 17628 "750,71000" 17649 17629 ] 17650 17630 ) … … 17665 17645 va (VaSet 17666 17646 ) 17667 xt " 2000,65000,18700,66000"17647 xt "1000,70000,17700,71000" 17668 17648 st "ram_start_addr : (RAMADDRWIDTH64b-1:0)" 17669 blo " 2000,65800"17649 blo "1000,70800" 17670 17650 tm "WireNameMgr" 17671 17651 ) … … 17673 17653 on &131 17674 17654 ) 17675 *61 6(Wire17655 *615 (Wire 17676 17656 uid 2470,0 17677 17657 shape (OrthoPolyLine … … 17680 17660 vasetType 3 17681 17661 ) 17682 xt "63750,70000,87250,71000" 17683 pts [ 17684 "63750,71000" 17685 "78000,71000" 17686 "78000,70000" 17687 "87250,70000" 17662 xt "59750,71000,87250,71000" 17663 pts [ 17664 "59750,71000" 17665 "87250,71000" 17688 17666 ] 17689 17667 ) … … 17703 17681 va (VaSet 17704 17682 ) 17705 xt "6 4000,70000,67400,71000"17683 xt "60000,70000,63400,71000" 17706 17684 st "wiz_busy" 17707 blo "6 4000,70800"17685 blo "60000,70800" 17708 17686 tm "WireNameMgr" 17709 17687 ) … … 17711 17689 on &155 17712 17690 ) 17713 *61 7(Wire17691 *616 (Wire 17714 17692 uid 2476,0 17715 17693 shape (OrthoPolyLine … … 17718 17696 vasetType 3 17719 17697 ) 17720 xt "63750,71000,87250,72000" 17721 pts [ 17722 "63750,72000" 17723 "84000,72000" 17724 "84000,71000" 17725 "87250,71000" 17698 xt "59750,72000,87250,72000" 17699 pts [ 17700 "59750,72000" 17701 "87250,72000" 17726 17702 ] 17727 17703 ) … … 17741 17717 va (VaSet 17742 17718 ) 17743 xt "6 4000,71000,69100,72000"17719 xt "60000,71000,65100,72000" 17744 17720 st "wiz_write_ea" 17745 blo "6 4000,71800"17721 blo "60000,71800" 17746 17722 tm "WireNameMgr" 17747 17723 ) … … 17749 17725 on &156 17750 17726 ) 17751 *61 8(Wire17727 *617 (Wire 17752 17728 uid 2482,0 17753 17729 shape (OrthoPolyLine … … 17757 17733 lineWidth 2 17758 17734 ) 17759 xt "63750,72000,87250,79000" 17760 pts [ 17761 "63750,73000" 17762 "67000,73000" 17763 "67000,79000" 17764 "85000,79000" 17765 "85000,72000" 17766 "87250,72000" 17735 xt "59750,73000,87250,73000" 17736 pts [ 17737 "59750,73000" 17738 "87250,73000" 17767 17739 ] 17768 17740 ) … … 17783 17755 va (VaSet 17784 17756 ) 17785 xt "6 4000,72000,73400,73000"17757 xt "60000,72000,69400,73000" 17786 17758 st "wiz_write_length : (16:0)" 17787 blo "6 4000,72800"17759 blo "60000,72800" 17788 17760 tm "WireNameMgr" 17789 17761 ) … … 17791 17763 on &157 17792 17764 ) 17793 *61 9(Wire17765 *618 (Wire 17794 17766 uid 2488,0 17795 17767 shape (OrthoPolyLine … … 17799 17771 lineWidth 2 17800 17772 ) 17801 xt "63750,73000,87250,74000" 17802 pts [ 17803 "63750,74000" 17804 "84000,74000" 17805 "84000,73000" 17806 "87250,73000" 17773 xt "59750,74000,87250,74000" 17774 pts [ 17775 "59750,74000" 17776 "87250,74000" 17807 17777 ] 17808 17778 ) … … 17823 17793 va (VaSet 17824 17794 ) 17825 xt "6 4000,73000,82800,74000"17795 xt "60000,73000,78800,74000" 17826 17796 st "wiz_ram_start_addr : (RAMADDRWIDTH64b+1:0)" 17827 blo "6 4000,73800"17797 blo "60000,73800" 17828 17798 tm "WireNameMgr" 17829 17799 ) … … 17831 17801 on &158 17832 17802 ) 17833 *6 20(Wire17803 *619 (Wire 17834 17804 uid 2494,0 17835 17805 shape (OrthoPolyLine … … 17839 17809 lineWidth 2 17840 17810 ) 17841 xt "63750,74000,87250,80000" 17842 pts [ 17843 "63750,75000" 17844 "66000,75000" 17845 "66000,80000" 17846 "86000,80000" 17847 "86000,74000" 17848 "87250,74000" 17811 xt "59750,75000,87250,75000" 17812 pts [ 17813 "59750,75000" 17814 "87250,75000" 17849 17815 ] 17850 17816 ) … … 17865 17831 va (VaSet 17866 17832 ) 17867 xt "6 4000,74000,75800,75000"17833 xt "60000,74000,71800,75000" 17868 17834 st "wiz_number_of_channels : (3:0)" 17869 blo "6 4000,74800"17835 blo "60000,74800" 17870 17836 tm "WireNameMgr" 17871 17837 ) … … 17873 17839 on &159 17874 17840 ) 17875 *62 1(Wire17841 *620 (Wire 17876 17842 uid 2500,0 17877 17843 shape (OrthoPolyLine … … 17880 17846 vasetType 3 17881 17847 ) 17882 xt "63750,75000,87250,76000" 17883 pts [ 17884 "63750,76000" 17885 "84000,76000" 17886 "84000,75000" 17887 "87250,75000" 17848 xt "59750,76000,87250,76000" 17849 pts [ 17850 "59750,76000" 17851 "87250,76000" 17888 17852 ] 17889 17853 ) … … 17903 17867 va (VaSet 17904 17868 ) 17905 xt "6 4000,75000,69500,76000"17869 xt "60000,75000,65500,76000" 17906 17870 st "wiz_write_end" 17907 blo "6 4000,75800"17871 blo "60000,75800" 17908 17872 tm "WireNameMgr" 17909 17873 ) … … 17911 17875 on &160 17912 17876 ) 17913 *62 2(Wire17877 *621 (Wire 17914 17878 uid 2506,0 17915 17879 shape (OrthoPolyLine … … 17918 17882 vasetType 3 17919 17883 ) 17920 xt "63750,76000,87250,77000" 17921 pts [ 17922 "63750,77000" 17923 "71000,77000" 17924 "71000,76000" 17925 "87250,76000" 17884 xt "59750,77000,87250,77000" 17885 pts [ 17886 "59750,77000" 17887 "87250,77000" 17926 17888 ] 17927 17889 ) … … 17941 17903 va (VaSet 17942 17904 ) 17943 xt "6 4000,76000,70600,77000"17905 xt "60000,76000,66600,77000" 17944 17906 st "wiz_write_header" 17945 blo "6 4000,76800"17907 blo "60000,76800" 17946 17908 tm "WireNameMgr" 17947 17909 ) … … 17949 17911 on &161 17950 17912 ) 17951 *62 3(Wire17913 *622 (Wire 17952 17914 uid 2576,0 17953 17915 shape (OrthoPolyLine … … 17956 17918 vasetType 3 17957 17919 ) 17958 xt "750,67000,31250,74000" 17959 pts [ 17960 "750,67000" 17961 "26000,67000" 17962 "26000,74000" 17963 "31250,74000" 17920 xt "750,72000,27250,72000" 17921 pts [ 17922 "750,72000" 17923 "27250,72000" 17964 17924 ] 17965 17925 ) … … 17979 17939 va (VaSet 17980 17940 ) 17981 xt " 2000,66000,7300,67000"17941 xt "1000,71000,6300,72000" 17982 17942 st "ram_write_ea" 17983 blo " 2000,66800"17943 blo "1000,71800" 17984 17944 tm "WireNameMgr" 17985 17945 ) … … 17987 17947 on &162 17988 17948 ) 17989 *62 4(Wire17949 *623 (Wire 17990 17950 uid 2582,0 17991 17951 shape (OrthoPolyLine … … 17994 17954 vasetType 3 17995 17955 ) 17996 xt "750,68000,31250,75000" 17997 pts [ 17998 "750,68000" 17999 "25000,68000" 18000 "25000,75000" 18001 "31250,75000" 17956 xt "750,73000,27250,73000" 17957 pts [ 17958 "750,73000" 17959 "27250,73000" 18002 17960 ] 18003 17961 ) … … 18017 17975 va (VaSet 18018 17976 ) 18019 xt " 2000,67000,8300,68000"17977 xt "1000,72000,7300,73000" 18020 17978 st "ram_write_ready" 18021 blo " 2000,67800"17979 blo "1000,72800" 18022 17980 tm "WireNameMgr" 18023 17981 ) … … 18025 17983 on &163 18026 17984 ) 18027 *62 5(Wire17985 *624 (Wire 18028 17986 uid 2588,0 18029 17987 shape (OrthoPolyLine … … 18032 17990 vasetType 3 18033 17991 ) 18034 xt "750,73000,31250,78000" 18035 pts [ 18036 "750,73000" 18037 "23000,73000" 18038 "23000,78000" 18039 "31250,78000" 17992 xt "750,76000,27250,76000" 17993 pts [ 17994 "750,76000" 17995 "27250,76000" 18040 17996 ] 18041 17997 ) … … 18056 18012 va (VaSet 18057 18013 ) 18058 xt "1000,7 2000,5800,73000"18014 xt "1000,75000,5800,76000" 18059 18015 st "config_start" 18060 blo "1000,7 2800"18016 blo "1000,75800" 18061 18017 tm "WireNameMgr" 18062 18018 ) … … 18064 18020 on &164 18065 18021 ) 18066 *62 6(Wire18022 *625 (Wire 18067 18023 uid 2594,0 18068 18024 shape (OrthoPolyLine … … 18071 18027 vasetType 3 18072 18028 ) 18073 xt "750,75000,31250,80000" 18074 pts [ 18075 "750,75000" 18076 "21000,75000" 18077 "21000,80000" 18078 "31250,80000" 18029 xt "750,78000,27250,78000" 18030 pts [ 18031 "750,78000" 18032 "27250,78000" 18079 18033 ] 18080 18034 ) … … 18094 18048 va (VaSet 18095 18049 ) 18096 xt "1000,7 4000,6100,75000"18050 xt "1000,77000,6100,78000" 18097 18051 st "config_ready" 18098 blo "1000,7 4800"18052 blo "1000,77800" 18099 18053 tm "WireNameMgr" 18100 18054 ) … … 18102 18056 on &165 18103 18057 ) 18104 *62 7(Wire18058 *626 (Wire 18105 18059 uid 2600,0 18106 18060 shape (OrthoPolyLine … … 18109 18063 vasetType 3 18110 18064 ) 18111 xt "750,77000,31250,81000" 18112 pts [ 18113 "750,77000" 18114 "20000,77000" 18115 "20000,81000" 18116 "31250,81000" 18065 xt "750,79000,27250,79000" 18066 pts [ 18067 "750,79000" 18068 "27250,79000" 18117 18069 ] 18118 18070 ) … … 18132 18084 va (VaSet 18133 18085 ) 18134 xt "1000,7 6000,4000,77000"18086 xt "1000,78000,4000,79000" 18135 18087 st "roi_max" 18136 blo "1000,7 6800"18088 blo "1000,78800" 18137 18089 tm "WireNameMgr" 18138 18090 ) … … 18140 18092 on &166 18141 18093 ) 18142 *62 8(Wire18094 *627 (Wire 18143 18095 uid 2642,0 18144 18096 shape (OrthoPolyLine … … 18148 18100 lineWidth 2 18149 18101 ) 18150 xt "750,78000,31250,82000" 18151 pts [ 18152 "750,78000" 18153 "19000,78000" 18154 "19000,82000" 18155 "31250,82000" 18102 xt "750,80000,27250,80000" 18103 pts [ 18104 "750,80000" 18105 "27250,80000" 18156 18106 ] 18157 18107 ) … … 18172 18122 va (VaSet 18173 18123 ) 18174 xt "1000,7 7000,10100,78000"18124 xt "1000,79000,10100,80000" 18175 18125 st "package_length : (15:0)" 18176 blo "1000,7 7800"18126 blo "1000,79800" 18177 18127 tm "WireNameMgr" 18178 18128 ) … … 18180 18130 on &167 18181 18131 ) 18182 *62 9(Wire18132 *628 (Wire 18183 18133 uid 2778,0 18184 18134 shape (OrthoPolyLine … … 18218 18168 on &168 18219 18169 ) 18220 *6 30(Wire18170 *629 (Wire 18221 18171 uid 2786,0 18222 18172 shape (OrthoPolyLine … … 18258 18208 on &191 18259 18209 ) 18260 *63 1(Wire18210 *630 (Wire 18261 18211 uid 3888,0 18262 18212 optionalChildren [ 18263 *63 2(BdJunction18213 *631 (BdJunction 18264 18214 uid 4230,0 18265 18215 ps "OnConnectorStrategy" … … 18273 18223 ) 18274 18224 ) 18275 *63 3(BdJunction18225 *632 (BdJunction 18276 18226 uid 4244,0 18277 18227 ps "OnConnectorStrategy" … … 18324 18274 on &187 18325 18275 ) 18326 *63 4(Wire18276 *633 (Wire 18327 18277 uid 3984,0 18328 18278 shape (OrthoPolyLine … … 18365 18315 on &185 18366 18316 ) 18367 *63 5(Wire18317 *634 (Wire 18368 18318 uid 4042,0 18369 18319 shape (OrthoPolyLine … … 18403 18353 on &190 18404 18354 ) 18405 *63 6(Wire18355 *635 (Wire 18406 18356 uid 4226,0 18407 18357 shape (OrthoPolyLine … … 18419 18369 ) 18420 18370 start &189 18421 end &63 218371 end &631 18422 18372 sat 32 18423 18373 eat 32 … … 18443 18393 on &187 18444 18394 ) 18445 *63 7(Wire18395 *636 (Wire 18446 18396 uid 4240,0 18447 18397 shape (OrthoPolyLine … … 18459 18409 ) 18460 18410 start &335 18461 end &63 318411 end &632 18462 18412 sat 32 18463 18413 eat 32 … … 18482 18432 on &187 18483 18433 ) 18484 *63 8(Wire18434 *637 (Wire 18485 18435 uid 4272,0 18486 18436 shape (OrthoPolyLine … … 18520 18470 on &192 18521 18471 ) 18522 *63 9(Wire18472 *638 (Wire 18523 18473 uid 4401,0 18524 18474 shape (OrthoPolyLine … … 18558 18508 on &194 18559 18509 ) 18560 *6 40(Wire18510 *639 (Wire 18561 18511 uid 4407,0 18562 18512 shape (OrthoPolyLine … … 18596 18546 on &195 18597 18547 ) 18598 *64 1(Wire18548 *640 (Wire 18599 18549 uid 4419,0 18600 18550 shape (OrthoPolyLine … … 18634 18584 on &196 18635 18585 ) 18636 *64 2(Wire18586 *641 (Wire 18637 18587 uid 4537,0 18638 18588 shape (OrthoPolyLine … … 18642 18592 lineWidth 2 18643 18593 ) 18644 xt "-2 7000,66000,-21750,67000"18594 xt "-26000,67000,-21750,67000" 18645 18595 pts [ 18646 18596 "-21750,67000" 18647 "-25000,67000" 18648 "-25000,66000" 18649 "-27000,66000" 18597 "-26000,67000" 18650 18598 ] 18651 18599 ) … … 18676 18624 on &197 18677 18625 ) 18678 *64 3(Wire18626 *642 (Wire 18679 18627 uid 4545,0 18680 18628 shape (OrthoPolyLine … … 18713 18661 on &198 18714 18662 ) 18715 *64 4(Wire18663 *643 (Wire 18716 18664 uid 4671,0 18717 18665 shape (OrthoPolyLine … … 18751 18699 on &201 18752 18700 ) 18753 *64 5(Wire18701 *644 (Wire 18754 18702 uid 4679,0 18755 18703 shape (OrthoPolyLine … … 18789 18737 on &202 18790 18738 ) 18791 *64 6(Wire18739 *645 (Wire 18792 18740 uid 4687,0 18793 18741 shape (OrthoPolyLine … … 18827 18775 on &203 18828 18776 ) 18829 *64 7(Wire18777 *646 (Wire 18830 18778 uid 4695,0 18831 18779 shape (OrthoPolyLine … … 18865 18813 on &204 18866 18814 ) 18867 *64 8(Wire18815 *647 (Wire 18868 18816 uid 4743,0 18869 18817 shape (OrthoPolyLine … … 18903 18851 on &209 18904 18852 ) 18905 *64 9(Wire18853 *648 (Wire 18906 18854 uid 4757,0 18907 18855 optionalChildren [ 18908 *6 50(BdJunction18856 *649 (BdJunction 18909 18857 uid 6076,0 18910 18858 ps "OnConnectorStrategy" … … 18934 18882 ) 18935 18883 start &211 18936 end *65 1(BdJunction18884 end *650 (BdJunction 18937 18885 uid 6080,0 18938 18886 ps "OnConnectorStrategy" … … 18968 18916 on &188 18969 18917 ) 18970 *65 2(Wire18918 *651 (Wire 18971 18919 uid 4948,0 18972 18920 shape (OrthoPolyLine … … 19006 18954 on &230 19007 18955 ) 19008 *65 3(Wire18956 *652 (Wire 19009 18957 uid 4962,0 19010 18958 shape (OrthoPolyLine … … 19044 18992 on &232 19045 18993 ) 19046 *65 4(Wire18994 *653 (Wire 19047 18995 uid 5090,0 19048 18996 shape (OrthoPolyLine … … 19083 19031 on &252 19084 19032 ) 19085 *65 5(Wire19033 *654 (Wire 19086 19034 uid 5098,0 19087 19035 shape (OrthoPolyLine … … 19117 19065 on &253 19118 19066 ) 19119 *65 6(Wire19067 *655 (Wire 19120 19068 uid 5106,0 19121 19069 shape (OrthoPolyLine … … 19154 19102 on &254 19155 19103 ) 19156 *65 7(Wire19104 *656 (Wire 19157 19105 uid 5114,0 19158 19106 shape (OrthoPolyLine … … 19193 19141 on &255 19194 19142 ) 19195 *65 8(Wire19143 *657 (Wire 19196 19144 uid 5122,0 19197 19145 shape (OrthoPolyLine … … 19230 19178 on &256 19231 19179 ) 19232 *65 9(Wire19180 *658 (Wire 19233 19181 uid 5130,0 19234 19182 shape (OrthoPolyLine … … 19267 19215 on &257 19268 19216 ) 19269 *6 60(Wire19217 *659 (Wire 19270 19218 uid 5138,0 19271 19219 optionalChildren [ 19272 *66 1(BdJunction19220 *660 (BdJunction 19273 19221 uid 5400,0 19274 19222 ps "OnConnectorStrategy" … … 19320 19268 on &171 19321 19269 ) 19322 *66 2(Wire19270 *661 (Wire 19323 19271 uid 5146,0 19324 19272 shape (OrthoPolyLine … … 19356 19304 on &258 19357 19305 ) 19358 *66 3(Wire19306 *662 (Wire 19359 19307 uid 5168,0 19360 19308 shape (OrthoPolyLine … … 19363 19311 vasetType 3 19364 19312 ) 19365 xt "18000,8 8000,31250,88000"19313 xt "18000,86000,27250,88000" 19366 19314 pts [ 19367 19315 "18000,88000" 19368 "31250,88000" 19369 ] 19370 ) 19371 start &661 19316 "24000,88000" 19317 "24000,86000" 19318 "27250,86000" 19319 ] 19320 ) 19321 start &660 19372 19322 end &147 19373 19323 sat 32 … … 19384 19334 va (VaSet 19385 19335 ) 19386 xt "2 8000,87000,31400,88000"19336 xt "24000,85000,27400,86000" 19387 19337 st "roi_array" 19388 blo "2 8000,87800"19338 blo "24000,85800" 19389 19339 tm "WireNameMgr" 19390 19340 ) … … 19392 19342 on &171 19393 19343 ) 19394 *66 4(Wire19344 *663 (Wire 19395 19345 uid 5184,0 19396 19346 shape (OrthoPolyLine … … 19429 19379 on &259 19430 19380 ) 19431 *66 5(Wire19381 *664 (Wire 19432 19382 uid 5190,0 19433 19383 shape (OrthoPolyLine … … 19466 19416 on &260 19467 19417 ) 19468 *66 6(Wire19418 *665 (Wire 19469 19419 uid 5222,0 19470 19420 shape (OrthoPolyLine … … 19506 19456 on &261 19507 19457 ) 19508 *66 7(Wire19458 *666 (Wire 19509 19459 uid 5404,0 19510 19460 shape (OrthoPolyLine … … 19543 19493 on &264 19544 19494 ) 19545 *66 8(Wire19495 *667 (Wire 19546 19496 uid 5474,0 19547 19497 shape (OrthoPolyLine … … 19580 19530 on &262 19581 19531 ) 19582 *66 9(Wire19532 *668 (Wire 19583 19533 uid 5480,0 19584 19534 shape (OrthoPolyLine … … 19617 19567 on &263 19618 19568 ) 19619 *6 70(Wire19569 *669 (Wire 19620 19570 uid 5582,0 19621 19571 shape (OrthoPolyLine … … 19652 19602 on &187 19653 19603 ) 19654 *67 1(Wire19604 *670 (Wire 19655 19605 uid 5602,0 19656 19606 optionalChildren [ 19657 &651 19658 *672 (BdJunction 19659 uid 6086,0 19660 ps "OnConnectorStrategy" 19661 shape (Circle 19662 uid 6087,0 19663 va (VaSet 19664 vasetType 1 19665 ) 19666 xt "27600,46600,28400,47400" 19667 radius 400 19668 ) 19669 ) 19607 &650 19670 19608 ] 19671 19609 shape (OrthoPolyLine … … 19709 19647 on &188 19710 19648 ) 19711 *67 3(Wire19649 *671 (Wire 19712 19650 uid 5626,0 19713 19651 shape (OrthoPolyLine … … 19745 19683 on &266 19746 19684 ) 19747 *67 4(Wire19685 *672 (Wire 19748 19686 uid 5634,0 19749 19687 shape (OrthoPolyLine … … 19783 19721 on &265 19784 19722 ) 19785 *67 5(Wire19723 *673 (Wire 19786 19724 uid 5646,0 19787 19725 shape (OrthoPolyLine … … 19819 19757 on &185 19820 19758 ) 19821 *67 6(Wire19759 *674 (Wire 19822 19760 uid 5745,0 19823 19761 shape (OrthoPolyLine … … 19857 19795 on &276 19858 19796 ) 19859 *67 7(Wire19797 *675 (Wire 19860 19798 uid 5805,0 19861 19799 shape (OrthoPolyLine … … 19891 19829 on &187 19892 19830 ) 19893 *67 8(Wire19831 *676 (Wire 19894 19832 uid 5813,0 19895 19833 shape (OrthoPolyLine … … 19929 19867 on &293 19930 19868 ) 19931 *67 9(Wire19869 *677 (Wire 19932 19870 uid 5821,0 19933 19871 shape (OrthoPolyLine … … 19967 19905 on &294 19968 19906 ) 19969 *6 80(Wire19907 *678 (Wire 19970 19908 uid 5829,0 19971 19909 shape (OrthoPolyLine … … 20005 19943 on &295 20006 19944 ) 20007 *6 81(Wire19945 *679 (Wire 20008 19946 uid 5837,0 20009 19947 shape (OrthoPolyLine … … 20045 19983 on &296 20046 19984 ) 20047 *68 2(Wire19985 *680 (Wire 20048 19986 uid 5950,0 20049 19987 shape (OrthoPolyLine … … 20083 20021 on &301 20084 20022 ) 20085 *68 3(Wire20023 *681 (Wire 20086 20024 uid 5962,0 20087 20025 shape (OrthoPolyLine … … 20121 20059 on &302 20122 20060 ) 20123 *68 4(Wire20061 *682 (Wire 20124 20062 uid 6002,0 20125 20063 shape (OrthoPolyLine … … 20159 20097 on &304 20160 20098 ) 20161 *68 5(Wire20099 *683 (Wire 20162 20100 uid 6008,0 20163 20101 shape (OrthoPolyLine … … 20197 20135 on &303 20198 20136 ) 20199 *68 6(Wire20137 *684 (Wire 20200 20138 uid 6018,0 20201 20139 shape (OrthoPolyLine … … 20204 20142 vasetType 3 20205 20143 ) 20206 xt "750,74000,31250,79000" 20207 pts [ 20208 "750,74000" 20209 "22000,74000" 20210 "22000,79000" 20211 "31250,79000" 20144 xt "750,77000,27250,77000" 20145 pts [ 20146 "750,77000" 20147 "27250,77000" 20212 20148 ] 20213 20149 ) … … 20227 20163 va (VaSet 20228 20164 ) 20229 xt "1000,7 3000,8200,74000"20165 xt "1000,76000,8200,77000" 20230 20166 st "config_started_mm" 20231 blo "1000,7 3800"20167 blo "1000,76800" 20232 20168 tm "WireNameMgr" 20233 20169 ) … … 20235 20171 on &305 20236 20172 ) 20237 *68 7(Wire20173 *685 (Wire 20238 20174 uid 6064,0 20239 20175 shape (OrthoPolyLine … … 20270 20206 on &258 20271 20207 ) 20272 *68 8(Wire20208 *686 (Wire 20273 20209 uid 6072,0 20274 20210 shape (OrthoPolyLine … … 20286 20222 ) 20287 20223 start &366 20288 end &6 5020224 end &649 20289 20225 sat 32 20290 20226 eat 32 … … 20309 20245 on &188 20310 20246 ) 20311 *689 (Wire 20312 uid 6082,0 20313 shape (OrthoPolyLine 20314 uid 6083,0 20315 va (VaSet 20316 vasetType 3 20317 lineColor "0,32896,0" 20318 ) 20319 xt "28000,47000,31250,71000" 20320 pts [ 20321 "31250,71000" 20322 "28000,71000" 20323 "28000,47000" 20324 ] 20325 ) 20326 start &134 20327 end &672 20328 sat 32 20329 eat 32 20330 stc 0 20331 st 0 20332 sf 1 20333 si 0 20334 tg (WTG 20335 uid 6084,0 20336 ps "ConnStartEndStrategy" 20337 stg "STSignalDisplayStrategy" 20338 f (Text 20339 uid 6085,0 20340 va (VaSet 20341 ) 20342 xt "28000,70000,31100,71000" 20343 st "CLK_25" 20344 blo "28000,70800" 20345 tm "WireNameMgr" 20346 ) 20347 ) 20348 on &188 20349 ) 20350 *690 (Wire 20247 *687 (Wire 20351 20248 uid 6160,0 20352 20249 shape (OrthoPolyLine … … 20386 20283 on &306 20387 20284 ) 20388 *6 91(Wire20285 *688 (Wire 20389 20286 uid 6276,0 20390 20287 shape (OrthoPolyLine … … 20393 20290 vasetType 3 20394 20291 ) 20395 xt "-61000,6 7000,-52750,67000"20396 pts [ 20397 "-61000,6 7000"20398 "-52750,6 7000"20292 xt "-61000,68000,-52750,68000" 20293 pts [ 20294 "-61000,68000" 20295 "-52750,68000" 20399 20296 ] 20400 20297 ) … … 20412 20309 va (VaSet 20413 20310 ) 20414 xt "-58000,6 6000,-53500,67000"20311 xt "-58000,67000,-53500,68000" 20415 20312 st "CLK_25_PS" 20416 blo "-58000,6 6800"20313 blo "-58000,67800" 20417 20314 tm "WireNameMgr" 20418 20315 ) … … 20420 20317 on &185 20421 20318 ) 20422 *6 92(Wire20319 *689 (Wire 20423 20320 uid 6362,0 20424 20321 shape (OrthoPolyLine … … 20433 20330 ] 20434 20331 ) 20435 start &54 620332 start &545 20436 20333 end &309 20437 20334 ss 0 … … 20459 20356 on &308 20460 20357 ) 20461 *69 3(Wire20358 *690 (Wire 20462 20359 uid 6452,0 20463 20360 shape (OrthoPolyLine … … 20495 20392 on &310 20496 20393 ) 20497 *69 4(Wire20394 *691 (Wire 20498 20395 uid 6540,0 20499 20396 shape (OrthoPolyLine … … 20509 20406 ) 20510 20407 start &315 20511 end &47 720408 end &476 20512 20409 sat 32 20513 20410 eat 32 … … 20532 20429 on &329 20533 20430 ) 20534 *69 5(Wire20431 *692 (Wire 20535 20432 uid 6548,0 20536 20433 shape (OrthoPolyLine … … 20569 20466 on &310 20570 20467 ) 20571 *69 6(Wire20468 *693 (Wire 20572 20469 uid 8416,0 20573 20470 shape (OrthoPolyLine … … 20576 20473 vasetType 3 20577 20474 ) 20578 xt "63750,77000,87250,78000" 20579 pts [ 20580 "63750,78000" 20581 "84000,78000" 20582 "84000,77000" 20583 "87250,77000" 20475 xt "59750,78000,87250,78000" 20476 pts [ 20477 "59750,78000" 20478 "87250,78000" 20584 20479 ] 20585 20480 ) … … 20599 20494 va (VaSet 20600 20495 ) 20601 xt "6 4000,77000,67000,78000"20496 xt "60000,77000,63000,78000" 20602 20497 st "wiz_ack" 20603 blo "6 4000,77800"20498 blo "60000,77800" 20604 20499 tm "WireNameMgr" 20605 20500 ) … … 20607 20502 on &341 20608 20503 ) 20609 *69 7(Wire20504 *694 (Wire 20610 20505 uid 8732,0 20611 20506 shape (OrthoPolyLine … … 20645 20540 on &360 20646 20541 ) 20647 *69 8(Wire20542 *695 (Wire 20648 20543 uid 8738,0 20649 20544 shape (OrthoPolyLine … … 20681 20576 on &361 20682 20577 ) 20683 *69 9(Wire20578 *696 (Wire 20684 20579 uid 8752,0 20685 20580 shape (OrthoPolyLine … … 20716 20611 on &361 20717 20612 ) 20718 * 700(Wire20613 *697 (Wire 20719 20614 uid 9006,0 20720 20615 shape (OrthoPolyLine … … 20754 20649 on &362 20755 20650 ) 20756 * 701(Wire20651 *698 (Wire 20757 20652 uid 9233,0 20758 20653 shape (OrthoPolyLine … … 20789 20684 on &376 20790 20685 ) 20791 * 702(Wire20686 *699 (Wire 20792 20687 uid 9241,0 20793 20688 shape (OrthoPolyLine … … 20824 20719 on &377 20825 20720 ) 20826 *70 3(Wire20721 *700 (Wire 20827 20722 uid 9253,0 20828 20723 shape (OrthoPolyLine … … 20858 20753 on &376 20859 20754 ) 20860 *70 4(Wire20755 *701 (Wire 20861 20756 uid 9261,0 20862 20757 shape (OrthoPolyLine … … 20892 20787 on &377 20893 20788 ) 20894 *70 5(Wire20789 *702 (Wire 20895 20790 uid 9943,0 20896 20791 shape (OrthoPolyLine … … 20927 20822 on &378 20928 20823 ) 20929 *70 6(Wire20824 *703 (Wire 20930 20825 uid 9951,0 20931 20826 shape (OrthoPolyLine … … 20962 20857 on &379 20963 20858 ) 20964 *70 7(Wire20859 *704 (Wire 20965 20860 uid 10010,0 20966 20861 shape (OrthoPolyLine … … 21000 20895 on &398 21001 20896 ) 21002 *70 8(Wire20897 *705 (Wire 21003 20898 uid 10018,0 21004 20899 shape (OrthoPolyLine … … 21036 20931 on &379 21037 20932 ) 21038 *70 9(Wire20933 *706 (Wire 21039 20934 uid 10036,0 21040 20935 shape (OrthoPolyLine … … 21070 20965 on &378 21071 20966 ) 21072 *7 10(Wire20967 *707 (Wire 21073 20968 uid 10194,0 21074 20969 shape (OrthoPolyLine … … 21110 21005 on &399 21111 21006 ) 21112 *7 11(Wire21007 *708 (Wire 21113 21008 uid 10202,0 21114 21009 shape (OrthoPolyLine … … 21148 21043 on &400 21149 21044 ) 21150 *7 12(Wire21045 *709 (Wire 21151 21046 uid 10266,0 21152 21047 shape (OrthoPolyLine … … 21181 21076 ) 21182 21077 ) 21183 on &49 921184 ) 21185 *71 3(Wire21078 on &498 21079 ) 21080 *710 (Wire 21186 21081 uid 10298,0 21187 21082 shape (OrthoPolyLine … … 21219 21114 on &402 21220 21115 ) 21221 *71 4(Wire21116 *711 (Wire 21222 21117 uid 10304,0 21223 21118 shape (OrthoPolyLine … … 21255 21150 on &403 21256 21151 ) 21257 *71 5(Wire21152 *712 (Wire 21258 21153 uid 10310,0 21259 21154 shape (OrthoPolyLine … … 21291 21186 on &404 21292 21187 ) 21293 *71 6(Wire21188 *713 (Wire 21294 21189 uid 10316,0 21295 21190 shape (OrthoPolyLine … … 21329 21224 on &405 21330 21225 ) 21331 *71 7(Wire21226 *714 (Wire 21332 21227 uid 10322,0 21333 21228 shape (OrthoPolyLine … … 21367 21262 on &406 21368 21263 ) 21369 *71 8(Wire21264 *715 (Wire 21370 21265 uid 10431,0 21371 21266 shape (OrthoPolyLine … … 21404 21299 on &401 21405 21300 ) 21406 *719 (Wire 21407 uid 10439,0 21408 optionalChildren [ 21409 *720 (BdJunction 21410 uid 12639,0 21411 ps "OnConnectorStrategy" 21412 shape (Circle 21413 uid 12640,0 21414 va (VaSet 21415 vasetType 1 21416 ) 21417 xt "-54400,71600,-53600,72400" 21418 radius 400 21419 ) 21420 ) 21421 ] 21422 shape (OrthoPolyLine 21423 uid 10440,0 21424 va (VaSet 21425 vasetType 3 21426 ) 21427 xt "-54000,68000,-21750,72000" 21428 pts [ 21429 "-21750,72000" 21430 "-54000,72000" 21431 "-54000,68000" 21432 "-52750,68000" 21433 ] 21434 ) 21435 start &30 21436 end &125 21437 sat 32 21438 eat 32 21439 st 0 21440 sf 1 21441 si 0 21442 tg (WTG 21443 uid 10441,0 21444 ps "ConnStartEndStrategy" 21445 stg "STSignalDisplayStrategy" 21446 f (Text 21447 uid 10442,0 21448 va (VaSet 21449 ) 21450 xt "-25750,71000,-21150,72000" 21451 st "trigger_out" 21452 blo "-25750,71800" 21453 tm "WireNameMgr" 21454 ) 21455 ) 21456 on &431 21457 ) 21458 *721 (Wire 21301 *716 (Wire 21459 21302 uid 10467,0 21460 21303 shape (OrthoPolyLine … … 21463 21306 vasetType 3 21464 21307 ) 21465 xt "750,69000,31250,76000" 21466 pts [ 21467 "31250,76000" 21468 "24000,76000" 21469 "24000,69000" 21470 "750,69000" 21308 xt "750,74000,27250,74000" 21309 pts [ 21310 "27250,74000" 21311 "750,74000" 21471 21312 ] 21472 21313 ) … … 21487 21328 va (VaSet 21488 21329 ) 21489 xt " 2000,68000,9800,69000"21330 xt "1000,73000,8800,74000" 21490 21331 st "ram_write_ready_ack" 21491 blo " 2000,68800"21332 blo "1000,73800" 21492 21333 tm "WireNameMgr" 21493 21334 ) 21494 21335 ) 21495 on &43 221496 ) 21497 *7 22(Wire21336 on &431 21337 ) 21338 *717 (Wire 21498 21339 uid 10629,0 21499 21340 shape (OrthoPolyLine … … 21528 21369 ) 21529 21370 ) 21530 on &43 321531 ) 21532 *7 23(Wire21371 on &432 21372 ) 21373 *718 (Wire 21533 21374 uid 10637,0 21534 21375 shape (OrthoPolyLine … … 21563 21404 ) 21564 21405 ) 21565 on &43 421566 ) 21567 *7 24(Wire21406 on &433 21407 ) 21408 *719 (Wire 21568 21409 uid 10685,0 21569 21410 shape (OrthoPolyLine … … 21578 21419 ] 21579 21420 ) 21580 end &44 721421 end &446 21581 21422 sat 16 21582 21423 eat 32 … … 21598 21439 ) 21599 21440 ) 21600 on &43 421601 ) 21602 *72 5(Wire21441 on &433 21442 ) 21443 *720 (Wire 21603 21444 uid 10691,0 21604 21445 shape (OrthoPolyLine … … 21613 21454 ] 21614 21455 ) 21615 end &44 821456 end &447 21616 21457 sat 16 21617 21458 eat 32 … … 21633 21474 ) 21634 21475 ) 21635 on &43 321636 ) 21637 *72 6(Wire21476 on &432 21477 ) 21478 *721 (Wire 21638 21479 uid 10699,0 21639 21480 shape (OrthoPolyLine … … 21649 21490 ] 21650 21491 ) 21651 end &44 221492 end &441 21652 21493 sat 16 21653 21494 eat 32 … … 21671 21512 on &187 21672 21513 ) 21673 *72 7(Wire21514 *722 (Wire 21674 21515 uid 10707,0 21675 21516 shape (OrthoPolyLine … … 21684 21525 ] 21685 21526 ) 21686 end &44 621527 end &445 21687 21528 sat 16 21688 21529 eat 32 … … 21704 21545 ) 21705 21546 ) 21706 on &45 321707 ) 21708 *72 8(Wire21547 on &452 21548 ) 21549 *723 (Wire 21709 21550 uid 10723,0 21710 21551 shape (OrthoPolyLine … … 21719 21560 ] 21720 21561 ) 21721 start &44 321722 end &43 621562 start &442 21563 end &435 21723 21564 sat 32 21724 21565 eat 32 … … 21742 21583 ) 21743 21584 ) 21744 on &43 521745 ) 21746 *72 9(Wire21585 on &434 21586 ) 21587 *724 (Wire 21747 21588 uid 10737,0 21748 21589 shape (OrthoPolyLine … … 21757 21598 ] 21758 21599 ) 21759 start &44 421760 end &43 821600 start &443 21601 end &437 21761 21602 sat 32 21762 21603 eat 32 … … 21780 21621 ) 21781 21622 ) 21782 on &43 721783 ) 21784 *7 30(Wire21623 on &436 21624 ) 21625 *725 (Wire 21785 21626 uid 10751,0 21786 21627 shape (OrthoPolyLine … … 21795 21636 ] 21796 21637 ) 21797 start &44 521798 end &4 4021638 start &444 21639 end &439 21799 21640 sat 32 21800 21641 eat 32 … … 21818 21659 ) 21819 21660 ) 21820 on &43 921821 ) 21822 *7 31(Wire21661 on &438 21662 ) 21663 *726 (Wire 21823 21664 uid 11405,0 21824 21665 shape (OrthoPolyLine … … 21854 21695 ) 21855 21696 ) 21856 on &45 321857 ) 21858 *7 32(Wire21697 on &452 21698 ) 21699 *727 (Wire 21859 21700 uid 11858,0 21860 21701 shape (OrthoPolyLine … … 21889 21730 ) 21890 21731 ) 21891 on &45 421892 ) 21893 *7 33(Wire21732 on &453 21733 ) 21734 *728 (Wire 21894 21735 uid 11952,0 21895 21736 shape (OrthoPolyLine … … 21904 21745 ] 21905 21746 ) 21906 end &46 121747 end &460 21907 21748 sat 16 21908 21749 eat 32 … … 21925 21766 ) 21926 21767 ) 21927 on &45 421928 ) 21929 *7 34(Wire21768 on &453 21769 ) 21770 *729 (Wire 21930 21771 uid 12306,0 21931 21772 shape (OrthoPolyLine … … 21941 21782 ) 21942 21783 start &411 21943 end &45 921784 end &458 21944 21785 sat 32 21945 21786 eat 32 … … 21963 21804 ) 21964 21805 ) 21965 on &473 21966 ) 21967 *735 (Wire 21968 uid 12635,0 21969 shape (OrthoPolyLine 21970 uid 12636,0 21971 va (VaSet 21972 vasetType 3 21973 ) 21974 xt "-55250,72000,-54000,72000" 21975 pts [ 21976 "-54000,72000" 21977 "-55250,72000" 21978 ] 21979 ) 21980 start &720 21981 end &476 21982 sat 32 21983 eat 32 21984 stc 0 21985 st 0 21986 sf 1 21987 si 0 21988 tg (WTG 21989 uid 12637,0 21990 ps "ConnStartEndStrategy" 21991 stg "STSignalDisplayStrategy" 21992 f (Text 21993 uid 12638,0 21994 va (VaSet 21995 ) 21996 xt "-54000,71000,-49400,72000" 21997 st "trigger_out" 21998 blo "-54000,71800" 21999 tm "WireNameMgr" 22000 ) 22001 ) 22002 on &431 22003 ) 22004 *736 (Wire 21806 on &472 21807 ) 21808 *730 (Wire 22005 21809 uid 12643,0 22006 21810 shape (OrthoPolyLine … … 22017 21821 ] 22018 21822 ) 22019 start &45 622020 end &47 521823 start &455 21824 end &474 22021 21825 sat 32 22022 21826 eat 32 … … 22040 21844 ) 22041 21845 ) 22042 on &48 422043 ) 22044 *73 7(Wire21846 on &483 21847 ) 21848 *731 (Wire 22045 21849 uid 12649,0 22046 21850 shape (OrthoPolyLine … … 22052 21856 pts [ 22053 21857 "-21750,74000" 22054 "-38000,74000"22055 21858 "-55250,74000" 22056 21859 ] 22057 21860 ) 22058 21861 start &66 22059 end &47 821862 end &477 22060 21863 sat 32 22061 21864 eat 32 … … 22077 21880 ) 22078 21881 ) 22079 on &48 522080 ) 22081 *73 8(Wire21882 on &484 21883 ) 21884 *732 (Wire 22082 21885 uid 12655,0 22083 21886 shape (OrthoPolyLine … … 22094 21897 ) 22095 21898 start &67 22096 end &47 921899 end &478 22097 21900 sat 32 22098 21901 eat 32 … … 22114 21917 ) 22115 21918 ) 22116 on &48 622117 ) 22118 *73 9(Wire21919 on &485 21920 ) 21921 *733 (Wire 22119 21922 uid 12687,0 22120 21923 shape (OrthoPolyLine … … 22132 21935 ] 22133 21936 ) 22134 end &4 8021937 end &479 22135 21938 sat 16 22136 21939 eat 32 … … 22154 21957 on &188 22155 21958 ) 22156 *7 40(Wire21959 *734 (Wire 22157 21960 uid 12707,0 22158 21961 shape (OrthoPolyLine … … 22167 21970 ] 22168 21971 ) 22169 start &44 922170 end &48 821972 start &448 21973 end &487 22171 21974 sat 32 22172 21975 eat 32 … … 22190 21993 ) 22191 21994 ) 22192 on &48 722193 ) 22194 *7 41(Wire21995 on &486 21996 ) 21997 *735 (Wire 22195 21998 uid 13143,0 22196 21999 shape (OrthoPolyLine … … 22199 22002 vasetType 3 22200 22003 ) 22201 xt " 63750,62000,69000,62000"22202 pts [ 22203 " 69000,62000"22204 " 63750,62000"22205 ] 22206 ) 22207 end &4 9022004 xt "72750,62000,78000,62000" 22005 pts [ 22006 "78000,62000" 22007 "72750,62000" 22008 ] 22009 ) 22010 end &489 22208 22011 sat 16 22209 22012 eat 32 … … 22219 22022 va (VaSet 22220 22023 ) 22221 xt " 65000,61000,68100,62000"22024 xt "74000,61000,77100,62000" 22222 22025 st "CLK_25" 22223 blo " 65000,61800"22026 blo "74000,61800" 22224 22027 tm "WireNameMgr" 22225 22028 ) … … 22227 22030 on &188 22228 22031 ) 22229 *7 42(Wire22032 *736 (Wire 22230 22033 uid 13159,0 22231 22034 shape (OrthoPolyLine … … 22234 22037 vasetType 3 22235 22038 ) 22236 xt " 63750,63000,87250,67000"22039 xt "72750,63000,87250,67000" 22237 22040 pts [ 22238 22041 "87250,67000" 22239 "7 9000,67000"22240 "7 9000,63000"22241 " 63750,63000"22042 "77000,67000" 22043 "77000,63000" 22044 "72750,63000" 22242 22045 ] 22243 22046 ) 22244 22047 start &114 22245 end &49 122048 end &490 22246 22049 sat 32 22247 22050 eat 32 … … 22263 22066 ) 22264 22067 ) 22265 on &49 722266 ) 22267 *7 43(Wire22068 on &496 22069 ) 22070 *737 (Wire 22268 22071 uid 13165,0 22269 22072 shape (OrthoPolyLine … … 22273 22076 lineWidth 2 22274 22077 ) 22275 xt " 63750,64000,87250,68000"22078 xt "72750,64000,87250,68000" 22276 22079 pts [ 22277 22080 "87250,68000" 22278 "7 8000,68000"22279 "7 8000,64000"22280 " 63750,64000"22081 "76000,68000" 22082 "76000,64000" 22083 "72750,64000" 22281 22084 ] 22282 22085 ) 22283 22086 start &115 22284 end &49 222087 end &491 22285 22088 sat 32 22286 22089 eat 32 … … 22303 22106 ) 22304 22107 ) 22305 on &49 822306 ) 22307 *7 44(Wire22108 on &497 22109 ) 22110 *738 (Wire 22308 22111 uid 13210,0 22309 22112 shape (OrthoPolyLine … … 22312 22115 vasetType 3 22313 22116 ) 22314 xt " 42000,62000,50250,62000"22315 pts [ 22316 "5 0250,62000"22317 " 42000,62000"22318 ] 22319 ) 22320 start &49 322321 end &50 222117 xt "54000,62000,59250,62000" 22118 pts [ 22119 "59250,62000" 22120 "54000,62000" 22121 ] 22122 ) 22123 start &492 22124 end &501 22322 22125 sat 32 22323 22126 eat 32 … … 22333 22136 va (VaSet 22334 22137 ) 22335 xt " 46250,61000,49450,62000"22138 xt "53250,61000,56450,62000" 22336 22139 st "trigger1" 22337 blo " 46250,61800"22140 blo "53250,61800" 22338 22141 tm "WireNameMgr" 22339 22142 ) 22340 22143 ) 22341 on & 50022342 ) 22343 *7 45(Wire22144 on &499 22145 ) 22146 *739 (Wire 22344 22147 uid 13216,0 22345 22148 shape (OrthoPolyLine … … 22348 22151 vasetType 3 22349 22152 ) 22350 xt " 42000,60000,45000,60000"22351 pts [ 22352 " 45000,60000"22353 " 42000,60000"22354 ] 22355 ) 22356 end &50 722153 xt "54000,60000,59000,60000" 22154 pts [ 22155 "59000,60000" 22156 "54000,60000" 22157 ] 22158 ) 22159 end &506 22357 22160 sat 16 22358 22161 eat 32 … … 22368 22171 uid 13221,0 22369 22172 va (VaSet 22370 isHidden 1 22371 ) 22372 xt "43000,59000,47800,60000" 22173 ) 22174 xt "54000,59000,58800,60000" 22373 22175 st "s_trigger_0" 22374 blo " 43000,59800"22176 blo "54000,59800" 22375 22177 tm "WireNameMgr" 22376 22178 ) 22377 22179 ) 22378 on &49 922379 ) 22380 *74 6(Wire22180 on &498 22181 ) 22182 *740 (Wire 22381 22183 uid 13224,0 22382 22184 shape (OrthoPolyLine … … 22385 22187 vasetType 3 22386 22188 ) 22387 xt " 33000,61000,36000,61000"22388 pts [ 22389 " 36000,61000"22390 " 33000,61000"22391 ] 22392 ) 22393 start &50 422189 xt "45000,61000,48000,61000" 22190 pts [ 22191 "48000,61000" 22192 "45000,61000" 22193 ] 22194 ) 22195 start &503 22394 22196 sat 32 22395 22197 eat 16 … … 22405 22207 uid 13229,0 22406 22208 va (VaSet 22407 isHidden 1 22408 ) 22409 xt "34000,60000,37600,61000" 22209 ) 22210 xt "45000,60000,48600,61000" 22410 22211 st "s_trigger" 22411 blo " 34000,60800"22212 blo "45000,60800" 22412 22213 tm "WireNameMgr" 22413 22214 ) … … 22415 22216 on &401 22416 22217 ) 22417 *74 7(Wire22218 *741 (Wire 22418 22219 uid 13695,0 22419 22220 shape (OrthoPolyLine … … 22429 22230 ] 22430 22231 ) 22431 start &52 422232 start &523 22432 22233 end &116 22433 22234 sat 32 … … 22452 22253 ) 22453 22254 ) 22454 on &52 522455 ) 22456 *74 8(Wire22255 on &524 22256 ) 22257 *742 (Wire 22457 22258 uid 13921,0 22458 22259 shape (OrthoPolyLine … … 22491 22292 on &71 22492 22293 ) 22493 *74 9(Wire22294 *743 (Wire 22494 22295 uid 13929,0 22495 22296 shape (OrthoPolyLine … … 22528 22329 on &122 22529 22330 ) 22530 *7 50(Wire22331 *744 (Wire 22531 22332 uid 14048,0 22532 22333 shape (OrthoPolyLine … … 22541 22342 ] 22542 22343 ) 22543 start &52 622544 end &53 222344 start &525 22345 end &531 22545 22346 sat 32 22546 22347 eat 32 … … 22563 22364 ) 22564 22365 ) 22565 on &52 722566 ) 22567 *7 51(Wire22366 on &526 22367 ) 22368 *745 (Wire 22568 22369 uid 14171,0 22569 22370 shape (OrthoPolyLine … … 22579 22380 ] 22580 22381 ) 22581 start &52 822382 start &527 22582 22383 sat 32 22583 22384 eat 16 … … 22601 22402 ) 22602 22403 ) 22603 on &52 922604 ) 22605 *7 52(Wire22404 on &528 22405 ) 22406 *746 (Wire 22606 22407 uid 14427,0 22607 22408 shape (OrthoPolyLine … … 22616 22417 ] 22617 22418 ) 22618 end &53 122419 end &530 22619 22420 sat 16 22620 22421 eat 32 … … 22638 22439 on &187 22639 22440 ) 22640 *7 53(Wire22441 *747 (Wire 22641 22442 uid 14479,0 22642 22443 shape (OrthoPolyLine … … 22651 22452 ] 22652 22453 ) 22653 start &53 422654 end &5 4022454 start &533 22455 end &539 22655 22456 sat 32 22656 22457 eat 32 … … 22674 22475 ) 22675 22476 ) 22676 on &53 922677 ) 22678 *7 54(Wire22477 on &538 22478 ) 22479 *748 (Wire 22679 22480 uid 14493,0 22680 22481 shape (OrthoPolyLine … … 22689 22490 ] 22690 22491 ) 22691 start &53 522692 end &54 222492 start &534 22493 end &541 22693 22494 sat 32 22694 22495 eat 32 … … 22712 22513 ) 22713 22514 ) 22714 on &54 122715 ) 22716 *7 55(Wire22515 on &540 22516 ) 22517 *749 (Wire 22717 22518 uid 14622,0 22718 22519 shape (OrthoPolyLine … … 22728 22529 ] 22729 22530 ) 22730 start &53 322731 end &54 422531 start &532 22532 end &543 22732 22533 sat 32 22733 22534 eat 32 … … 22752 22553 ) 22753 22554 ) 22754 on &54 322755 ) 22756 *75 6(Wire22555 on &542 22556 ) 22557 *750 (Wire 22757 22558 uid 15071,0 22758 22559 shape (OrthoPolyLine … … 22768 22569 ) 22769 22570 start &101 22770 end &54 922571 end &548 22771 22572 sat 32 22772 22573 eat 32 … … 22788 22589 ) 22789 22590 ) 22790 on &59 622791 ) 22792 *75 7(Wire22591 on &595 22592 ) 22593 *751 (Wire 22793 22594 uid 15081,0 22794 22595 shape (OrthoPolyLine … … 22803 22604 ] 22804 22605 ) 22805 start &55 122806 end &58 922606 start &550 22607 end &588 22807 22608 sat 32 22808 22609 eat 32 … … 22826 22627 ) 22827 22628 ) 22828 on &59 722829 ) 22830 *75 8(Wire22629 on &596 22630 ) 22631 *752 (Wire 22831 22632 uid 15122,0 22832 22633 shape (OrthoPolyLine … … 22842 22643 ] 22843 22644 ) 22844 start &58 722845 end &56 422645 start &586 22646 end &563 22846 22647 sat 32 22847 22648 eat 32 … … 22864 22665 ) 22865 22666 ) 22866 on &59 822867 ) 22868 *75 9(Wire22667 on &597 22668 ) 22669 *753 (Wire 22869 22670 uid 15130,0 22870 22671 shape (OrthoPolyLine … … 22879 22680 ] 22880 22681 ) 22881 end &57 922682 end &578 22882 22683 es 0 22883 22684 sat 16 … … 22902 22703 ) 22903 22704 ) 22904 on &54 122905 ) 22906 *7 60(Wire22705 on &540 22706 ) 22707 *754 (Wire 22907 22708 uid 15138,0 22908 22709 shape (OrthoPolyLine … … 22917 22718 ] 22918 22719 ) 22919 end &58 122720 end &580 22920 22721 es 0 22921 22722 sat 16 … … 22940 22741 ) 22941 22742 ) 22942 on &539 22743 on &538 22744 ) 22745 *755 (Wire 22746 uid 15379,0 22747 shape (OrthoPolyLine 22748 uid 15380,0 22749 va (VaSet 22750 vasetType 3 22751 ) 22752 xt "29000,64000,29000,67250" 22753 pts [ 22754 "29000,64000" 22755 "29000,67250" 22756 ] 22757 ) 22758 end &134 22759 sat 16 22760 eat 32 22761 st 0 22762 sf 1 22763 si 0 22764 tg (WTG 22765 uid 15383,0 22766 ps "ConnStartEndStrategy" 22767 stg "STSignalDisplayStrategy" 22768 f (Text 22769 uid 15384,0 22770 va (VaSet 22771 ) 22772 xt "29000,64000,32100,65000" 22773 st "CLK_25" 22774 blo "29000,64800" 22775 tm "WireNameMgr" 22776 ) 22777 ) 22778 on &188 22943 22779 ) 22944 22780 ] … … 22954 22790 color "26368,26368,26368" 22955 22791 ) 22956 packageList *7 61(PackageList22792 packageList *756 (PackageList 22957 22793 uid 41,0 22958 22794 stg "VerticalLayoutStrategy" 22959 22795 textVec [ 22960 *7 62(Text22796 *757 (Text 22961 22797 uid 42,0 22962 22798 va (VaSet … … 22967 22803 blo "-163000,-15200" 22968 22804 ) 22969 *7 63(MLText22805 *758 (MLText 22970 22806 uid 43,0 22971 22807 va (VaSet … … 22992 22828 stg "VerticalLayoutStrategy" 22993 22829 textVec [ 22994 *7 64(Text22830 *759 (Text 22995 22831 uid 45,0 22996 22832 va (VaSet … … 23002 22838 blo "20000,800" 23003 22839 ) 23004 *76 5(Text22840 *760 (Text 23005 22841 uid 46,0 23006 22842 va (VaSet … … 23012 22848 blo "20000,1800" 23013 22849 ) 23014 *76 6(MLText22850 *761 (MLText 23015 22851 uid 47,0 23016 22852 va (VaSet … … 23022 22858 tm "BdCompilerDirectivesTextMgr" 23023 22859 ) 23024 *76 7(Text22860 *762 (Text 23025 22861 uid 48,0 23026 22862 va (VaSet … … 23032 22868 blo "20000,4800" 23033 22869 ) 23034 *76 8(MLText22870 *763 (MLText 23035 22871 uid 49,0 23036 22872 va (VaSet … … 23040 22876 tm "BdCompilerDirectivesTextMgr" 23041 22877 ) 23042 *76 9(Text22878 *764 (Text 23043 22879 uid 50,0 23044 22880 va (VaSet … … 23050 22886 blo "20000,5800" 23051 22887 ) 23052 *7 70(MLText22888 *765 (MLText 23053 22889 uid 51,0 23054 22890 va (VaSet … … 23062 22898 ) 23063 22899 windowSize "0,0,1281,1024" 23064 viewArea "- 85665,-1810,-19291,52928"22900 viewArea "-65668,47481,1175,102606" 23065 22901 cachedDiagramExtent "-174000,-25425,428157,346294" 23066 22902 pageSetupInfo (PageSetupInfo … … 23088 22924 hasePageBreakOrigin 1 23089 22925 pageBreakOrigin "-73000,0" 23090 lastUid 15 174,022926 lastUid 15388,0 23091 22927 defaultCommentText (CommentText 23092 22928 shape (Rectangle … … 23150 22986 stg "VerticalLayoutStrategy" 23151 22987 textVec [ 23152 *7 71(Text22988 *766 (Text 23153 22989 va (VaSet 23154 22990 font "Arial,8,1" … … 23159 22995 tm "BdLibraryNameMgr" 23160 22996 ) 23161 *7 72(Text22997 *767 (Text 23162 22998 va (VaSet 23163 22999 font "Arial,8,1" … … 23168 23004 tm "BlkNameMgr" 23169 23005 ) 23170 *7 73(Text23006 *768 (Text 23171 23007 va (VaSet 23172 23008 font "Arial,8,1" … … 23219 23055 stg "VerticalLayoutStrategy" 23220 23056 textVec [ 23221 *7 74(Text23057 *769 (Text 23222 23058 va (VaSet 23223 23059 font "Arial,8,1" … … 23227 23063 blo "550,4300" 23228 23064 ) 23229 *77 5(Text23065 *770 (Text 23230 23066 va (VaSet 23231 23067 font "Arial,8,1" … … 23235 23071 blo "550,5300" 23236 23072 ) 23237 *77 6(Text23073 *771 (Text 23238 23074 va (VaSet 23239 23075 font "Arial,8,1" … … 23284 23120 stg "VerticalLayoutStrategy" 23285 23121 textVec [ 23286 *77 7(Text23122 *772 (Text 23287 23123 va (VaSet 23288 23124 font "Arial,8,1" … … 23293 23129 tm "BdLibraryNameMgr" 23294 23130 ) 23295 *77 8(Text23131 *773 (Text 23296 23132 va (VaSet 23297 23133 font "Arial,8,1" … … 23302 23138 tm "CptNameMgr" 23303 23139 ) 23304 *77 9(Text23140 *774 (Text 23305 23141 va (VaSet 23306 23142 font "Arial,8,1" … … 23356 23192 stg "VerticalLayoutStrategy" 23357 23193 textVec [ 23358 *7 80(Text23194 *775 (Text 23359 23195 va (VaSet 23360 23196 font "Arial,8,1" … … 23364 23200 blo "500,4300" 23365 23201 ) 23366 *7 81(Text23202 *776 (Text 23367 23203 va (VaSet 23368 23204 font "Arial,8,1" … … 23372 23208 blo "500,5300" 23373 23209 ) 23374 *7 82(Text23210 *777 (Text 23375 23211 va (VaSet 23376 23212 font "Arial,8,1" … … 23417 23253 stg "VerticalLayoutStrategy" 23418 23254 textVec [ 23419 *7 83(Text23255 *778 (Text 23420 23256 va (VaSet 23421 23257 font "Arial,8,1" … … 23425 23261 blo "50,4300" 23426 23262 ) 23427 *7 84(Text23263 *779 (Text 23428 23264 va (VaSet 23429 23265 font "Arial,8,1" … … 23433 23269 blo "50,5300" 23434 23270 ) 23435 *78 5(Text23271 *780 (Text 23436 23272 va (VaSet 23437 23273 font "Arial,8,1" … … 23474 23310 stg "VerticalLayoutStrategy" 23475 23311 textVec [ 23476 *78 6(Text23312 *781 (Text 23477 23313 va (VaSet 23478 23314 font "Arial,8,1" … … 23483 23319 tm "HdlTextNameMgr" 23484 23320 ) 23485 *78 7(Text23321 *782 (Text 23486 23322 va (VaSet 23487 23323 font "Arial,8,1" … … 23886 23722 stg "VerticalLayoutStrategy" 23887 23723 textVec [ 23888 *78 8(Text23724 *783 (Text 23889 23725 va (VaSet 23890 23726 font "Arial,8,1" … … 23894 23730 blo "14100,20800" 23895 23731 ) 23896 *78 9(MLText23732 *784 (MLText 23897 23733 va (VaSet 23898 23734 ) … … 23946 23782 stg "VerticalLayoutStrategy" 23947 23783 textVec [ 23948 *7 90(Text23784 *785 (Text 23949 23785 va (VaSet 23950 23786 font "Arial,8,1" … … 23954 23790 blo "14100,20800" 23955 23791 ) 23956 *7 91(MLText23792 *786 (MLText 23957 23793 va (VaSet 23958 23794 ) … … 24079 23915 font "Arial,8,1" 24080 23916 ) 24081 xt "-174000,10 7600,-169300,108600"23917 xt "-174000,106800,-169300,107800" 24082 23918 st "Post User:" 24083 blo "-174000,10 8400"23919 blo "-174000,107600" 24084 23920 ) 24085 23921 postUserText (MLText … … 24094 23930 commonDM (CommonDM 24095 23931 ldm (LogicalDM 24096 suid 299,023932 suid 300,0 24097 23933 usingSuid 1 24098 emptyRow *7 92(LEmptyRow23934 emptyRow *787 (LEmptyRow 24099 23935 ) 24100 23936 uid 54,0 24101 23937 optionalChildren [ 24102 *7 93(RefLabelRowHdr24103 ) 24104 *7 94(TitleRowHdr24105 ) 24106 *79 5(FilterRowHdr24107 ) 24108 *79 6(RefLabelColHdr23938 *788 (RefLabelRowHdr 23939 ) 23940 *789 (TitleRowHdr 23941 ) 23942 *790 (FilterRowHdr 23943 ) 23944 *791 (RefLabelColHdr 24109 23945 tm "RefLabelColHdrMgr" 24110 23946 ) 24111 *79 7(RowExpandColHdr23947 *792 (RowExpandColHdr 24112 23948 tm "RowExpandColHdrMgr" 24113 23949 ) 24114 *79 8(GroupColHdr23950 *793 (GroupColHdr 24115 23951 tm "GroupColHdrMgr" 24116 23952 ) 24117 *79 9(NameColHdr23953 *794 (NameColHdr 24118 23954 tm "BlockDiagramNameColHdrMgr" 24119 23955 ) 24120 * 800(ModeColHdr23956 *795 (ModeColHdr 24121 23957 tm "BlockDiagramModeColHdrMgr" 24122 23958 ) 24123 * 801(TypeColHdr23959 *796 (TypeColHdr 24124 23960 tm "BlockDiagramTypeColHdrMgr" 24125 23961 ) 24126 * 802(BoundsColHdr23962 *797 (BoundsColHdr 24127 23963 tm "BlockDiagramBoundsColHdrMgr" 24128 23964 ) 24129 * 803(InitColHdr23965 *798 (InitColHdr 24130 23966 tm "BlockDiagramInitColHdrMgr" 24131 23967 ) 24132 * 804(EolColHdr23968 *799 (EolColHdr 24133 23969 tm "BlockDiagramEolColHdrMgr" 24134 23970 ) 24135 *80 5(LeafLogPort23971 *800 (LeafLogPort 24136 23972 port (LogicalPort 24137 23973 m 4 … … 24147 23983 uid 516,0 24148 23984 ) 24149 *80 6(LeafLogPort23985 *801 (LeafLogPort 24150 23986 port (LogicalPort 24151 23987 m 4 … … 24160 23996 uid 518,0 24161 23997 ) 24162 *80 7(LeafLogPort23998 *802 (LeafLogPort 24163 23999 port (LogicalPort 24164 24000 m 4 … … 24173 24009 uid 520,0 24174 24010 ) 24175 *80 8(LeafLogPort24011 *803 (LeafLogPort 24176 24012 port (LogicalPort 24177 24013 m 4 … … 24186 24022 uid 530,0 24187 24023 ) 24188 *80 9(LeafLogPort24024 *804 (LeafLogPort 24189 24025 port (LogicalPort 24190 24026 m 4 … … 24199 24035 uid 532,0 24200 24036 ) 24201 *8 10(LeafLogPort24037 *805 (LeafLogPort 24202 24038 port (LogicalPort 24203 24039 m 1 … … 24212 24048 uid 534,0 24213 24049 ) 24214 *8 11(LeafLogPort24050 *806 (LeafLogPort 24215 24051 port (LogicalPort 24216 24052 m 1 … … 24225 24061 uid 536,0 24226 24062 ) 24227 *8 12(LeafLogPort24063 *807 (LeafLogPort 24228 24064 port (LogicalPort 24229 24065 m 2 … … 24238 24074 uid 538,0 24239 24075 ) 24240 *8 13(LeafLogPort24076 *808 (LeafLogPort 24241 24077 port (LogicalPort 24242 24078 m 1 … … 24251 24087 uid 540,0 24252 24088 ) 24253 *8 14(LeafLogPort24089 *809 (LeafLogPort 24254 24090 port (LogicalPort 24255 24091 m 1 … … 24264 24100 uid 542,0 24265 24101 ) 24266 *81 5(LeafLogPort24102 *810 (LeafLogPort 24267 24103 port (LogicalPort 24268 24104 m 1 … … 24277 24113 uid 546,0 24278 24114 ) 24279 *81 6(LeafLogPort24115 *811 (LeafLogPort 24280 24116 port (LogicalPort 24281 24117 decl (Decl … … 24288 24124 uid 548,0 24289 24125 ) 24290 *81 7(LeafLogPort24126 *812 (LeafLogPort 24291 24127 port (LogicalPort 24292 24128 decl (Decl … … 24300 24136 uid 1455,0 24301 24137 ) 24302 *81 8(LeafLogPort24138 *813 (LeafLogPort 24303 24139 port (LogicalPort 24304 24140 decl (Decl … … 24313 24149 uid 1457,0 24314 24150 ) 24315 *81 9(LeafLogPort24151 *814 (LeafLogPort 24316 24152 port (LogicalPort 24317 24153 decl (Decl … … 24325 24161 uid 1694,0 24326 24162 ) 24327 *8 20(LeafLogPort24163 *815 (LeafLogPort 24328 24164 port (LogicalPort 24329 24165 lang 2 … … 24341 24177 uid 1993,0 24342 24178 ) 24343 *8 21(LeafLogPort24179 *816 (LeafLogPort 24344 24180 port (LogicalPort 24345 24181 m 4 … … 24356 24192 uid 2305,0 24357 24193 ) 24358 *8 22(LeafLogPort24194 *817 (LeafLogPort 24359 24195 port (LogicalPort 24360 24196 lang 2 … … 24369 24205 uid 2510,0 24370 24206 ) 24371 *8 23(LeafLogPort24207 *818 (LeafLogPort 24372 24208 port (LogicalPort 24373 24209 lang 2 … … 24383 24219 uid 2512,0 24384 24220 ) 24385 *8 24(LeafLogPort24221 *819 (LeafLogPort 24386 24222 port (LogicalPort 24387 24223 lang 2 … … 24398 24234 uid 2514,0 24399 24235 ) 24400 *82 5(LeafLogPort24236 *820 (LeafLogPort 24401 24237 port (LogicalPort 24402 24238 lang 2 … … 24414 24250 uid 2516,0 24415 24251 ) 24416 *82 6(LeafLogPort24252 *821 (LeafLogPort 24417 24253 port (LogicalPort 24418 24254 lang 2 … … 24429 24265 uid 2518,0 24430 24266 ) 24431 *82 7(LeafLogPort24267 *822 (LeafLogPort 24432 24268 port (LogicalPort 24433 24269 lang 2 … … 24443 24279 uid 2520,0 24444 24280 ) 24445 *82 8(LeafLogPort24281 *823 (LeafLogPort 24446 24282 port (LogicalPort 24447 24283 lang 2 … … 24457 24293 uid 2522,0 24458 24294 ) 24459 *82 9(LeafLogPort24295 *824 (LeafLogPort 24460 24296 port (LogicalPort 24461 24297 m 4 … … 24469 24305 uid 2604,0 24470 24306 ) 24471 *8 30(LeafLogPort24307 *825 (LeafLogPort 24472 24308 port (LogicalPort 24473 24309 m 4 … … 24482 24318 uid 2606,0 24483 24319 ) 24484 *8 31(LeafLogPort24320 *826 (LeafLogPort 24485 24321 port (LogicalPort 24486 24322 m 4 … … 24495 24331 uid 2608,0 24496 24332 ) 24497 *8 32(LeafLogPort24333 *827 (LeafLogPort 24498 24334 port (LogicalPort 24499 24335 m 4 … … 24507 24343 uid 2610,0 24508 24344 ) 24509 *8 33(LeafLogPort24345 *828 (LeafLogPort 24510 24346 port (LogicalPort 24511 24347 m 4 … … 24519 24355 uid 2612,0 24520 24356 ) 24521 *8 34(LeafLogPort24357 *829 (LeafLogPort 24522 24358 port (LogicalPort 24523 24359 m 4 … … 24532 24368 uid 2646,0 24533 24369 ) 24534 *83 5(LeafLogPort24370 *830 (LeafLogPort 24535 24371 port (LogicalPort 24536 24372 m 1 … … 24545 24381 uid 2812,0 24546 24382 ) 24547 *83 6(LeafLogPort24383 *831 (LeafLogPort 24548 24384 port (LogicalPort 24549 24385 m 4 … … 24557 24393 uid 2962,0 24558 24394 ) 24559 *83 7(LeafLogPort24395 *832 (LeafLogPort 24560 24396 port (LogicalPort 24561 24397 m 1 … … 24569 24405 uid 3902,0 24570 24406 ) 24571 *83 8(LeafLogPort24407 *833 (LeafLogPort 24572 24408 port (LogicalPort 24573 24409 m 1 … … 24581 24417 uid 4070,0 24582 24418 ) 24583 *83 9(LeafLogPort24419 *834 (LeafLogPort 24584 24420 port (LogicalPort 24585 24421 m 4 … … 24593 24429 uid 4212,0 24594 24430 ) 24595 *8 40(LeafLogPort24431 *835 (LeafLogPort 24596 24432 port (LogicalPort 24597 24433 decl (Decl … … 24604 24440 uid 4234,0 24605 24441 ) 24606 *8 41(LeafLogPort24442 *836 (LeafLogPort 24607 24443 port (LogicalPort 24608 24444 decl (Decl … … 24616 24452 uid 4262,0 24617 24453 ) 24618 *8 42(LeafLogPort24454 *837 (LeafLogPort 24619 24455 port (LogicalPort 24620 24456 decl (Decl … … 24627 24463 uid 4276,0 24628 24464 ) 24629 *8 43(LeafLogPort24465 *838 (LeafLogPort 24630 24466 port (LogicalPort 24631 24467 m 4 … … 24640 24476 uid 4563,0 24641 24477 ) 24642 *8 44(LeafLogPort24478 *839 (LeafLogPort 24643 24479 port (LogicalPort 24644 24480 m 4 … … 24652 24488 uid 4565,0 24653 24489 ) 24654 *84 5(LeafLogPort24490 *840 (LeafLogPort 24655 24491 port (LogicalPort 24656 24492 m 4 … … 24665 24501 uid 4569,0 24666 24502 ) 24667 *84 6(LeafLogPort24503 *841 (LeafLogPort 24668 24504 port (LogicalPort 24669 24505 m 1 … … 24679 24515 uid 4585,0 24680 24516 ) 24681 *84 7(LeafLogPort24517 *842 (LeafLogPort 24682 24518 port (LogicalPort 24683 24519 m 1 … … 24692 24528 uid 4587,0 24693 24529 ) 24694 *84 8(LeafLogPort24530 *843 (LeafLogPort 24695 24531 port (LogicalPort 24696 24532 decl (Decl … … 24703 24539 uid 4733,0 24704 24540 ) 24705 *84 9(LeafLogPort24541 *844 (LeafLogPort 24706 24542 port (LogicalPort 24707 24543 decl (Decl … … 24714 24550 uid 4735,0 24715 24551 ) 24716 *8 50(LeafLogPort24552 *845 (LeafLogPort 24717 24553 port (LogicalPort 24718 24554 decl (Decl … … 24725 24561 uid 4737,0 24726 24562 ) 24727 *8 51(LeafLogPort24563 *846 (LeafLogPort 24728 24564 port (LogicalPort 24729 24565 decl (Decl … … 24736 24572 uid 4739,0 24737 24573 ) 24738 *8 52(LeafLogPort24574 *847 (LeafLogPort 24739 24575 port (LogicalPort 24740 24576 m 4 … … 24748 24584 uid 4749,0 24749 24585 ) 24750 *8 53(LeafLogPort24586 *848 (LeafLogPort 24751 24587 port (LogicalPort 24752 24588 m 1 … … 24761 24597 uid 4974,0 24762 24598 ) 24763 *8 54(LeafLogPort24599 *849 (LeafLogPort 24764 24600 port (LogicalPort 24765 24601 m 1 … … 24774 24610 uid 4976,0 24775 24611 ) 24776 *85 5(LeafLogPort24612 *850 (LeafLogPort 24777 24613 port (LogicalPort 24778 24614 m 4 … … 24787 24623 uid 5198,0 24788 24624 ) 24789 *85 6(LeafLogPort24625 *851 (LeafLogPort 24790 24626 port (LogicalPort 24791 24627 m 4 … … 24799 24635 uid 5200,0 24800 24636 ) 24801 *85 7(LeafLogPort24637 *852 (LeafLogPort 24802 24638 port (LogicalPort 24803 24639 m 4 … … 24811 24647 uid 5202,0 24812 24648 ) 24813 *85 8(LeafLogPort24649 *853 (LeafLogPort 24814 24650 port (LogicalPort 24815 24651 m 4 … … 24824 24660 uid 5204,0 24825 24661 ) 24826 *85 9(LeafLogPort24662 *854 (LeafLogPort 24827 24663 port (LogicalPort 24828 24664 m 4 … … 24836 24672 uid 5206,0 24837 24673 ) 24838 *8 60(LeafLogPort24674 *855 (LeafLogPort 24839 24675 port (LogicalPort 24840 24676 m 4 … … 24848 24684 uid 5208,0 24849 24685 ) 24850 *8 61(LeafLogPort24686 *856 (LeafLogPort 24851 24687 port (LogicalPort 24852 24688 m 4 … … 24860 24696 uid 5210,0 24861 24697 ) 24862 *8 62(LeafLogPort24698 *857 (LeafLogPort 24863 24699 port (LogicalPort 24864 24700 m 4 … … 24872 24708 uid 5212,0 24873 24709 ) 24874 *8 63(LeafLogPort24710 *858 (LeafLogPort 24875 24711 port (LogicalPort 24876 24712 m 4 … … 24884 24720 uid 5214,0 24885 24721 ) 24886 *8 64(LeafLogPort24722 *859 (LeafLogPort 24887 24723 port (LogicalPort 24888 24724 m 1 … … 24899 24735 uid 5226,0 24900 24736 ) 24901 *86 5(LeafLogPort24737 *860 (LeafLogPort 24902 24738 port (LogicalPort 24903 24739 m 4 … … 24911 24747 uid 5502,0 24912 24748 ) 24913 *86 6(LeafLogPort24749 *861 (LeafLogPort 24914 24750 port (LogicalPort 24915 24751 m 4 … … 24923 24759 uid 5504,0 24924 24760 ) 24925 *86 7(LeafLogPort24761 *862 (LeafLogPort 24926 24762 port (LogicalPort 24927 24763 m 4 … … 24935 24771 uid 5600,0 24936 24772 ) 24937 *86 8(LeafLogPort24773 *863 (LeafLogPort 24938 24774 port (LogicalPort 24939 24775 lang 10 … … 24949 24785 uid 5642,0 24950 24786 ) 24951 *86 9(LeafLogPort24787 *864 (LeafLogPort 24952 24788 port (LogicalPort 24953 24789 m 4 … … 24961 24797 uid 5644,0 24962 24798 ) 24963 *8 70(LeafLogPort24799 *865 (LeafLogPort 24964 24800 port (LogicalPort 24965 24801 m 4 … … 24974 24810 uid 5751,0 24975 24811 ) 24976 *8 71(LeafLogPort24812 *866 (LeafLogPort 24977 24813 port (LogicalPort 24978 24814 m 1 … … 24986 24822 uid 5867,0 24987 24823 ) 24988 *8 72(LeafLogPort24824 *867 (LeafLogPort 24989 24825 port (LogicalPort 24990 24826 m 2 … … 25000 24836 uid 5869,0 25001 24837 ) 25002 *8 73(LeafLogPort24838 *868 (LeafLogPort 25003 24839 port (LogicalPort 25004 24840 m 1 … … 25012 24848 uid 5871,0 25013 24849 ) 25014 *8 74(LeafLogPort24850 *869 (LeafLogPort 25015 24851 port (LogicalPort 25016 24852 m 1 … … 25025 24861 uid 5873,0 25026 24862 ) 25027 *87 5(LeafLogPort24863 *870 (LeafLogPort 25028 24864 port (LogicalPort 25029 24865 m 4 … … 25038 24874 uid 5966,0 25039 24875 ) 25040 *87 6(LeafLogPort24876 *871 (LeafLogPort 25041 24877 port (LogicalPort 25042 24878 m 4 … … 25050 24886 uid 5968,0 25051 24887 ) 25052 *87 7(LeafLogPort24888 *872 (LeafLogPort 25053 24889 port (LogicalPort 25054 24890 m 4 … … 25063 24899 uid 6022,0 25064 24900 ) 25065 *87 8(LeafLogPort24901 *873 (LeafLogPort 25066 24902 port (LogicalPort 25067 24903 m 4 … … 25076 24912 uid 6024,0 25077 24913 ) 25078 *87 9(LeafLogPort24914 *874 (LeafLogPort 25079 24915 port (LogicalPort 25080 24916 m 4 … … 25088 24924 uid 6026,0 25089 24925 ) 25090 *8 80(LeafLogPort24926 *875 (LeafLogPort 25091 24927 port (LogicalPort 25092 24928 m 1 … … 25101 24937 uid 6172,0 25102 24938 ) 25103 *8 81(LeafLogPort24939 *876 (LeafLogPort 25104 24940 port (LogicalPort 25105 24941 m 1 … … 25116 24952 uid 6374,0 25117 24953 ) 25118 *8 82(LeafLogPort24954 *877 (LeafLogPort 25119 24955 port (LogicalPort 25120 24956 m 4 … … 25129 24965 uid 6464,0 25130 24966 ) 25131 *8 83(LeafLogPort24967 *878 (LeafLogPort 25132 24968 port (LogicalPort 25133 24969 m 4 … … 25142 24978 uid 6554,0 25143 24979 ) 25144 *8 84(LeafLogPort24980 *879 (LeafLogPort 25145 24981 port (LogicalPort 25146 24982 lang 2 … … 25155 24991 uid 8420,0 25156 24992 ) 25157 *88 5(LeafLogPort24993 *880 (LeafLogPort 25158 24994 port (LogicalPort 25159 24995 m 4 … … 25167 25003 uid 8758,0 25168 25004 ) 25169 *88 6(LeafLogPort25005 *881 (LeafLogPort 25170 25006 port (LogicalPort 25171 25007 m 4 … … 25179 25015 uid 8760,0 25180 25016 ) 25181 *88 7(LeafLogPort25017 *882 (LeafLogPort 25182 25018 port (LogicalPort 25183 25019 m 1 … … 25192 25028 uid 9018,0 25193 25029 ) 25194 *88 8(LeafLogPort25030 *883 (LeafLogPort 25195 25031 port (LogicalPort 25196 25032 m 4 … … 25207 25043 uid 9247,0 25208 25044 ) 25209 *88 9(LeafLogPort25045 *884 (LeafLogPort 25210 25046 port (LogicalPort 25211 25047 m 4 … … 25223 25059 uid 9249,0 25224 25060 ) 25225 *8 90(LeafLogPort25061 *885 (LeafLogPort 25226 25062 port (LogicalPort 25227 25063 m 4 … … 25238 25074 uid 10024,0 25239 25075 ) 25240 *8 91(LeafLogPort25076 *886 (LeafLogPort 25241 25077 port (LogicalPort 25242 25078 m 4 … … 25251 25087 uid 10026,0 25252 25088 ) 25253 *8 92(LeafLogPort25089 *887 (LeafLogPort 25254 25090 port (LogicalPort 25255 25091 m 4 … … 25264 25100 uid 10028,0 25265 25101 ) 25266 *8 93(LeafLogPort25102 *888 (LeafLogPort 25267 25103 port (LogicalPort 25268 25104 m 4 … … 25280 25116 uid 10208,0 25281 25117 ) 25282 *8 94(LeafLogPort25118 *889 (LeafLogPort 25283 25119 port (LogicalPort 25284 25120 m 4 … … 25296 25132 uid 10210,0 25297 25133 ) 25298 *89 5(LeafLogPort25134 *890 (LeafLogPort 25299 25135 port (LogicalPort 25300 25136 m 4 … … 25308 25144 uid 10294,0 25309 25145 ) 25310 *89 6(LeafLogPort25146 *891 (LeafLogPort 25311 25147 port (LogicalPort 25312 25148 m 4 … … 25320 25156 uid 10334,0 25321 25157 ) 25322 *89 7(LeafLogPort25158 *892 (LeafLogPort 25323 25159 port (LogicalPort 25324 25160 m 4 … … 25333 25169 uid 10336,0 25334 25170 ) 25335 *89 8(LeafLogPort25171 *893 (LeafLogPort 25336 25172 port (LogicalPort 25337 25173 m 4 … … 25346 25182 uid 10338,0 25347 25183 ) 25348 *89 9(LeafLogPort25184 *894 (LeafLogPort 25349 25185 port (LogicalPort 25350 25186 m 4 … … 25360 25196 uid 10340,0 25361 25197 ) 25362 * 900(LeafLogPort25198 *895 (LeafLogPort 25363 25199 port (LogicalPort 25364 25200 m 1 … … 25373 25209 uid 10342,0 25374 25210 ) 25375 *901 (LeafLogPort 25376 port (LogicalPort 25377 m 4 25378 decl (Decl 25379 n "trigger_out" 25380 t "std_logic" 25381 preAdd 0 25382 posAdd 0 25383 o 120 25384 suid 240,0 25385 ) 25386 ) 25387 uid 10473,0 25388 ) 25389 *902 (LeafLogPort 25211 *896 (LeafLogPort 25390 25212 port (LogicalPort 25391 25213 lang 2 … … 25404 25226 uid 10475,0 25405 25227 ) 25228 *897 (LeafLogPort 25229 port (LogicalPort 25230 m 4 25231 decl (Decl 25232 n "socks_connected" 25233 t "std_logic" 25234 o 111 25235 suid 243,0 25236 ) 25237 ) 25238 uid 10763,0 25239 ) 25240 *898 (LeafLogPort 25241 port (LogicalPort 25242 m 4 25243 decl (Decl 25244 n "socks_waiting" 25245 t "std_logic" 25246 o 112 25247 suid 244,0 25248 ) 25249 ) 25250 uid 10765,0 25251 ) 25252 *899 (LeafLogPort 25253 port (LogicalPort 25254 m 1 25255 decl (Decl 25256 n "green" 25257 t "std_logic" 25258 o 34 25259 suid 248,0 25260 ) 25261 ) 25262 uid 10767,0 25263 ) 25264 *900 (LeafLogPort 25265 port (LogicalPort 25266 m 1 25267 decl (Decl 25268 n "amber" 25269 t "std_logic" 25270 o 29 25271 suid 249,0 25272 ) 25273 ) 25274 uid 10769,0 25275 ) 25276 *901 (LeafLogPort 25277 port (LogicalPort 25278 m 1 25279 decl (Decl 25280 n "red" 25281 t "std_logic" 25282 o 39 25283 suid 250,0 25284 ) 25285 ) 25286 uid 10771,0 25287 ) 25288 *902 (LeafLogPort 25289 port (LogicalPort 25290 m 4 25291 decl (Decl 25292 n "drs_readout_started" 25293 t "std_logic" 25294 o 87 25295 suid 252,0 25296 ) 25297 ) 25298 uid 11411,0 25299 ) 25406 25300 *903 (LeafLogPort 25407 25301 port (LogicalPort 25408 25302 m 4 25409 25303 decl (Decl 25410 n "socks_connected"25411 t "std_logic"25412 o 11125413 suid 243,025414 )25415 )25416 uid 10763,025417 )25418 *904 (LeafLogPort25419 port (LogicalPort25420 m 425421 decl (Decl25422 n "socks_waiting"25423 t "std_logic"25424 o 11225425 suid 244,025426 )25427 )25428 uid 10765,025429 )25430 *905 (LeafLogPort25431 port (LogicalPort25432 m 125433 decl (Decl25434 n "green"25435 t "std_logic"25436 o 3425437 suid 248,025438 )25439 )25440 uid 10767,025441 )25442 *906 (LeafLogPort25443 port (LogicalPort25444 m 125445 decl (Decl25446 n "amber"25447 t "std_logic"25448 o 2925449 suid 249,025450 )25451 )25452 uid 10769,025453 )25454 *907 (LeafLogPort25455 port (LogicalPort25456 m 125457 decl (Decl25458 n "red"25459 t "std_logic"25460 o 3925461 suid 250,025462 )25463 )25464 uid 10771,025465 )25466 *908 (LeafLogPort25467 port (LogicalPort25468 m 425469 decl (Decl25470 n "drs_readout_started"25471 t "std_logic"25472 o 8725473 suid 252,025474 )25475 )25476 uid 11411,025477 )25478 *909 (LeafLogPort25479 port (LogicalPort25480 m 425481 decl (Decl25482 25304 n "trigger_enable" 25483 25305 t "std_logic" … … 25488 25310 uid 11966,0 25489 25311 ) 25490 *9 10(LeafLogPort25312 *904 (LeafLogPort 25491 25313 port (LogicalPort 25492 25314 m 4 … … 25502 25324 uid 12310,0 25503 25325 ) 25504 *9 11(LeafLogPort25326 *905 (LeafLogPort 25505 25327 port (LogicalPort 25506 25328 m 4 … … 25516 25338 uid 12659,0 25517 25339 ) 25518 *9 12(LeafLogPort25340 *906 (LeafLogPort 25519 25341 port (LogicalPort 25520 25342 m 4 … … 25533 25355 uid 12661,0 25534 25356 ) 25535 *9 13(LeafLogPort25357 *907 (LeafLogPort 25536 25358 port (LogicalPort 25537 25359 m 4 … … 25545 25367 uid 12663,0 25546 25368 ) 25547 *9 14(LeafLogPort25369 *908 (LeafLogPort 25548 25370 port (LogicalPort 25549 25371 m 1 … … 25557 25379 uid 12719,0 25558 25380 ) 25559 *9 15(LeafLogPort25381 *909 (LeafLogPort 25560 25382 port (LogicalPort 25561 25383 m 4 … … 25570 25392 uid 13275,0 25571 25393 ) 25572 *91 6(LeafLogPort25394 *910 (LeafLogPort 25573 25395 port (LogicalPort 25574 25396 m 4 … … 25586 25408 uid 13277,0 25587 25409 ) 25588 *91 7(LeafLogPort25410 *911 (LeafLogPort 25589 25411 port (LogicalPort 25590 25412 m 4 … … 25598 25420 uid 13279,0 25599 25421 ) 25600 *91 8(LeafLogPort25422 *912 (LeafLogPort 25601 25423 port (LogicalPort 25602 25424 m 4 … … 25610 25432 uid 13281,0 25611 25433 ) 25612 *91 9(LeafLogPort25434 *913 (LeafLogPort 25613 25435 port (LogicalPort 25614 25436 decl (Decl … … 25623 25445 scheme 0 25624 25446 ) 25625 *9 20(LeafLogPort25447 *914 (LeafLogPort 25626 25448 port (LogicalPort 25627 25449 decl (Decl … … 25636 25458 scheme 0 25637 25459 ) 25638 *9 21(LeafLogPort25460 *915 (LeafLogPort 25639 25461 port (LogicalPort 25640 25462 decl (Decl … … 25650 25472 scheme 0 25651 25473 ) 25652 *9 22(LeafLogPort25474 *916 (LeafLogPort 25653 25475 port (LogicalPort 25654 25476 m 1 … … 25665 25487 uid 14507,0 25666 25488 ) 25667 *9 23(LeafLogPort25489 *917 (LeafLogPort 25668 25490 port (LogicalPort 25669 25491 m 1 … … 25680 25502 uid 14509,0 25681 25503 ) 25682 *9 24(LeafLogPort25504 *918 (LeafLogPort 25683 25505 port (LogicalPort 25684 25506 m 1 … … 25694 25516 uid 14634,0 25695 25517 ) 25696 *9 25(LeafLogPort25518 *919 (LeafLogPort 25697 25519 port (LogicalPort 25698 25520 m 4 … … 25709 25531 uid 15144,0 25710 25532 ) 25711 *92 6(LeafLogPort25533 *920 (LeafLogPort 25712 25534 port (LogicalPort 25713 25535 m 4 … … 25724 25546 uid 15146,0 25725 25547 ) 25726 *92 7(LeafLogPort25548 *921 (LeafLogPort 25727 25549 port (LogicalPort 25728 25550 m 4 … … 25746 25568 uid 67,0 25747 25569 optionalChildren [ 25748 *92 8(Sheet25570 *922 (Sheet 25749 25571 sheetRow (SheetRow 25750 25572 headerVa (MVa … … 25763 25585 font "Tahoma,10,0" 25764 25586 ) 25765 emptyMRCItem *92 9(MRCItem25766 litem &7 9225767 pos 12 325587 emptyMRCItem *923 (MRCItem 25588 litem &787 25589 pos 122 25768 25590 dimension 20 25769 25591 ) 25770 25592 uid 69,0 25771 25593 optionalChildren [ 25772 *9 30(MRCItem25773 litem &7 9325594 *924 (MRCItem 25595 litem &788 25774 25596 pos 0 25775 25597 dimension 20 25776 25598 uid 70,0 25777 25599 ) 25778 *9 31(MRCItem25779 litem &7 9425600 *925 (MRCItem 25601 litem &789 25780 25602 pos 1 25781 25603 dimension 23 25782 25604 uid 71,0 25783 25605 ) 25784 *9 32(MRCItem25785 litem &79 525606 *926 (MRCItem 25607 litem &790 25786 25608 pos 2 25787 25609 hidden 1 … … 25789 25611 uid 72,0 25790 25612 ) 25791 *9 33(MRCItem25792 litem &80 525613 *927 (MRCItem 25614 litem &800 25793 25615 pos 37 25794 25616 dimension 20 25795 25617 uid 517,0 25796 25618 ) 25797 *9 34(MRCItem25798 litem &80 625619 *928 (MRCItem 25620 litem &801 25799 25621 pos 38 25800 25622 dimension 20 25801 25623 uid 519,0 25802 25624 ) 25803 *9 35(MRCItem25804 litem &80 725625 *929 (MRCItem 25626 litem &802 25805 25627 pos 39 25806 25628 dimension 20 25807 25629 uid 521,0 25808 25630 ) 25809 *93 6(MRCItem25810 litem &80 825631 *930 (MRCItem 25632 litem &803 25811 25633 pos 40 25812 25634 dimension 20 25813 25635 uid 531,0 25814 25636 ) 25815 *93 7(MRCItem25816 litem &80 925637 *931 (MRCItem 25638 litem &804 25817 25639 pos 41 25818 25640 dimension 20 25819 25641 uid 533,0 25820 25642 ) 25821 *93 8(MRCItem25822 litem &8 1025643 *932 (MRCItem 25644 litem &805 25823 25645 pos 0 25824 25646 dimension 20 25825 25647 uid 535,0 25826 25648 ) 25827 *93 9(MRCItem25828 litem &8 1125649 *933 (MRCItem 25650 litem &806 25829 25651 pos 1 25830 25652 dimension 20 25831 25653 uid 537,0 25832 25654 ) 25833 *9 40(MRCItem25834 litem &8 1225655 *934 (MRCItem 25656 litem &807 25835 25657 pos 2 25836 25658 dimension 20 25837 25659 uid 539,0 25838 25660 ) 25839 *9 41(MRCItem25840 litem &8 1325661 *935 (MRCItem 25662 litem &808 25841 25663 pos 3 25842 25664 dimension 20 25843 25665 uid 541,0 25844 25666 ) 25845 *9 42(MRCItem25846 litem &8 1425667 *936 (MRCItem 25668 litem &809 25847 25669 pos 4 25848 25670 dimension 20 25849 25671 uid 543,0 25850 25672 ) 25851 *9 43(MRCItem25852 litem &81 525673 *937 (MRCItem 25674 litem &810 25853 25675 pos 5 25854 25676 dimension 20 25855 25677 uid 547,0 25856 25678 ) 25857 *9 44(MRCItem25858 litem &81 625679 *938 (MRCItem 25680 litem &811 25859 25681 pos 6 25860 25682 dimension 20 25861 25683 uid 549,0 25862 25684 ) 25863 *9 45(MRCItem25864 litem &81 725685 *939 (MRCItem 25686 litem &812 25865 25687 pos 8 25866 25688 dimension 20 25867 25689 uid 1456,0 25868 25690 ) 25869 *94 6(MRCItem25870 litem &81 825691 *940 (MRCItem 25692 litem &813 25871 25693 pos 7 25872 25694 dimension 20 25873 25695 uid 1458,0 25874 25696 ) 25875 *94 7(MRCItem25876 litem &81 925697 *941 (MRCItem 25698 litem &814 25877 25699 pos 9 25878 25700 dimension 20 25879 25701 uid 1695,0 25880 25702 ) 25881 *94 8(MRCItem25882 litem &8 2025703 *942 (MRCItem 25704 litem &815 25883 25705 pos 42 25884 25706 dimension 20 25885 25707 uid 1994,0 25886 25708 ) 25887 *94 9(MRCItem25888 litem &8 2125709 *943 (MRCItem 25710 litem &816 25889 25711 pos 43 25890 25712 dimension 20 25891 25713 uid 2306,0 25892 25714 ) 25893 *9 50(MRCItem25894 litem &8 2225715 *944 (MRCItem 25716 litem &817 25895 25717 pos 44 25896 25718 dimension 20 25897 25719 uid 2511,0 25898 25720 ) 25899 *9 51(MRCItem25900 litem &8 2325721 *945 (MRCItem 25722 litem &818 25901 25723 pos 45 25902 25724 dimension 20 25903 25725 uid 2513,0 25904 25726 ) 25905 *9 52(MRCItem25906 litem &8 2425727 *946 (MRCItem 25728 litem &819 25907 25729 pos 46 25908 25730 dimension 20 25909 25731 uid 2515,0 25910 25732 ) 25911 *9 53(MRCItem25912 litem &82 525733 *947 (MRCItem 25734 litem &820 25913 25735 pos 47 25914 25736 dimension 20 25915 25737 uid 2517,0 25916 25738 ) 25917 *9 54(MRCItem25918 litem &82 625739 *948 (MRCItem 25740 litem &821 25919 25741 pos 48 25920 25742 dimension 20 25921 25743 uid 2519,0 25922 25744 ) 25923 *9 55(MRCItem25924 litem &82 725745 *949 (MRCItem 25746 litem &822 25925 25747 pos 49 25926 25748 dimension 20 25927 25749 uid 2521,0 25928 25750 ) 25929 *95 6(MRCItem25930 litem &82 825751 *950 (MRCItem 25752 litem &823 25931 25753 pos 50 25932 25754 dimension 20 25933 25755 uid 2523,0 25934 25756 ) 25935 *95 7(MRCItem25936 litem &82 925757 *951 (MRCItem 25758 litem &824 25937 25759 pos 51 25938 25760 dimension 20 25939 25761 uid 2605,0 25940 25762 ) 25941 *95 8(MRCItem25942 litem &8 3025763 *952 (MRCItem 25764 litem &825 25943 25765 pos 52 25944 25766 dimension 20 25945 25767 uid 2607,0 25946 25768 ) 25947 *95 9(MRCItem25948 litem &8 3125769 *953 (MRCItem 25770 litem &826 25949 25771 pos 53 25950 25772 dimension 20 25951 25773 uid 2609,0 25952 25774 ) 25953 *9 60(MRCItem25954 litem &8 3225775 *954 (MRCItem 25776 litem &827 25955 25777 pos 54 25956 25778 dimension 20 25957 25779 uid 2611,0 25958 25780 ) 25959 *9 61(MRCItem25960 litem &8 3325781 *955 (MRCItem 25782 litem &828 25961 25783 pos 55 25962 25784 dimension 20 25963 25785 uid 2613,0 25964 25786 ) 25965 *9 62(MRCItem25966 litem &8 3425787 *956 (MRCItem 25788 litem &829 25967 25789 pos 56 25968 25790 dimension 20 25969 25791 uid 2647,0 25970 25792 ) 25971 *9 63(MRCItem25972 litem &83 525793 *957 (MRCItem 25794 litem &830 25973 25795 pos 10 25974 25796 dimension 20 25975 25797 uid 2813,0 25976 25798 ) 25977 *9 64(MRCItem25978 litem &83 625799 *958 (MRCItem 25800 litem &831 25979 25801 pos 57 25980 25802 dimension 20 25981 25803 uid 2963,0 25982 25804 ) 25983 *9 65(MRCItem25984 litem &83 725805 *959 (MRCItem 25806 litem &832 25985 25807 pos 11 25986 25808 dimension 20 25987 25809 uid 3903,0 25988 25810 ) 25989 *96 6(MRCItem25990 litem &83 825811 *960 (MRCItem 25812 litem &833 25991 25813 pos 12 25992 25814 dimension 20 25993 25815 uid 4071,0 25994 25816 ) 25995 *96 7(MRCItem25996 litem &83 925817 *961 (MRCItem 25818 litem &834 25997 25819 pos 58 25998 25820 dimension 20 25999 25821 uid 4213,0 26000 25822 ) 26001 *96 8(MRCItem26002 litem &8 4025823 *962 (MRCItem 25824 litem &835 26003 25825 pos 13 26004 25826 dimension 20 26005 25827 uid 4235,0 26006 25828 ) 26007 *96 9(MRCItem26008 litem &8 4125829 *963 (MRCItem 25830 litem &836 26009 25831 pos 14 26010 25832 dimension 20 26011 25833 uid 4263,0 26012 25834 ) 26013 *9 70(MRCItem26014 litem &8 4225835 *964 (MRCItem 25836 litem &837 26015 25837 pos 15 26016 25838 dimension 20 26017 25839 uid 4277,0 26018 25840 ) 26019 *9 71(MRCItem26020 litem &8 4325841 *965 (MRCItem 25842 litem &838 26021 25843 pos 59 26022 25844 dimension 20 26023 25845 uid 4564,0 26024 25846 ) 26025 *9 72(MRCItem26026 litem &8 4425847 *966 (MRCItem 25848 litem &839 26027 25849 pos 60 26028 25850 dimension 20 26029 25851 uid 4566,0 26030 25852 ) 26031 *9 73(MRCItem26032 litem &84 525853 *967 (MRCItem 25854 litem &840 26033 25855 pos 61 26034 25856 dimension 20 26035 25857 uid 4570,0 26036 25858 ) 26037 *9 74(MRCItem26038 litem &84 625859 *968 (MRCItem 25860 litem &841 26039 25861 pos 16 26040 25862 dimension 20 26041 25863 uid 4586,0 26042 25864 ) 26043 *9 75(MRCItem26044 litem &84 725865 *969 (MRCItem 25866 litem &842 26045 25867 pos 17 26046 25868 dimension 20 26047 25869 uid 4588,0 26048 25870 ) 26049 *97 6(MRCItem26050 litem &84 825871 *970 (MRCItem 25872 litem &843 26051 25873 pos 18 26052 25874 dimension 20 26053 25875 uid 4734,0 26054 25876 ) 26055 *97 7(MRCItem26056 litem &84 925877 *971 (MRCItem 25878 litem &844 26057 25879 pos 19 26058 25880 dimension 20 26059 25881 uid 4736,0 26060 25882 ) 26061 *97 8(MRCItem26062 litem &8 5025883 *972 (MRCItem 25884 litem &845 26063 25885 pos 20 26064 25886 dimension 20 26065 25887 uid 4738,0 26066 25888 ) 26067 *97 9(MRCItem26068 litem &8 5125889 *973 (MRCItem 25890 litem &846 26069 25891 pos 21 26070 25892 dimension 20 26071 25893 uid 4740,0 26072 25894 ) 26073 *9 80(MRCItem26074 litem &8 5225895 *974 (MRCItem 25896 litem &847 26075 25897 pos 62 26076 25898 dimension 20 26077 25899 uid 4750,0 26078 25900 ) 26079 *9 81(MRCItem26080 litem &8 5325901 *975 (MRCItem 25902 litem &848 26081 25903 pos 22 26082 25904 dimension 20 26083 25905 uid 4975,0 26084 25906 ) 26085 *9 82(MRCItem26086 litem &8 5425907 *976 (MRCItem 25908 litem &849 26087 25909 pos 23 26088 25910 dimension 20 26089 25911 uid 4977,0 26090 25912 ) 26091 *9 83(MRCItem26092 litem &85 525913 *977 (MRCItem 25914 litem &850 26093 25915 pos 63 26094 25916 dimension 20 26095 25917 uid 5199,0 26096 25918 ) 26097 *9 84(MRCItem26098 litem &85 625919 *978 (MRCItem 25920 litem &851 26099 25921 pos 64 26100 25922 dimension 20 26101 25923 uid 5201,0 26102 25924 ) 26103 *9 85(MRCItem26104 litem &85 725925 *979 (MRCItem 25926 litem &852 26105 25927 pos 65 26106 25928 dimension 20 26107 25929 uid 5203,0 26108 25930 ) 26109 *98 6(MRCItem26110 litem &85 825931 *980 (MRCItem 25932 litem &853 26111 25933 pos 66 26112 25934 dimension 20 26113 25935 uid 5205,0 26114 25936 ) 26115 *98 7(MRCItem26116 litem &85 925937 *981 (MRCItem 25938 litem &854 26117 25939 pos 67 26118 25940 dimension 20 26119 25941 uid 5207,0 26120 25942 ) 26121 *98 8(MRCItem26122 litem &8 6025943 *982 (MRCItem 25944 litem &855 26123 25945 pos 68 26124 25946 dimension 20 26125 25947 uid 5209,0 26126 25948 ) 26127 *98 9(MRCItem26128 litem &8 6125949 *983 (MRCItem 25950 litem &856 26129 25951 pos 69 26130 25952 dimension 20 26131 25953 uid 5211,0 26132 25954 ) 26133 *9 90(MRCItem26134 litem &8 6225955 *984 (MRCItem 25956 litem &857 26135 25957 pos 70 26136 25958 dimension 20 26137 25959 uid 5213,0 26138 25960 ) 26139 *9 91(MRCItem26140 litem &8 6325961 *985 (MRCItem 25962 litem &858 26141 25963 pos 71 26142 25964 dimension 20 26143 25965 uid 5215,0 26144 25966 ) 26145 *9 92(MRCItem26146 litem &8 6425967 *986 (MRCItem 25968 litem &859 26147 25969 pos 24 26148 25970 dimension 20 26149 25971 uid 5227,0 26150 25972 ) 26151 *9 93(MRCItem26152 litem &86 525973 *987 (MRCItem 25974 litem &860 26153 25975 pos 72 26154 25976 dimension 20 26155 25977 uid 5503,0 26156 25978 ) 26157 *9 94(MRCItem26158 litem &86 625979 *988 (MRCItem 25980 litem &861 26159 25981 pos 73 26160 25982 dimension 20 26161 25983 uid 5505,0 26162 25984 ) 26163 *9 95(MRCItem26164 litem &86 725985 *989 (MRCItem 25986 litem &862 26165 25987 pos 74 26166 25988 dimension 20 26167 25989 uid 5601,0 26168 25990 ) 26169 *99 6(MRCItem26170 litem &86 825991 *990 (MRCItem 25992 litem &863 26171 25993 pos 75 26172 25994 dimension 20 26173 25995 uid 5643,0 26174 25996 ) 26175 *99 7(MRCItem26176 litem &86 925997 *991 (MRCItem 25998 litem &864 26177 25999 pos 76 26178 26000 dimension 20 26179 26001 uid 5645,0 26180 26002 ) 26181 *99 8(MRCItem26182 litem &8 7026003 *992 (MRCItem 26004 litem &865 26183 26005 pos 77 26184 26006 dimension 20 26185 26007 uid 5752,0 26186 26008 ) 26187 *99 9(MRCItem26188 litem &8 7126009 *993 (MRCItem 26010 litem &866 26189 26011 pos 25 26190 26012 dimension 20 26191 26013 uid 5868,0 26192 26014 ) 26193 * 1000(MRCItem26194 litem &8 7226015 *994 (MRCItem 26016 litem &867 26195 26017 pos 26 26196 26018 dimension 20 26197 26019 uid 5870,0 26198 26020 ) 26199 * 1001(MRCItem26200 litem &8 7326021 *995 (MRCItem 26022 litem &868 26201 26023 pos 27 26202 26024 dimension 20 26203 26025 uid 5872,0 26204 26026 ) 26205 * 1002(MRCItem26206 litem &8 7426027 *996 (MRCItem 26028 litem &869 26207 26029 pos 28 26208 26030 dimension 20 26209 26031 uid 5874,0 26210 26032 ) 26211 * 1003(MRCItem26212 litem &87 526033 *997 (MRCItem 26034 litem &870 26213 26035 pos 78 26214 26036 dimension 20 26215 26037 uid 5967,0 26216 26038 ) 26217 * 1004(MRCItem26218 litem &87 626039 *998 (MRCItem 26040 litem &871 26219 26041 pos 79 26220 26042 dimension 20 26221 26043 uid 5969,0 26222 26044 ) 26223 * 1005(MRCItem26224 litem &87 726045 *999 (MRCItem 26046 litem &872 26225 26047 pos 80 26226 26048 dimension 20 26227 26049 uid 6023,0 26228 26050 ) 26229 *100 6(MRCItem26230 litem &87 826051 *1000 (MRCItem 26052 litem &873 26231 26053 pos 81 26232 26054 dimension 20 26233 26055 uid 6025,0 26234 26056 ) 26235 *100 7(MRCItem26236 litem &87 926057 *1001 (MRCItem 26058 litem &874 26237 26059 pos 82 26238 26060 dimension 20 26239 26061 uid 6027,0 26240 26062 ) 26241 *100 8(MRCItem26242 litem &8 8026063 *1002 (MRCItem 26064 litem &875 26243 26065 pos 29 26244 26066 dimension 20 26245 26067 uid 6173,0 26246 26068 ) 26247 *100 9(MRCItem26248 litem &8 8126069 *1003 (MRCItem 26070 litem &876 26249 26071 pos 30 26250 26072 dimension 20 26251 26073 uid 6375,0 26252 26074 ) 26253 *10 10(MRCItem26254 litem &8 8226075 *1004 (MRCItem 26076 litem &877 26255 26077 pos 83 26256 26078 dimension 20 26257 26079 uid 6465,0 26258 26080 ) 26259 *10 11(MRCItem26260 litem &8 8326081 *1005 (MRCItem 26082 litem &878 26261 26083 pos 84 26262 26084 dimension 20 26263 26085 uid 6555,0 26264 26086 ) 26265 *10 12(MRCItem26266 litem &8 8426087 *1006 (MRCItem 26088 litem &879 26267 26089 pos 85 26268 26090 dimension 20 26269 26091 uid 8421,0 26270 26092 ) 26271 *10 13(MRCItem26272 litem &88 526093 *1007 (MRCItem 26094 litem &880 26273 26095 pos 86 26274 26096 dimension 20 26275 26097 uid 8759,0 26276 26098 ) 26277 *10 14(MRCItem26278 litem &88 626099 *1008 (MRCItem 26100 litem &881 26279 26101 pos 87 26280 26102 dimension 20 26281 26103 uid 8761,0 26282 26104 ) 26283 *10 15(MRCItem26284 litem &88 726105 *1009 (MRCItem 26106 litem &882 26285 26107 pos 31 26286 26108 dimension 20 26287 26109 uid 9019,0 26288 26110 ) 26289 *101 6(MRCItem26290 litem &88 826111 *1010 (MRCItem 26112 litem &883 26291 26113 pos 88 26292 26114 dimension 20 26293 26115 uid 9248,0 26294 26116 ) 26295 *101 7(MRCItem26296 litem &88 926117 *1011 (MRCItem 26118 litem &884 26297 26119 pos 89 26298 26120 dimension 20 26299 26121 uid 9250,0 26300 26122 ) 26301 *101 8(MRCItem26302 litem &8 9026123 *1012 (MRCItem 26124 litem &885 26303 26125 pos 90 26304 26126 dimension 20 26305 26127 uid 10025,0 26306 26128 ) 26307 *101 9(MRCItem26308 litem &8 9126129 *1013 (MRCItem 26130 litem &886 26309 26131 pos 91 26310 26132 dimension 20 26311 26133 uid 10027,0 26312 26134 ) 26313 *10 20(MRCItem26314 litem &8 9226135 *1014 (MRCItem 26136 litem &887 26315 26137 pos 92 26316 26138 dimension 20 26317 26139 uid 10029,0 26318 26140 ) 26319 *10 21(MRCItem26320 litem &8 9326141 *1015 (MRCItem 26142 litem &888 26321 26143 pos 93 26322 26144 dimension 20 26323 26145 uid 10209,0 26324 26146 ) 26325 *10 22(MRCItem26326 litem &8 9426147 *1016 (MRCItem 26148 litem &889 26327 26149 pos 94 26328 26150 dimension 20 26329 26151 uid 10211,0 26330 26152 ) 26331 *10 23(MRCItem26332 litem &89 526153 *1017 (MRCItem 26154 litem &890 26333 26155 pos 95 26334 26156 dimension 20 26335 26157 uid 10295,0 26336 26158 ) 26337 *10 24(MRCItem26338 litem &89 626159 *1018 (MRCItem 26160 litem &891 26339 26161 pos 96 26340 26162 dimension 20 26341 26163 uid 10335,0 26342 26164 ) 26343 *10 25(MRCItem26344 litem &89 726165 *1019 (MRCItem 26166 litem &892 26345 26167 pos 97 26346 26168 dimension 20 26347 26169 uid 10337,0 26348 26170 ) 26349 *102 6(MRCItem26350 litem &89 826171 *1020 (MRCItem 26172 litem &893 26351 26173 pos 98 26352 26174 dimension 20 26353 26175 uid 10339,0 26354 26176 ) 26355 *102 7(MRCItem26356 litem &89 926177 *1021 (MRCItem 26178 litem &894 26357 26179 pos 99 26358 26180 dimension 20 26359 26181 uid 10341,0 26360 26182 ) 26361 *102 8(MRCItem26362 litem & 90026183 *1022 (MRCItem 26184 litem &895 26363 26185 pos 32 26364 26186 dimension 20 26365 26187 uid 10343,0 26366 26188 ) 26367 *102 9(MRCItem26368 litem & 90126189 *1023 (MRCItem 26190 litem &896 26369 26191 pos 100 26370 26192 dimension 20 26371 uid 1047 4,026372 ) 26373 *10 30(MRCItem26374 litem & 90226193 uid 10476,0 26194 ) 26195 *1024 (MRCItem 26196 litem &897 26375 26197 pos 101 26376 26198 dimension 20 26377 uid 10 476,026378 ) 26379 *10 31(MRCItem26380 litem & 90326199 uid 10764,0 26200 ) 26201 *1025 (MRCItem 26202 litem &898 26381 26203 pos 102 26382 26204 dimension 20 26383 uid 10764,026384 )26385 *1032 (MRCItem26386 litem &90426387 pos 10326388 dimension 2026389 26205 uid 10766,0 26390 26206 ) 26391 *10 33(MRCItem26392 litem & 90526207 *1026 (MRCItem 26208 litem &899 26393 26209 pos 33 26394 26210 dimension 20 26395 26211 uid 10768,0 26396 26212 ) 26397 *10 34(MRCItem26398 litem &90 626213 *1027 (MRCItem 26214 litem &900 26399 26215 pos 34 26400 26216 dimension 20 26401 26217 uid 10770,0 26402 26218 ) 26403 *10 35(MRCItem26404 litem &90 726219 *1028 (MRCItem 26220 litem &901 26405 26221 pos 35 26406 26222 dimension 20 26407 26223 uid 10772,0 26408 26224 ) 26409 *1036 (MRCItem 26410 litem &908 26225 *1029 (MRCItem 26226 litem &902 26227 pos 103 26228 dimension 20 26229 uid 11412,0 26230 ) 26231 *1030 (MRCItem 26232 litem &903 26411 26233 pos 104 26412 26234 dimension 20 26413 uid 11 412,026414 ) 26415 *103 7(MRCItem26416 litem &90 926235 uid 11967,0 26236 ) 26237 *1031 (MRCItem 26238 litem &904 26417 26239 pos 105 26418 26240 dimension 20 26419 uid 1 1967,026420 ) 26421 *103 8(MRCItem26422 litem &9 1026241 uid 12311,0 26242 ) 26243 *1032 (MRCItem 26244 litem &905 26423 26245 pos 106 26424 26246 dimension 20 26425 uid 12 311,026426 ) 26427 *103 9(MRCItem26428 litem &9 1126247 uid 12660,0 26248 ) 26249 *1033 (MRCItem 26250 litem &906 26429 26251 pos 107 26430 26252 dimension 20 26431 uid 1266 0,026432 ) 26433 *10 40(MRCItem26434 litem &9 1226253 uid 12662,0 26254 ) 26255 *1034 (MRCItem 26256 litem &907 26435 26257 pos 108 26436 26258 dimension 20 26437 uid 12662,026438 )26439 *1041 (MRCItem26440 litem &91326441 pos 10926442 dimension 2026443 26259 uid 12664,0 26444 26260 ) 26445 *10 42(MRCItem26446 litem &9 1426261 *1035 (MRCItem 26262 litem &908 26447 26263 pos 36 26448 26264 dimension 20 26449 26265 uid 12720,0 26450 26266 ) 26451 *1043 (MRCItem 26452 litem &915 26267 *1036 (MRCItem 26268 litem &909 26269 pos 109 26270 dimension 20 26271 uid 13276,0 26272 ) 26273 *1037 (MRCItem 26274 litem &910 26453 26275 pos 110 26454 26276 dimension 20 26455 uid 1327 6,026456 ) 26457 *10 44(MRCItem26458 litem &91 626277 uid 13278,0 26278 ) 26279 *1038 (MRCItem 26280 litem &911 26459 26281 pos 111 26460 26282 dimension 20 26461 uid 132 78,026462 ) 26463 *10 45(MRCItem26464 litem &91 726283 uid 13280,0 26284 ) 26285 *1039 (MRCItem 26286 litem &912 26465 26287 pos 112 26466 26288 dimension 20 26467 uid 1328 0,026468 ) 26469 *104 6(MRCItem26470 litem &91 826289 uid 13282,0 26290 ) 26291 *1040 (MRCItem 26292 litem &913 26471 26293 pos 113 26472 26294 dimension 20 26473 uid 13 282,026474 ) 26475 *104 7(MRCItem26476 litem &91 926295 uid 13688,0 26296 ) 26297 *1041 (MRCItem 26298 litem &914 26477 26299 pos 114 26478 26300 dimension 20 26479 uid 1 3688,026480 ) 26481 *104 8(MRCItem26482 litem &9 2026301 uid 14041,0 26302 ) 26303 *1042 (MRCItem 26304 litem &915 26483 26305 pos 115 26484 26306 dimension 20 26485 uid 14 041,026486 ) 26487 *104 9(MRCItem26488 litem &9 2126307 uid 14164,0 26308 ) 26309 *1043 (MRCItem 26310 litem &916 26489 26311 pos 116 26490 26312 dimension 20 26491 uid 14 164,026492 ) 26493 *10 50(MRCItem26494 litem &9 2226313 uid 14508,0 26314 ) 26315 *1044 (MRCItem 26316 litem &917 26495 26317 pos 117 26496 26318 dimension 20 26497 uid 145 08,026498 ) 26499 *10 51(MRCItem26500 litem &9 2326319 uid 14510,0 26320 ) 26321 *1045 (MRCItem 26322 litem &918 26501 26323 pos 118 26502 26324 dimension 20 26503 uid 14 510,026504 ) 26505 *10 52(MRCItem26506 litem &9 2426325 uid 14635,0 26326 ) 26327 *1046 (MRCItem 26328 litem &919 26507 26329 pos 119 26508 26330 dimension 20 26509 uid 1 4635,026510 ) 26511 *10 53(MRCItem26512 litem &92 526331 uid 15145,0 26332 ) 26333 *1047 (MRCItem 26334 litem &920 26513 26335 pos 120 26514 26336 dimension 20 26515 uid 1514 5,026516 ) 26517 *10 54(MRCItem26518 litem &92 626337 uid 15147,0 26338 ) 26339 *1048 (MRCItem 26340 litem &921 26519 26341 pos 121 26520 dimension 2026521 uid 15147,026522 )26523 *1055 (MRCItem26524 litem &92726525 pos 12226526 26342 dimension 20 26527 26343 uid 15149,0 … … 26538 26354 uid 73,0 26539 26355 optionalChildren [ 26540 *10 56(MRCItem26541 litem &79 626356 *1049 (MRCItem 26357 litem &791 26542 26358 pos 0 26543 26359 dimension 20 26544 26360 uid 74,0 26545 26361 ) 26546 *105 7(MRCItem26547 litem &79 826362 *1050 (MRCItem 26363 litem &793 26548 26364 pos 1 26549 26365 dimension 50 26550 26366 uid 75,0 26551 26367 ) 26552 *105 8(MRCItem26553 litem &79 926368 *1051 (MRCItem 26369 litem &794 26554 26370 pos 2 26555 26371 dimension 100 26556 26372 uid 76,0 26557 26373 ) 26558 *105 9(MRCItem26559 litem & 80026374 *1052 (MRCItem 26375 litem &795 26560 26376 pos 3 26561 26377 dimension 50 26562 26378 uid 77,0 26563 26379 ) 26564 *10 60(MRCItem26565 litem & 80126380 *1053 (MRCItem 26381 litem &796 26566 26382 pos 4 26567 26383 dimension 100 26568 26384 uid 78,0 26569 26385 ) 26570 *10 61(MRCItem26571 litem & 80226386 *1054 (MRCItem 26387 litem &797 26572 26388 pos 5 26573 26389 dimension 100 26574 26390 uid 79,0 26575 26391 ) 26576 *10 62(MRCItem26577 litem & 80326392 *1055 (MRCItem 26393 litem &798 26578 26394 pos 6 26579 26395 dimension 50 26580 26396 uid 80,0 26581 26397 ) 26582 *10 63(MRCItem26583 litem & 80426398 *1056 (MRCItem 26399 litem &799 26584 26400 pos 7 26585 26401 dimension 290 … … 26601 26417 genericsCommonDM (CommonDM 26602 26418 ldm (LogicalDM 26603 emptyRow *10 64(LEmptyRow26419 emptyRow *1057 (LEmptyRow 26604 26420 ) 26605 26421 uid 83,0 26606 26422 optionalChildren [ 26607 *10 65(RefLabelRowHdr26608 ) 26609 *10 66(TitleRowHdr26610 ) 26611 *106 7(FilterRowHdr26612 ) 26613 *106 8(RefLabelColHdr26423 *1058 (RefLabelRowHdr 26424 ) 26425 *1059 (TitleRowHdr 26426 ) 26427 *1060 (FilterRowHdr 26428 ) 26429 *1061 (RefLabelColHdr 26614 26430 tm "RefLabelColHdrMgr" 26615 26431 ) 26616 *106 9(RowExpandColHdr26432 *1062 (RowExpandColHdr 26617 26433 tm "RowExpandColHdrMgr" 26618 26434 ) 26619 *10 70(GroupColHdr26435 *1063 (GroupColHdr 26620 26436 tm "GroupColHdrMgr" 26621 26437 ) 26622 *10 71(NameColHdr26438 *1064 (NameColHdr 26623 26439 tm "GenericNameColHdrMgr" 26624 26440 ) 26625 *10 72(TypeColHdr26441 *1065 (TypeColHdr 26626 26442 tm "GenericTypeColHdrMgr" 26627 26443 ) 26628 *10 73(InitColHdr26444 *1066 (InitColHdr 26629 26445 tm "GenericValueColHdrMgr" 26630 26446 ) 26631 *10 74(PragmaColHdr26447 *1067 (PragmaColHdr 26632 26448 tm "GenericPragmaColHdrMgr" 26633 26449 ) 26634 *10 75(EolColHdr26450 *1068 (EolColHdr 26635 26451 tm "GenericEolColHdrMgr" 26636 26452 ) 26637 *10 76(LogGeneric26453 *1069 (LogGeneric 26638 26454 generic (GiElement 26639 26455 name "RAMADDRWIDTH64b" … … 26650 26466 uid 95,0 26651 26467 optionalChildren [ 26652 *107 7(Sheet26468 *1070 (Sheet 26653 26469 sheetRow (SheetRow 26654 26470 headerVa (MVa … … 26667 26483 font "Tahoma,10,0" 26668 26484 ) 26669 emptyMRCItem *107 8(MRCItem26670 litem &10 6426485 emptyMRCItem *1071 (MRCItem 26486 litem &1057 26671 26487 pos 1 26672 26488 dimension 20 … … 26674 26490 uid 97,0 26675 26491 optionalChildren [ 26676 *107 9(MRCItem26677 litem &10 6526492 *1072 (MRCItem 26493 litem &1058 26678 26494 pos 0 26679 26495 dimension 20 26680 26496 uid 98,0 26681 26497 ) 26682 *10 80(MRCItem26683 litem &10 6626498 *1073 (MRCItem 26499 litem &1059 26684 26500 pos 1 26685 26501 dimension 23 26686 26502 uid 99,0 26687 26503 ) 26688 *10 81(MRCItem26689 litem &106 726504 *1074 (MRCItem 26505 litem &1060 26690 26506 pos 2 26691 26507 hidden 1 … … 26693 26509 uid 100,0 26694 26510 ) 26695 *10 82(MRCItem26696 litem &10 7626511 *1075 (MRCItem 26512 litem &1069 26697 26513 pos 0 26698 26514 dimension 20 … … 26710 26526 uid 101,0 26711 26527 optionalChildren [ 26712 *10 83(MRCItem26713 litem &106 826528 *1076 (MRCItem 26529 litem &1061 26714 26530 pos 0 26715 26531 dimension 20 26716 26532 uid 102,0 26717 26533 ) 26718 *10 84(MRCItem26719 litem &10 7026534 *1077 (MRCItem 26535 litem &1063 26720 26536 pos 1 26721 26537 dimension 50 26722 26538 uid 103,0 26723 26539 ) 26724 *10 85(MRCItem26725 litem &10 7126540 *1078 (MRCItem 26541 litem &1064 26726 26542 pos 2 26727 26543 dimension 186 26728 26544 uid 104,0 26729 26545 ) 26730 *10 86(MRCItem26731 litem &10 7226546 *1079 (MRCItem 26547 litem &1065 26732 26548 pos 3 26733 26549 dimension 96 26734 26550 uid 105,0 26735 26551 ) 26736 *108 7(MRCItem26737 litem &10 7326552 *1080 (MRCItem 26553 litem &1066 26738 26554 pos 4 26739 26555 dimension 50 26740 26556 uid 106,0 26741 26557 ) 26742 *108 8(MRCItem26743 litem &10 7426558 *1081 (MRCItem 26559 litem &1067 26744 26560 pos 5 26745 26561 dimension 50 26746 26562 uid 107,0 26747 26563 ) 26748 *108 9(MRCItem26749 litem &10 7526564 *1082 (MRCItem 26565 litem &1068 26750 26566 pos 6 26751 26567 dimension 80 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb
r10129 r10138 1199 1199 (vvPair 1200 1200 variable "date" 1201 value "0 4.02.2011"1201 value "08.02.2011" 1202 1202 ) 1203 1203 (vvPair 1204 1204 variable "day" 1205 value " Fr"1205 value "Di" 1206 1206 ) 1207 1207 (vvPair 1208 1208 variable "day_long" 1209 value " Freitag"1209 value "Dienstag" 1210 1210 ) 1211 1211 (vvPair 1212 1212 variable "dd" 1213 value "0 4"1213 value "08" 1214 1214 ) 1215 1215 (vvPair … … 1351 1351 (vvPair 1352 1352 variable "time" 1353 value "1 2:56:44"1353 value "11:06:22" 1354 1354 ) 1355 1355 (vvPair … … 4000 4000 ) 4001 4001 ) 4002 lastUid 5 873,04002 lastUid 5942,0 4003 4003 okToSyncOnLoad 1 4004 4004 OkToSyncGenericsOnLoad 1 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/w5300_modul/symbol.sb
r10123 r10138 347 347 t "std_logic_vector" 348 348 b "(7 downto 0)" 349 prec "-- read/write configRAM" 350 preAdd 0 349 351 o 25 350 352 suid 24,0 … … 358 360 n "config_busy" 359 361 t "std_logic" 360 pre c "-- --"361 p reAdd 0362 preAdd 0 363 posAdd 0 362 364 o 31 363 365 suid 25,0 … … 385 387 n "config_started" 386 388 t "std_logic" 389 posAdd 0 387 390 o 24 388 391 suid 27,0 … … 410 413 n "new_config" 411 414 t "std_logic" 412 prec "--" 415 prec "-- FAD configuration signals: 416 ------------------------------------------------------------------------------ 417 -- start entire configuration chain" 413 418 preAdd 0 414 419 o 23 … … 441 446 eolc "-- default domino wave off" 442 447 posAdd 0 443 o 3 5448 o 36 444 449 suid 31,0 445 450 i "'0'" … … 457 462 preAdd 0 458 463 posAdd 0 459 o 3 6464 o 37 460 465 suid 32,0 461 466 i "'0'" … … 485 490 eolc "-- default DWRITE HIGH." 486 491 posAdd 0 487 o 3 7492 o 38 488 493 suid 35,0 489 494 i "'1'" … … 498 503 n "ps_direction" 499 504 t "std_logic" 505 prec "------------------------------------------------------------------------------ 506 507 -- ADC CLK generator, is able to shift phase with respect to X_50M 508 -- these signals control the behavior of the digital clock manager (DCM) 509 ------------------------------------------------------------------------------" 500 510 eolc "-- default phase shift upwards" 501 posAdd 0 502 o 38 511 preAdd 0 512 posAdd 0 513 o 40 503 514 suid 36,0 504 515 i "'1'" … … 516 527 preAdd 0 517 528 posAdd 0 518 o 39529 o 41 519 530 suid 37,0 520 531 i "'0'" … … 531 542 eolc "-- pulse this to reset the variable phase shift" 532 543 posAdd 0 533 o 4 0544 o 42 534 545 suid 38,0 535 546 i "'0'" … … 546 557 eolc "-- default SRCLK on." 547 558 posAdd 0 548 o 41559 o 39 549 560 suid 39,0 550 561 i "'1'" … … 558 569 n "config_rw_ack" 559 570 t "std_logic" 560 prec "-- --"561 571 preAdd 0 562 572 posAdd 0 … … 572 582 n "config_rw_ready" 573 583 t "std_logic" 574 prec "-- --"575 584 preAdd 0 576 585 posAdd 0 … … 587 596 n "socks_connected" 588 597 t "std_logic" 598 posc "------------------------------------------------------------------------------" 599 posAdd 0 589 600 o 44 590 601 suid 42,0 … … 599 610 n "socks_waiting" 600 611 t "std_logic" 612 prec "------------------------------------------------------------------------------ 613 614 -- signals used to control FAD LED bahavior: 615 -- one of the three LEDs is used for com-status info 616 ------------------------------------------------------------------------------" 601 617 preAdd 0 602 618 o 43 … … 612 628 n "trigger_enable" 613 629 t "std_logic" 630 prec "------------------------------------------------------------------------------ 631 632 -- user controllable enable signals 633 ------------------------------------------------------------------------------" 614 634 eolc "-- default triggers are NOT accepted" 615 posAdd 0 616 o 42 635 preAdd 0 636 posAdd 0 637 o 35 617 638 suid 44,0 618 639 i "'0'" … … 656 677 t "std_logic_vector" 657 678 b "(1 downto 0)" 679 prec "------------------------------------------------------------------------------ 680 681 -- MAC/IP calculation signals: 682 ------------------------------------------------------------------------------" 683 preAdd 0 658 684 o 32 659 685 suid 48,0 … … 680 706 t "std_logic_vector" 681 707 b "(1 downto 0)" 708 posAdd 0 682 709 o 34 683 710 suid 50,0 … … 1114 1141 value "14" 1115 1142 ) 1116 uid 13 29,01143 uid 1354,0 1117 1144 ) 1118 1145 ] … … 1170 1197 pos 0 1171 1198 dimension 20 1172 uid 13 30,01199 uid 1355,0 1173 1200 ) 1174 1201 ] … … 1283 1310 (vvPair 1284 1311 variable "date" 1285 value " 27.01.2011"1312 value "08.02.2011" 1286 1313 ) 1287 1314 (vvPair 1288 1315 variable "day" 1289 value "D o"1316 value "Di" 1290 1317 ) 1291 1318 (vvPair 1292 1319 variable "day_long" 1293 value "D onnerstag"1320 value "Dienstag" 1294 1321 ) 1295 1322 (vvPair 1296 1323 variable "dd" 1297 value " 27"1324 value "08" 1298 1325 ) 1299 1326 (vvPair … … 1359 1386 (vvPair 1360 1387 variable "mm" 1361 value "0 1"1388 value "02" 1362 1389 ) 1363 1390 (vvPair … … 1367 1394 (vvPair 1368 1395 variable "month" 1369 value " Jan"1396 value "Feb" 1370 1397 ) 1371 1398 (vvPair 1372 1399 variable "month_long" 1373 value " Januar"1400 value "Februar" 1374 1401 ) 1375 1402 (vvPair … … 1403 1430 (vvPair 1404 1431 variable "task_ModelSimPath" 1405 value " <TBD>"1432 value "C:\\modeltech_6.6a\\win32" 1406 1433 ) 1407 1434 (vvPair … … 1435 1462 (vvPair 1436 1463 variable "time" 1437 value "1 5:14:14"1464 value "10:18:42" 1438 1465 ) 1439 1466 (vvPair … … 2161 2188 xt "200,31000,13900,35000" 2162 2189 st " 2163 ---- Uncomment the following library declaration if instantiating 2164 ---- any Xilinx primitives in this code. 2165 --library UNISIM; 2166 --use UNISIM.VComponents.all; 2190 2167 2191 " 2168 2192 tm "CommentText" … … 2439 2463 font "Courier New,8,0" 2440 2464 ) 2441 xt "2000,36800,33000,37600" 2442 st "config_addr : OUT std_logic_vector (7 downto 0) ; 2465 xt "2000,38400,33000,40000" 2466 st "-- read/write configRAM 2467 config_addr : OUT std_logic_vector (7 downto 0) ; 2443 2468 " 2444 2469 ) … … 2449 2474 t "std_logic_vector" 2450 2475 b "(7 downto 0)" 2476 prec "-- read/write configRAM" 2477 preAdd 0 2451 2478 o 25 2452 2479 suid 24,0 … … 2485 2512 font "Courier New,8,0" 2486 2513 ) 2487 xt "2000,43200,23000,44800" 2488 st "-- -- 2489 config_busy : IN std_logic ; 2514 xt "2000,44000,23000,44800" 2515 st "config_busy : IN std_logic ; 2490 2516 " 2491 2517 ) … … 2494 2520 n "config_busy" 2495 2521 t "std_logic" 2496 pre c "-- --"2497 p reAdd 02522 preAdd 0 2523 posAdd 0 2498 2524 o 31 2499 2525 suid 25,0 … … 2533 2559 font "Courier New,8,0" 2534 2560 ) 2535 xt "2000, 37600,43000,38400"2561 xt "2000,40000,43000,40800" 2536 2562 st "config_data : INOUT std_logic_vector (15 downto 0) := (others => 'Z') ; 2537 2563 " … … 2580 2606 font "Courier New,8,0" 2581 2607 ) 2582 xt "2000,3 6000,23000,36800"2608 xt "2000,37600,23000,38400" 2583 2609 st "config_started : IN std_logic ; 2584 2610 " … … 2588 2614 n "config_started" 2589 2615 t "std_logic" 2616 posAdd 0 2590 2617 o 24 2591 2618 suid 27,0 … … 2625 2652 font "Courier New,8,0" 2626 2653 ) 2627 xt "2000, 38400,37000,39200"2654 xt "2000,40800,37000,41600" 2628 2655 st "config_wr_en : OUT std_logic := '0' ; 2629 2656 " … … 2672 2699 font "Courier New,8,0" 2673 2700 ) 2674 xt "2000,34400,37000,36000" 2675 st "-- 2701 xt "2000,34400,43000,37600" 2702 st "-- FAD configuration signals: 2703 ------------------------------------------------------------------------------ 2704 -- start entire configuration chain 2676 2705 new_config : OUT std_logic := '0' ; 2677 2706 " … … 2682 2711 n "new_config" 2683 2712 t "std_logic" 2684 prec "--" 2713 prec "-- FAD configuration signals: 2714 ------------------------------------------------------------------------------ 2715 -- start entire configuration chain" 2685 2716 preAdd 0 2686 2717 o 23 … … 2722 2753 font "Courier New,8,0" 2723 2754 ) 2724 xt "2000, 39200,37000,40000"2755 xt "2000,41600,37000,42400" 2725 2756 st "config_rd_en : OUT std_logic := '0' ; 2726 2757 " … … 2770 2801 font "Courier New,8,0" 2771 2802 ) 2772 xt "2000, 47200,50500,48000"2803 xt "2000,54400,50500,55200" 2773 2804 st "denable : OUT std_logic := '0' ; -- default domino wave off 2774 2805 " … … 2781 2812 eolc "-- default domino wave off" 2782 2813 posAdd 0 2783 o 3 52814 o 36 2784 2815 suid 31,0 2785 2816 i "'0'" … … 2819 2850 font "Courier New,8,0" 2820 2851 ) 2821 xt "2000, 48000,48500,48800"2852 xt "2000,55200,48500,56000" 2822 2853 st "dwrite_enable : OUT std_logic := '0' ; -- default DWRITE low. 2823 2854 " … … 2831 2862 preAdd 0 2832 2863 posAdd 0 2833 o 3 62864 o 37 2834 2865 suid 32,0 2835 2866 i "'0'" … … 2916 2947 font "Courier New,8,0" 2917 2948 ) 2918 xt "2000, 48800,49000,49600"2949 xt "2000,56000,49000,56800" 2919 2950 st "sclk_enable : OUT std_logic := '1' ; -- default DWRITE HIGH. 2920 2951 " … … 2927 2958 eolc "-- default DWRITE HIGH." 2928 2959 posAdd 0 2929 o 3 72960 o 38 2930 2961 suid 35,0 2931 2962 i "'1'" … … 2965 2996 font "Courier New,8,0" 2966 2997 ) 2967 xt "2000,49600,52500,50400" 2968 st "ps_direction : OUT std_logic := '1' ; -- default phase shift upwards 2998 xt "2000,57600,52500,62400" 2999 st "------------------------------------------------------------------------------ 3000 3001 -- ADC CLK generator, is able to shift phase with respect to X_50M 3002 -- these signals control the behavior of the digital clock manager (DCM) 3003 ------------------------------------------------------------------------------ 3004 ps_direction : OUT std_logic := '1' ; -- default phase shift upwards 2969 3005 " 2970 3006 ) … … 2974 3010 n "ps_direction" 2975 3011 t "std_logic" 3012 prec "------------------------------------------------------------------------------ 3013 3014 -- ADC CLK generator, is able to shift phase with respect to X_50M 3015 -- these signals control the behavior of the digital clock manager (DCM) 3016 ------------------------------------------------------------------------------" 2976 3017 eolc "-- default phase shift upwards" 2977 posAdd 0 2978 o 38 3018 preAdd 0 3019 posAdd 0 3020 o 40 2979 3021 suid 36,0 2980 3022 i "'1'" … … 3014 3056 font "Courier New,8,0" 3015 3057 ) 3016 xt "2000, 50400,53500,51200"3058 xt "2000,62400,53500,63200" 3017 3059 st "ps_do_phase_shift : OUT std_logic := '0' ; --pulse this to phase shift once 3018 3060 " … … 3026 3068 preAdd 0 3027 3069 posAdd 0 3028 o 393070 o 41 3029 3071 suid 37,0 3030 3072 i "'0'" … … 3064 3106 font "Courier New,8,0" 3065 3107 ) 3066 xt "2000, 51200,61000,52000"3108 xt "2000,63200,61000,64000" 3067 3109 st "ps_reset : OUT std_logic := '0' ; -- pulse this to reset the variable phase shift 3068 3110 " … … 3075 3117 eolc "-- pulse this to reset the variable phase shift" 3076 3118 posAdd 0 3077 o 4 03119 o 42 3078 3120 suid 38,0 3079 3121 i "'0'" … … 3113 3155 font "Courier New,8,0" 3114 3156 ) 3115 xt "2000,5 2000,47500,52800"3157 xt "2000,56800,47500,57600" 3116 3158 st "srclk_enable : OUT std_logic := '1' ; -- default SRCLK on. 3117 3159 " … … 3124 3166 eolc "-- default SRCLK on." 3125 3167 posAdd 0 3126 o 413168 o 39 3127 3169 suid 39,0 3128 3170 i "'1'" … … 3161 3203 font "Courier New,8,0" 3162 3204 ) 3163 xt "2000,40000,23000,41600" 3164 st "-- -- 3165 config_rw_ack : IN std_logic ; 3205 xt "2000,42400,23000,43200" 3206 st "config_rw_ack : IN std_logic ; 3166 3207 " 3167 3208 ) … … 3170 3211 n "config_rw_ack" 3171 3212 t "std_logic" 3172 prec "-- --"3173 3213 preAdd 0 3174 3214 posAdd 0 … … 3209 3249 font "Courier New,8,0" 3210 3250 ) 3211 xt "2000,41600,23000,43200" 3212 st "-- -- 3213 config_rw_ready : IN std_logic ; 3251 xt "2000,43200,23000,44000" 3252 st "config_rw_ready : IN std_logic ; 3214 3253 " 3215 3254 ) … … 3218 3257 n "config_rw_ready" 3219 3258 t "std_logic" 3220 prec "-- --"3221 3259 preAdd 0 3222 3260 posAdd 0 … … 3258 3296 font "Courier New,8,0" 3259 3297 ) 3260 xt "2000, 54400,22000,55200"3298 xt "2000,68800,43000,70400" 3261 3299 st "socks_connected : OUT std_logic 3300 ------------------------------------------------------------------------------ 3262 3301 " 3263 3302 ) … … 3267 3306 n "socks_connected" 3268 3307 t "std_logic" 3308 posc "------------------------------------------------------------------------------" 3309 posAdd 0 3269 3310 o 44 3270 3311 suid 42,0 … … 3304 3345 font "Courier New,8,0" 3305 3346 ) 3306 xt "2000,53600,23000,54400" 3307 st "socks_waiting : OUT std_logic ; 3347 xt "2000,64000,43000,68800" 3348 st "------------------------------------------------------------------------------ 3349 3350 -- signals used to control FAD LED bahavior: 3351 -- one of the three LEDs is used for com-status info 3352 ------------------------------------------------------------------------------ 3353 socks_waiting : OUT std_logic ; 3308 3354 " 3309 3355 ) … … 3313 3359 n "socks_waiting" 3314 3360 t "std_logic" 3361 prec "------------------------------------------------------------------------------ 3362 3363 -- signals used to control FAD LED bahavior: 3364 -- one of the three LEDs is used for com-status info 3365 ------------------------------------------------------------------------------" 3315 3366 preAdd 0 3316 3367 o 43 … … 3351 3402 font "Courier New,8,0" 3352 3403 ) 3353 xt "2000,52800,55500,53600" 3354 st "trigger_enable : OUT std_logic := '0' ; -- default triggers are NOT accepted 3404 xt "2000,50400,55500,54400" 3405 st "------------------------------------------------------------------------------ 3406 3407 -- user controllable enable signals 3408 ------------------------------------------------------------------------------ 3409 trigger_enable : OUT std_logic := '0' ; -- default triggers are NOT accepted 3355 3410 " 3356 3411 ) … … 3360 3415 n "trigger_enable" 3361 3416 t "std_logic" 3417 prec "------------------------------------------------------------------------------ 3418 3419 -- user controllable enable signals 3420 ------------------------------------------------------------------------------" 3362 3421 eolc "-- default triggers are NOT accepted" 3363 posAdd 0 3364 o 42 3422 preAdd 0 3423 posAdd 0 3424 o 35 3365 3425 suid 44,0 3366 3426 i "'0'" … … 3496 3556 font "Courier New,8,0" 3497 3557 ) 3498 xt "2000,44800,33000,45600" 3499 st "MAC_jumper : IN std_logic_vector (1 downto 0) ; 3558 xt "2000,44800,43000,48800" 3559 st "------------------------------------------------------------------------------ 3560 3561 -- MAC/IP calculation signals: 3562 ------------------------------------------------------------------------------ 3563 MAC_jumper : IN std_logic_vector (1 downto 0) ; 3500 3564 " 3501 3565 ) … … 3505 3569 t "std_logic_vector" 3506 3570 b "(1 downto 0)" 3571 prec "------------------------------------------------------------------------------ 3572 3573 -- MAC/IP calculation signals: 3574 ------------------------------------------------------------------------------" 3575 preAdd 0 3507 3576 o 32 3508 3577 suid 48,0 … … 3541 3610 font "Courier New,8,0" 3542 3611 ) 3543 xt "2000,4 5600,33000,46400"3612 xt "2000,48800,33000,49600" 3544 3613 st "BoardID : IN std_logic_vector (3 downto 0) ; 3545 3614 " … … 3586 3655 font "Courier New,8,0" 3587 3656 ) 3588 xt "2000,4 6400,33000,47200"3657 xt "2000,49600,33000,50400" 3589 3658 st "CrateID : IN std_logic_vector (1 downto 0) ; 3590 3659 " … … 3595 3664 t "std_logic_vector" 3596 3665 b "(1 downto 0)" 3666 posAdd 0 3597 3667 o 34 3598 3668 suid 50,0 … … 4276 4346 font "Arial,8,1" 4277 4347 ) 4278 xt "0, 55200,2400,56200"4348 xt "0,70400,2400,71400" 4279 4349 st "User:" 4280 blo "0, 56000"4350 blo "0,71200" 4281 4351 ) 4282 4352 internalLabel (Text … … 4295 4365 font "Courier New,8,0" 4296 4366 ) 4297 xt "2000, 56200,2000,56200"4367 xt "2000,71400,2000,71400" 4298 4368 tm "SyDeclarativeTextMgr" 4299 4369 ) … … 4308 4378 ) 4309 4379 ) 4310 lastUid 13 30,04380 lastUid 1355,0 4311 4381 activeModelName "Symbol:CDM" 4312 4382 )
Note:
See TracChangeset
for help on using the changeset viewer.