Changeset 10149
- Timestamp:
- 02/09/11 11:16:09 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 2 edited
-
REFCLK_counter_behavior.vhd (modified) (1 diff)
-
phase_shifter.vhd (modified) (6 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/REFCLK_counter_behavior.vhd
r10129 r10149 26 26 counter_result : out std_logic_vector(11 downto 0) := (others => '0'); 27 27 28 alarm_refclk_too_high : out std_logic := ' 0';29 alarm_refclk_too_low : out std_logic := ' 0'28 alarm_refclk_too_high : out std_logic := '1'; 29 alarm_refclk_too_low : out std_logic := '1' 30 30 ); 31 31 END ENTITY REFCLK_counter; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd
r10129 r10149 5 5 -- and clock_generator_variable_PS_struct.vhd 6 6 -- 7 --8 --9 7 library ieee; 10 8 use ieee.std_logic_1164.all; … … 19 17 PORT( 20 18 CLK : IN std_logic; 21 rst : in std_logic; --asynch in of DCM19 rst : out std_logic := '0'; --asynch in of DCM 22 20 23 21 -- interface to: clock_generator_variable_PS_struct.vhd … … 26 24 PSINCDEC : OUT std_logic := '1'; -- default is 'incrementing' 27 25 PSDONE : IN std_logic; -- will pulse once, if phase shifting was done. 28 LOCKED : IN std_logic; 26 LOCKED : IN std_logic; -- when is this going high? 29 27 30 28 … … 32 30 shift_phase : IN std_logic; 33 31 direction : IN std_logic; -- corresponds to 'PSINCDEC' 34 32 reset_DCM : in std_logic; -- asynch in: orders us, to reset the DCM 33 35 34 -- status: 36 35 shifting : OUT std_logic := '0'; … … 72 71 73 72 architecture first_behave of phase_shifter is 74 constant OFFS_MIN : integer := - 128;75 constant OFFS_MAX : integer := 127;73 constant OFFS_MIN : integer := -51; 74 constant OFFS_MAX : integer := 51; 76 75 77 type states is (INIT, READY_STATE, SHIFTING_STATE, WAITINGFORDONE);76 type states is (INIT, READY_STATE, PRE_SHIFTING_STATE, SHIFTING_STATE, WAITINGFORDONE, RESET_STATE); 78 77 signal state,next_state : states := INIT; 79 78 80 79 signal local_direction : std_logic; 81 80 signal offset_int : integer range OFFS_MIN to OFFS_MAX := 0; 82 83 84 81 signal lower_limit_reached : std_logic := '0'; 82 signal upper_limit_reached : std_logic := '0'; 83 84 signal reset_dcm_sr : std_logic_vector(1 downto 0) := "00"; 85 signal shift_phase_sr : std_logic_vector(1 downto 0) := "00"; 86 signal ready_int : std_logic := '0'; 85 87 begin 86 88 87 89 -- concurrent statements: 88 90 DCM_locked <= LOCKED; 91 ready <= ready_int; 89 92 PSCLK <= CLK; 90 offset <= std_logic_vector(to_signed(offset_int,8));93 offset <= LOCKED & ready_int & std_logic_vector(to_signed(offset_int,6)); 91 94 92 95 -- MAIN FSM: go to next state if rising edge, or to INIT if LOCKED not high. 96 -- is this really coorect? 97 93 98 FSM_Registers: process(CLK, LOCKED, rst) 94 99 begin 95 if rst = '1' then 96 state <= INIT; 97 elsif LOCKED = '0' then 100 if LOCKED = '0' then 98 101 state <= INIT; 99 102 elsif Rising_edge(CLK) then … … 106 109 begin 107 110 next_state <= state; 111 reset_dcm_sr <= reset_dcm_sr(1) & reset_DCM; --synch in 112 shift_phase_sr <= shift_phase_sr(1) & shift_phase; --synch in 108 113 case state is 109 110 -- INIT state: here the FSM is idling, when LOCKED is not HIGH. 111 when INIT => 112 ready <= '0'; 113 offset_int <= 0; 114 shifting <= '0'; 115 PSEN <= '0'; 116 if (LOCKED = '1') then 117 next_state <= READY_STATE; 118 else 114 -- INIT state: here the FSM is idling, when LOCKED is not HIGH. 115 when INIT => 116 rst <= '0'; 117 ready_int <= '0'; 118 shifting <= '0'; 119 PSEN <= '0'; 120 offset_int <= 0; 121 if (LOCKED = '1') then 122 next_state <= READY_STATE; 123 else 124 next_state <= INIT; 125 end if; 126 -- RESET state: when ordered to do so: DCM is reseted and FSM send back to INIT. 127 when RESET_STATE => 128 rst <= '1'; 129 ready_int <= '0'; 130 shifting <= '0'; 131 PSEN <= '0'; 119 132 next_state <= INIT; 120 end if; 121 122 -- READY_STATE state: here FSM is waiting for the 'shift_phase' to go high 123 when READY_STATE => 124 ready <= '1'; 125 shifting <= '0'; 126 PSEN <= '0'; 127 if (shift_phase = '1') then 128 next_state <= SHIFTING_STATE; 129 local_direction <= direction; -- direction is sampled, once 'shift_phase' goes high 130 else 131 next_state <= READY_STATE; 132 end if; 133 134 -- SHIFTING_STATE state: PSENC is set HIGH here and set low in the next state. 135 when SHIFTING_STATE => 136 ready <= '1'; 137 shifting <= '1'; 138 PSEN <= '1'; 139 PSINCDEC <= local_direction; -- this is the value of 'direction', when 'shift_phase' went up. 140 next_state <= WAITINGFORDONE; 141 142 -- WAITINGFORDONE state: PSENC is set LOW, ensuring that is was high only one clock cycle. 143 when WAITINGFORDONE => 144 ready <= '1'; 145 shifting <= '1'; 146 PSEN <= '0'; 147 if (PSDONE = '1') then 148 next_state <= READY_STATE; 149 if (local_direction = '1') then 150 if (offset_int < OFFS_MAX) then 151 offset_int <= offset_int + 1; 152 end if; 153 else 154 if (offset_int > OFFS_MIN) then 155 offset_int <= offset_int - 1; 156 end if; 157 end if; 158 else 159 next_state <= WAITINGFORDONE; 160 end if; 161 133 134 -- READY_STATE state: here FSM is waiting for the 'shift_phase' to go high, or 135 -- if reset_DCM goes high, we will reset the DCM and go back to init. 136 when READY_STATE => 137 ready_int <= '1'; 138 shifting <= '0'; 139 PSEN <= '0'; 140 141 lower_limit_reached <='0'; 142 upper_limit_reached <='0'; 143 if (offset_int = OFFS_MIN) then 144 lower_limit_reached <= '1'; 145 elsif (offset_int = OFFS_MAX) then 146 upper_limit_reached <= '1'; 147 end if; 148 149 if (shift_phase_sr = "01") then 150 local_direction <= direction; -- direction is sampled, once 'shift_phase' goes high 151 next_state <= PRE_SHIFTING_STATE; 152 else 153 next_state <= READY_STATE; 154 end if; 155 156 if (reset_dcm_sr = "01") then 157 next_state <= RESET_STATE; 158 end if; 159 160 -- checks if possible to shift in asked direction. If not ... back to READY. 161 when PRE_SHIFTING_STATE => 162 ready_int <= '0'; 163 if (local_direction = '1' and upper_limit_reached = '1') or 164 (local_direction = '0' and lower_limit_reached = '1') then 165 next_state <= READY_STATE; 166 else 167 next_state <= SHIFTING_STATE; 168 end if; 169 170 171 -- SHIFTING_STATE state: PSENC is set HIGH here and set low in the next state. 172 when SHIFTING_STATE => 173 ready_int <= '0'; 174 shifting <= '1'; 175 PSEN <= '1'; 176 PSINCDEC <= local_direction; -- this is the value of 'direction', when 'shift_phase' went up. 177 next_state <= WAITINGFORDONE; 178 179 -- WAITINGFORDONE state: PSENC is set LOW, ensuring that is was high only one clock cycle. 180 when WAITINGFORDONE => 181 ready_int <= '0'; 182 shifting <= '1'; 183 PSEN <= '0'; 184 if (PSDONE = '1') then 185 next_state <= READY_STATE; 186 if (local_direction = '1') then 187 offset_int <= offset_int + 1; 188 else 189 offset_int <= offset_int - 1; 190 end if; 191 else 192 next_state <= WAITINGFORDONE; 193 end if; 194 195 -- does this work???? 196 when others => 197 next_state <= RESET_STATE; 198 162 199 end case; 163 200 end process; 164 201 165 166 167 202 end first_behave;
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