- Timestamp:
- 02/12/11 12:06:02 (14 years ago)
- File:
-
- 1 edited
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd
r10149 r10154 35 35 shifting : OUT std_logic := '0'; 36 36 ready : OUT std_logic := '0'; 37 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ;38 DCM_locked : OUT std_logic37 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') 38 39 39 40 40 ); … … 71 71 72 72 architecture first_behave of phase_shifter is 73 74 75 73 constant OFFS_MIN : integer := -51; 74 constant OFFS_MAX : integer := 51; 75 76 76 type states is (INIT, READY_STATE, PRE_SHIFTING_STATE, SHIFTING_STATE, WAITINGFORDONE, RESET_STATE); 77 signal state ,next_state: states := INIT;77 signal state : states := INIT; 78 78 79 79 signal local_direction : std_logic; … … 88 88 89 89 -- concurrent statements: 90 DCM_locked <= LOCKED;91 90 ready <= ready_int; 92 91 PSCLK <= CLK; 93 92 offset <= LOCKED & ready_int & std_logic_vector(to_signed(offset_int,6)); 94 93 95 -- MAIN FSM: go to next state if rising edge, or to INIT if LOCKED not high. 96 -- is this really coorect? 97 98 FSM_Registers: process(CLK, LOCKED, rst) 99 begin 100 if LOCKED = '0' then 101 state <= INIT; 102 elsif Rising_edge(CLK) then 103 state <= next_state; 104 end if; 105 end process; 106 107 -- MAIN FSM 108 FSM_logic: process(state, PSDONE, LOCKED, shift_phase, direction, local_direction) 109 begin 110 next_state <= state; 94 -- MAIN FSM 95 FSM: process(state, PSDONE, LOCKED, shift_phase, direction, local_direction) 96 begin 97 98 if rising_edge(CLK) then 111 99 reset_dcm_sr <= reset_dcm_sr(1) & reset_DCM; --synch in 112 100 shift_phase_sr <= shift_phase_sr(1) & shift_phase; --synch in 113 case state is 101 102 case state is 114 103 -- INIT state: here the FSM is idling, when LOCKED is not HIGH. 115 104 when INIT => … … 120 109 offset_int <= 0; 121 110 if (LOCKED = '1') then 122 next_state <= READY_STATE;111 state <= READY_STATE; 123 112 else 124 next_state <= INIT;113 state <= INIT; 125 114 end if; 115 126 116 -- RESET state: when ordered to do so: DCM is reseted and FSM send back to INIT. 127 117 when RESET_STATE => … … 130 120 shifting <= '0'; 131 121 PSEN <= '0'; 132 next_state <= INIT;122 state <= INIT; 133 123 134 124 -- READY_STATE state: here FSM is waiting for the 'shift_phase' to go high, or … … 149 139 if (shift_phase_sr = "01") then 150 140 local_direction <= direction; -- direction is sampled, once 'shift_phase' goes high 151 next_state <= PRE_SHIFTING_STATE;141 state <= PRE_SHIFTING_STATE; 152 142 else 153 next_state <= READY_STATE;143 state <= READY_STATE; 154 144 end if; 155 145 156 146 if (reset_dcm_sr = "01") then 157 next_state <= RESET_STATE;147 state <= RESET_STATE; 158 148 end if; 159 149 … … 163 153 if (local_direction = '1' and upper_limit_reached = '1') or 164 154 (local_direction = '0' and lower_limit_reached = '1') then 165 next_state <= READY_STATE;155 state <= READY_STATE; 166 156 else 167 next_state <= SHIFTING_STATE;157 state <= SHIFTING_STATE; 168 158 end if; 169 159 … … 175 165 PSEN <= '1'; 176 166 PSINCDEC <= local_direction; -- this is the value of 'direction', when 'shift_phase' went up. 177 next_state <= WAITINGFORDONE;167 state <= WAITINGFORDONE; 178 168 179 169 -- WAITINGFORDONE state: PSENC is set LOW, ensuring that is was high only one clock cycle. … … 183 173 PSEN <= '0'; 184 174 if (PSDONE = '1') then 185 next_state <= READY_STATE;175 state <= READY_STATE; 186 176 if (local_direction = '1') then 187 177 offset_int <= offset_int + 1; … … 190 180 end if; 191 181 else 192 next_state <= WAITINGFORDONE;182 state <= WAITINGFORDONE; 193 183 end if; 194 184 195 185 -- does this work???? 196 186 when others => 197 next_state <= RESET_STATE;187 state <= RESET_STATE; 198 188 199 end case; 200 end process; 189 end case; 190 end if; 191 end process; 201 192 202 193 end first_behave;
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