Changeset 10155 for firmware


Ignore:
Timestamp:
Feb 15, 2011, 12:07:05 PM (9 years ago)
Author:
neise
Message:
highly unstable version !!!
Location:
firmware/FAD
Files:
5 added
25 edited

Legend:

Unmodified
Added
Removed
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD.hdp

    r10129 r10155  
    55FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/work
    66secureip = D:/unisim/secureip
    7 simprim = D:/unisim/simprim
    8 unimacro = D:/unisim/unimacro
    9 unisim = D:/unisim/unisim
    10 XilinxCoreLib = D:/unisim/xilinxcorelib
     7simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
     8unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
     9unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
     10XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
    1111[QuestaSim]
    1212secureip = D:/unisim/secureip
    13 simprim = D:/unisim/simprim
    14 unimacro = D:/unisim/unimacro
    15 unisim = D:/unisim/unisim
    16 XilinxCoreLib = D:/unisim/xilinxcorelib
     13simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
     14unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
     15unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
     16XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
    1717[XilinxISE]
    1818FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/ise
    19 FACT_FAD_TB_lib = $HDS_PROJECT_DIR\FACT_FAD_TB_lib\ise
     19FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise
    2020[hdl]
    2121FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hdl
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd

    r10129 r10155  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 15:27:49 04.02.2011
     5--          at - 13:26:27 14.02.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    3232-- Created:
    3333--          by - dneise.UNKNOWN (E5B-LABOR6)
    34 --          at - 15:27:49 04.02.2011
     34--          at - 13:26:27 14.02.2011
    3535--
    3636-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    4242LIBRARY UNISIM;
    4343--USE UNISIM.Vcomponents.all;
     44LIBRARY FACT_FAD_lib;
     45USE FACT_FAD_lib.fad_definitions.all;
    4446
    4547LIBRARY FACT_FAD_lib;
     
    5658   SIGNAL PSEN_IN     : std_logic;
    5759   SIGNAL PSINCDEC_IN : std_logic;
     60   SIGNAL rst         : std_logic := '0';    --asynch in of DCM
    5861
    5962   -- Implicit buffer signal declarations
     
    9194   PORT (
    9295      CLK         : IN     std_logic ;
    93       rst         : IN     std_logic ;                                    --asynch in of DCM
     96      rst         : OUT    std_logic                     := '0'; --asynch in of DCM
    9497      -- interface to: clock_generator_variable_PS_struct.vhd
    9598      PSCLK       : OUT    std_logic ;
    9699      PSEN        : OUT    std_logic                     := '0';
    97       PSINCDEC    : OUT    std_logic                     := '1';           -- default is 'incrementing'
    98       PSDONE      : IN     std_logic ;                                     -- will pulse once, if phase shifting was done.
    99       LOCKED      : IN     std_logic ;
     100      PSINCDEC    : OUT    std_logic                     := '1'; -- default is 'incrementing'
     101      PSDONE      : IN     std_logic ;                           -- will pulse once, if phase shifting was done.
     102      LOCKED      : IN     std_logic ;                           -- when is this going high?
    100103      -- interface to: w5300_modul.vhd
    101104      shift_phase : IN     std_logic ;
    102       direction   : IN     std_logic ;                                     -- corresponds TO 'PSINCDEC'
     105      direction   : IN     std_logic ;                           -- corresponds TO 'PSINCDEC'
     106      reset_DCM   : IN     std_logic ;                           -- asynch in: orders us, TO reset the DCM
    103107      -- status:
    104108      shifting    : OUT    std_logic                     := '0';
    105109      ready       : OUT    std_logic                     := '0';
    106       offset      : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    107       DCM_locked  : OUT    std_logic
     110      offset      : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0')
    108111   );
    109112   END COMPONENT;
     
    139142         PSEN_IN     => PSEN_IN,
    140143         PSINCDEC_IN => PSINCDEC_IN,
    141          RST_IN      => RST_IN,
     144         RST_IN      => rst,
    142145         CLK0_OUT    => CLK_25_PS,
    143146         LOCKED_OUT  => LOCKED_OUT,
     
    147150      PORT MAP (
    148151         CLK         => CLK0_OUT,
    149          rst         => RST_IN,
     152         rst         => rst,
    150153         PSCLK       => PSCLK_IN,
    151154         PSEN        => PSEN_IN,
     
    155158         shift_phase => do_shift,
    156159         direction   => direction,
     160         reset_DCM   => RST_IN,
    157161         shifting    => OPEN,
    158162         ready       => OPEN,
    159          offset      => offset,
    160          DCM_locked  => OPEN
     163         offset      => offset
    161164      );
    162165
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd

    r10129 r10155  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 11:39:13 04.02.2011
     5--          at - 13:10:37 12.02.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    4242-- Created:
    4343--          by - dneise.UNKNOWN (E5B-LABOR6)
    44 --          at - 11:39:13 04.02.2011
     44--          at - 13:10:37 12.02.2011
    4545--
    4646-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd

    r10138 r10155  
    4545      sensor_ready : in std_logic;
    4646      dac_array : in dac_array_type;
     47     
     48      -- EVT HEADER - part 1
    4749      package_length : in std_logic_vector (15 downto 0);
     50      pll_lock                                                  : in std_logic_vector ( 3 downto 0);
     51      --
     52           
     53      -- EVT HEADER - part 2  --> FTM trigger informaton, comes in late ...
     54      -- during EVT header wrinting, this field is left out ... and only written into event header,
     55      -- when the DRS chip were read out already.
     56      FTM_RS485_ready : in std_logic;
     57      FTM_trigger_info : in std_logic_vector (55 downto 0); --7 byte
     58      --
     59     
     60                        -- EVT HEADER - part 3
     61      fad_event_counter     : in std_logic_vector (31 downto 0);
     62      refclk_counter    : in std_logic_vector (11 downto 0);
     63      refclk_too_high: in std_logic;
     64      refclk_too_low : in std_logic;
     65      --
     66     
     67      -- EVT HEADER - part 4
    4868      board_id       : in std_logic_vector (3 downto 0);
    4969      crate_id       : in std_logic_vector (1 downto 0);
    50       trigger_id     : in std_logic_vector (47 downto 0);
     70      DCM_PS_status     : in std_logic_vector (7 downto 0);
     71      TRG_GEN_no                                        : in std_logic_vector (15 downto 0);
     72      TRG_GEN_div                                       : in std_logic_vector (15 downto 0);
     73      --
     74     
     75      -- EVT HEADER - part 5
     76      dna                               : in std_logic_vector (63 downto 0);
     77      --
     78     
     79      -- EVT HEADER - part 6
     80      timer_value : in std_logic_vector (31 downto 0); -- time in units of 100us
     81      --
     82     
    5183      trigger        : in std_logic;
    5284--      s_trigger      : in std_logic;
     
    79111architecture Behavioral of data_generator is
    80112
    81 type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
    82                              WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
    83                              WRITE_END_FLAG, WRITE_DATA_STOP, WRITE_DATA_STOP1,
    84                              WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING);
     113type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7,
     114                                WRITE_DATA_IDLE,
     115                                WRITE_HEADER, WRITE_FTM_INFO, WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER, WRITE_BOARD_ID,
     116                                WRITE_DNA, WRITE_TIMER, WRITE_TEMPERATURES,
     117                                WRITE_DAC1, WRITE_DAC2,
     118                                WAIT_FOR_STOP_CELL,
     119                                START_DRS_READING,
     120                                WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_FILLING,
     121                                WAIT_FOR_ADC, WRITE_ADC_DATA,
     122                                WRITE_EXTERNAL_TRIGGER,
     123                                WRITE_END_FLAG,
     124                                WRITE_DATA_END, WRITE_DATA_END_WAIT,
     125                                WRITE_DATA_STOP, WRITE_DATA_STOP1);
    85126
    86127signal state_generate : state_generate_type := INIT;
     
    199240                                when WRITE_HEADER =>
    200241                                  write_ea <= "1";
    201           data_out <= X"0000" & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01";
    202                                         addr_cntr <= addr_cntr + 3;
    203                                         state_generate <= WRITE_BOARD_ID;
    204         when WRITE_BOARD_ID =>     -- crate ID & board ID
    205           data_out <= (63 downto 10 => '0') & crate_id & "1000" & board_id;
    206           addr_cntr <= addr_cntr + 1;
    207           state_generate <= WRITE_TEMPERATURES;
     242          data_out <= X"000" & pll_lock & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01";
     243                                        addr_cntr <= addr_cntr + 1; 
     244                                        state_generate <= WRITE_FTM_INFO;
     245                                       
     246                                when WRITE_FTM_INFO =>
     247                                        -- here we do not write the FTM info ... just jump over it.
     248                                        addr_cntr <= addr_cntr + 1; 
     249                                        state_generate <= WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER;
     250                                       
     251                                when WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER =>
     252                                data_out <= X"0000" &
     253                                                                                        refclk_too_high & refclk_too_low & "00" & refclk_counter &
     254                                                fad_event_counter(15 downto 0) &
     255                                                fad_event_counter(31 downto 16) ;
     256                                addr_cntr <= addr_cntr + 1;
     257                                state_generate <= WRITE_BOARD_ID;
     258                                -- crate ID & board ID
     259                                -- and a lot more...
     260                                        -- info about the phase shifter
     261                                        -- status of the trigger generator
     262        when WRITE_BOARD_ID =>     
     263          data_out <= TRG_GEN_div & TRG_GEN_no & X"00" & DCM_PS_status & "000000" & crate_id & "1000" & board_id;
     264          addr_cntr <= addr_cntr + 1;
     265          state_generate <= WRITE_DNA;
     266         
     267        when WRITE_DNA =>
     268                                data_out <= X"00" & dna(55 downto 0);
     269          addr_cntr <= addr_cntr + 1;
     270          state_generate <= WRITE_TIMER;
     271         
     272        when WRITE_TIMER =>
     273                data_out <= X"0000" & X"0000" & timer_value; -- 2times 16bit reserved for additional status info
     274                        addr_cntr <= addr_cntr + 1;
     275                        state_generate <= WRITE_TEMPERATURES;
     276
    208277        when WRITE_TEMPERATURES =>     -- temperatures
    209278          if (sensor_ready = '1') then
     
    248317
    249318        when WRITE_CHANNEL_ID =>    -- write DRS and Channel IDs
    250           data_out <= conv_std_logic_vector(0,10) & conv_std_logic_vector(3,2) & conv_std_logic_vector(channel_id,4)
    251                     & conv_std_logic_vector(0,10) & conv_std_logic_vector(2,2) & conv_std_logic_vector(channel_id,4)
    252                     & conv_std_logic_vector(0,10) & conv_std_logic_vector(1,2) & conv_std_logic_vector(channel_id,4)
    253                     & conv_std_logic_vector(0,10) & conv_std_logic_vector(0,2) & conv_std_logic_vector(channel_id,4);
     319          data_out <=  conv_std_logic_vector(3,12) & conv_std_logic_vector(channel_id,4)
     320                    &  conv_std_logic_vector(2,12) & conv_std_logic_vector(channel_id,4)
     321                    &  conv_std_logic_vector(1,12) & conv_std_logic_vector(channel_id,4)
     322                    &  conv_std_logic_vector(0,12) & conv_std_logic_vector(channel_id,4);
    254323          addr_cntr <= addr_cntr + 1;
    255324          state_generate <= WRITE_START_CELL;
     
    267336                    & "00000" & conv_std_logic_vector (roi_array((0) * 9 + channel_id), 11);
    268337          addr_cntr <= addr_cntr + 1;
    269           state_generate <= WAIT_FOR_ADC;
     338          state_generate <= WRITE_FILLING;
     339         
     340                when WRITE_FILLING =>    -- write FILLING
     341                                                data_out <= conv_std_logic_vector(0,64); -- filling
     342                                                addr_cntr <= addr_cntr + 1;
     343                                                state_generate <= WAIT_FOR_ADC;
     344 
    270345        when WAIT_FOR_ADC =>
    271346          -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
     
    281356                      & "000" & adc_otr(1) & adc_data_array(1)
    282357                      & "000" & adc_otr(0) & adc_data_array(0);
    283  --             data_out <= "00000" & conv_std_logic_vector (data_cntr, 11)
     358--             data_out <= "00000" & conv_std_logic_vector (data_cntr, 11)
    284359--                          & "00010" & conv_std_logic_vector (data_cntr, 11)
    285360--                          & "00100" & conv_std_logic_vector (data_cntr, 11)
     
    303378          end if;
    304379         
    305          
    306380        when WRITE_EXTERNAL_TRIGGER =>    -- external trigger ID
    307381          addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH);
    308 --          data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16);
    309           data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16);
    310           state_generate <= WRITE_INTERNAL_TRIGGER;
    311         when WRITE_INTERNAL_TRIGGER =>    -- internal trigger ID
    312           addr_out <= start_addr + conv_std_logic_vector(2, RAM_ADDR_WIDTH);
    313           data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16);
     382          data_out <=           FTM_trigger_info(15 downto 0)
     383                                                                                                & FTM_trigger_info(31 downto 16)
     384                                                                                                & FTM_trigger_info(47 downto 32)
     385                                                                                                & X"00" & FTM_trigger_info(55 downto 48);
    314386          state_generate <= WRITE_END_FLAG;
     387       
    315388                                when WRITE_END_FLAG =>
    316389          data_out <= (63 downto 32 => '0') & X"04FE" & X"4242";
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd

    r10129 r10155  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 15:27:51 04.02.2011
     5--          at - 13:26:28 14.02.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    7676-- Created:
    7777--          by - dneise.UNKNOWN (E5B-LABOR6)
    78 --          at - 15:27:51 04.02.2011
     78--          at - 13:26:28 14.02.2011
    7979--
    8080-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd

    r10138 r10155  
    5656  constant PACKAGE_HEADER_LENGTH : integer := 22;
    5757  constant PACKAGE_END_LENGTH : integer := 2; -- CRC and END-Flag
     58  constant CHANNEL_HEADER_SIZE : integer := 3;
    5859 
    5960  constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd

    r10129 r10155  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 15:27:49 04.02.2011
     5--          at - 13:26:27 14.02.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    7272-- Created:
    7373--          by - dneise.UNKNOWN (E5B-LABOR6)
    74 --          at - 15:27:50 04.02.2011
     74--          at - 13:26:28 14.02.2011
    7575--
    7676-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    171171   SIGNAL trigger_enable         : std_logic;
    172172   SIGNAL trigger_id             : std_logic_vector(47 DOWNTO 0);
    173    SIGNAL trigger_out            : std_logic;
     173   SIGNAL trigger_out            : std_logic                                    := '0';
    174174   SIGNAL wiz_ack                : std_logic;
    175175   SIGNAL wiz_busy               : std_logic;
     
    451451      c_trigger_enable  : OUT    std_logic                      := '0';
    452452      c_trigger_mult    : OUT    std_logic_vector (7 DOWNTO 0)  := (OTHERS => '1'); --subject TO changes
    453       --
     453      -- FAD configuration signals:
     454      ------------------------------------------------------------------------------
     455      -- start entire configuration chain
    454456      new_config        : OUT    std_logic                      := '0';
    455457      config_started    : IN     std_logic ;
     458      -- read/write configRAM
    456459      config_addr       : OUT    std_logic_vector (7 DOWNTO 0);
    457460      config_data       : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z');
    458461      config_wr_en      : OUT    std_logic                      := '0';
    459462      config_rd_en      : OUT    std_logic                      := '0';
    460       -- --
    461463      config_rw_ack     : IN     std_logic ;
    462       -- --
    463464      config_rw_ready   : IN     std_logic ;
    464       -- --
    465465      config_busy       : IN     std_logic ;
     466      ------------------------------------------------------------------------------
     467     
     468      -- MAC/IP calculation signals:
     469      ------------------------------------------------------------------------------
    466470      MAC_jumper        : IN     std_logic_vector (1 DOWNTO 0);
    467471      BoardID           : IN     std_logic_vector (3 DOWNTO 0);
    468472      CrateID           : IN     std_logic_vector (1 DOWNTO 0);
     473      ------------------------------------------------------------------------------
     474     
     475      -- user controllable enable signals
     476      ------------------------------------------------------------------------------
     477      trigger_enable    : OUT    std_logic                      := '0';             -- default triggers are NOT accepted
    469478      denable           : OUT    std_logic                      := '0';             -- default domino wave off
    470479      dwrite_enable     : OUT    std_logic                      := '0';             -- default DWRITE low.
    471480      sclk_enable       : OUT    std_logic                      := '1';             -- default DWRITE HIGH.
     481      srclk_enable      : OUT    std_logic                      := '1';             -- default SRCLK on.
     482      ------------------------------------------------------------------------------
     483     
     484      -- ADC CLK generator, is able to shift phase with respect to X_50M
     485      -- these signals control the behavior of the digital clock manager (DCM)
     486      ------------------------------------------------------------------------------
    472487      ps_direction      : OUT    std_logic                      := '1';             -- default phase shift upwards
    473488      ps_do_phase_shift : OUT    std_logic                      := '0';             --pulse this TO phase shift once
    474489      ps_reset          : OUT    std_logic                      := '0';             -- pulse this TO reset the variable phase shift
    475       srclk_enable      : OUT    std_logic                      := '1';             -- default SRCLK on.
    476       trigger_enable    : OUT    std_logic                      := '0';             -- default triggers are NOT accepted
     490      ------------------------------------------------------------------------------
     491     
     492      -- signals used to control FAD LED bahavior:
     493      -- one of the three LEDs is used for com-status info
     494      ------------------------------------------------------------------------------
    477495      socks_waiting     : OUT    std_logic ;
    478496      socks_connected   : OUT    std_logic
     497      ------------------------------------------------------------------------------
    479498   );
    480499   END COMPONENT;
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd

    r10072 r10155  
    5151      wiz_write_end : OUT std_logic := '0';
    5252      wiz_busy : IN std_logic;
    53           wiz_ack : IN std_logic;
     53            wiz_ack : IN std_logic;
    5454      ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0')
    5555   );
     
    134134              roi_max_array (channel_id) <= temp_roi;
    135135            end if;
    136             channel_size (channel_id) <= channel_size (channel_id) + temp_roi + 3;
     136            channel_size (channel_id) <= channel_size (channel_id) + temp_roi + CHANNEL_HEADER_SIZE;
    137137            drs_id <= drs_id + 1;
    138138            state_mm <= MAX_ROI;
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd

    r10154 r10155  
    3535                shifting : OUT std_logic := '0';
    3636                ready : OUT std_logic := '0';
     37               
    3738                offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0')
    3839               
     
    9394
    9495        -- MAIN FSM
    95         FSM: process(state, PSDONE, LOCKED, shift_phase, direction, local_direction)
     96        FSM: process(CLK)
    9697        begin
    9798       
     
    144145                        end if;
    145146                       
    146                         if (reset_dcm_sr = "01") then
     147                        if (reset_dcm_sr = "01") then   
    147148                                state <= RESET_STATE;
    148149                        end if;
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd

    r10129 r10155  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 16:13:08 03.02.2011
     5--          at - 13:10:37 12.02.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    3838-- Created:
    3939--          by - dneise.UNKNOWN (E5B-LABOR6)
    40 --          at - 16:13:08 03.02.2011
     40--          at - 13:10:37 12.02.2011
    4141--
    4242-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/trigger_counter_beha.vhd

    r9912 r10155  
    1616entity trigger_counter is
    1717  port(
    18     trigger_id : out std_logic_vector(47 downto 0);
     18    trigger_id : out std_logic_vector(31 downto 0);
    1919    trigger : in std_logic;
    2020    clk : in std_logic
     
    2929begin
    3030 
    31   trigger_id <= X"AA55" & conv_std_logic_vector(temp_id, 32);
     31  trigger_id <= conv_std_logic_vector(temp_id, 32);
    3232 
    3333  trigger_incr_proc: process(clk)
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/clock_generator_var_ps_struct.xrf

    r10129 r10155  
    4343DESIGN clock_generator_var_ps
    4444VIEW struct.bd
    45 NO_GRAPHIC 43
    46 DESIGN clock_generator_var_ps
    47 VIEW struct.bd
    48 GRAPHIC 0,0 46 2
    49 DESIGN clock_generator_var_ps
    50 VIEW struct.bd
    51 GRAPHIC 524,0 51 0
    52 DESIGN clock_generator_var_ps
    53 VIEW struct.bd
    54 GRAPHIC 600,0 52 0
    55 DESIGN clock_generator_var_ps
    56 VIEW struct.bd
    57 GRAPHIC 530,0 53 0
    58 DESIGN clock_generator_var_ps
    59 VIEW struct.bd
    60 GRAPHIC 586,0 54 0
    61 DESIGN clock_generator_var_ps
    62 VIEW struct.bd
    63 GRAPHIC 544,0 55 0
    64 DESIGN clock_generator_var_ps
    65 VIEW struct.bd
    66 GRAPHIC 558,0 56 0
    67 DESIGN clock_generator_var_ps
    68 VIEW struct.bd
    69 NO_GRAPHIC 57
    70 DESIGN clock_generator_var_ps
    71 VIEW struct.bd
    72 GRAPHIC 229,0 59 0
    73 DESIGN clock_generator_var_ps
    74 VIEW struct.bd
    75 NO_GRAPHIC 61
     45NO_GRAPHIC 45
     46DESIGN clock_generator_var_ps
     47VIEW struct.bd
     48GRAPHIC 0,0 48 2
     49DESIGN clock_generator_var_ps
     50VIEW struct.bd
     51GRAPHIC 524,0 53 0
     52DESIGN clock_generator_var_ps
     53VIEW struct.bd
     54GRAPHIC 600,0 54 0
     55DESIGN clock_generator_var_ps
     56VIEW struct.bd
     57GRAPHIC 530,0 55 0
     58DESIGN clock_generator_var_ps
     59VIEW struct.bd
     60GRAPHIC 586,0 56 0
     61DESIGN clock_generator_var_ps
     62VIEW struct.bd
     63GRAPHIC 544,0 57 0
     64DESIGN clock_generator_var_ps
     65VIEW struct.bd
     66GRAPHIC 558,0 58 0
     67DESIGN clock_generator_var_ps
     68VIEW struct.bd
     69GRAPHIC 1979,0 59 0
     70DESIGN clock_generator_var_ps
     71VIEW struct.bd
     72NO_GRAPHIC 60
     73DESIGN clock_generator_var_ps
     74VIEW struct.bd
     75GRAPHIC 229,0 62 0
     76DESIGN clock_generator_var_ps
     77VIEW struct.bd
     78NO_GRAPHIC 64
    7679LIBRARY FACT_FAD_lib
    7780DESIGN dcm_50_to_25
    7881VIEW @b@e@h@a@v@i@o@r@a@l
    79 GRAPHIC 403,0 63 0
    80 DESIGN clock_generator_var_ps
    81 VIEW struct.bd
    82 NO_GRAPHIC 69
    83 DESIGN clock_generator_var_ps
    84 VIEW struct.bd
    85 GRAPHIC 354,0 71 0
    86 DESIGN clock_generator_var_ps
    87 VIEW struct.bd
    88 NO_GRAPHIC 75
    89 DESIGN clock_generator_var_ps
    90 VIEW struct.bd
    91 GRAPHIC 514,0 77 0
    92 DESIGN clock_generator_var_ps
    93 VIEW struct.bd
    94 NO_GRAPHIC 87
    95 DESIGN clock_generator_var_ps
    96 VIEW struct.bd
    97 GRAPHIC 826,0 89 0
    98 DESIGN phase_shifter
    99 VIEW first_behave
    100 GRAPHIC 48,0 91 0
    101 DESIGN phase_shifter
    102 VIEW first_behave
    103 GRAPHIC 281,0 92 0
    104 DESIGN phase_shifter
    105 VIEW first_behave
    106 GRAPHIC 53,0 93 0
    107 DESIGN phase_shifter
    108 VIEW first_behave
    109 GRAPHIC 58,0 95 0
    110 DESIGN phase_shifter
    111 VIEW first_behave
    112 GRAPHIC 63,0 96 0
    113 DESIGN phase_shifter
    114 VIEW first_behave
    115 GRAPHIC 68,0 97 0
    116 DESIGN phase_shifter
    117 VIEW first_behave
    118 GRAPHIC 73,0 98 0
    119 DESIGN phase_shifter
    120 VIEW first_behave
    121 GRAPHIC 83,0 99 0
    122 DESIGN phase_shifter
    123 VIEW first_behave
    124 GRAPHIC 88,0 101 0
    125 DESIGN phase_shifter
    126 VIEW first_behave
    127 GRAPHIC 93,0 102 0
    128 DESIGN phase_shifter
    129 VIEW first_behave
    130 GRAPHIC 98,0 104 0
    131 DESIGN phase_shifter
    132 VIEW first_behave
    133 GRAPHIC 103,0 105 0
    134 DESIGN phase_shifter
    135 VIEW first_behave
    136 GRAPHIC 108,0 106 0
     82GRAPHIC 403,0 66 0
     83DESIGN clock_generator_var_ps
     84VIEW struct.bd
     85NO_GRAPHIC 72
     86DESIGN clock_generator_var_ps
     87VIEW struct.bd
     88GRAPHIC 354,0 74 0
     89DESIGN clock_generator_var_ps
     90VIEW struct.bd
     91NO_GRAPHIC 78
     92DESIGN clock_generator_var_ps
     93VIEW struct.bd
     94GRAPHIC 514,0 80 0
     95DESIGN clock_generator_var_ps
     96VIEW struct.bd
     97NO_GRAPHIC 90
     98DESIGN clock_generator_var_ps
     99VIEW struct.bd
     100GRAPHIC 826,0 92 0
     101DESIGN phase_shifter
     102VIEW first_behave
     103GRAPHIC 48,0 94 0
     104DESIGN phase_shifter
     105VIEW first_behave
     106GRAPHIC 281,0 95 0
     107DESIGN phase_shifter
     108VIEW first_behave
     109GRAPHIC 53,0 96 0
     110DESIGN phase_shifter
     111VIEW first_behave
     112GRAPHIC 58,0 98 0
     113DESIGN phase_shifter
     114VIEW first_behave
     115GRAPHIC 63,0 99 0
     116DESIGN phase_shifter
     117VIEW first_behave
     118GRAPHIC 68,0 100 0
     119DESIGN phase_shifter
     120VIEW first_behave
     121GRAPHIC 73,0 101 0
     122DESIGN phase_shifter
     123VIEW first_behave
     124GRAPHIC 83,0 102 0
     125DESIGN phase_shifter
     126VIEW first_behave
     127GRAPHIC 88,0 104 0
     128DESIGN phase_shifter
     129VIEW first_behave
     130GRAPHIC 362,0 105 0
     131DESIGN phase_shifter
     132VIEW first_behave
     133GRAPHIC 93,0 106 0
     134DESIGN phase_shifter
     135VIEW first_behave
     136GRAPHIC 98,0 108 0
     137DESIGN phase_shifter
     138VIEW first_behave
     139GRAPHIC 103,0 109 0
    137140LIBRARY FACT_FAD_lib
    138141DESIGN clock_generator_var_ps
    139142VIEW struct.bd
    140 NO_GRAPHIC 109
    141 DESIGN clock_generator_var_ps
    142 VIEW struct.bd
    143 GRAPHIC 403,0 112 0
    144 DESIGN clock_generator_var_ps
    145 VIEW struct.bd
    146 GRAPHIC 354,0 113 0
    147 DESIGN clock_generator_var_ps
    148 VIEW struct.bd
    149 GRAPHIC 514,0 114 0
    150 DESIGN clock_generator_var_ps
    151 VIEW struct.bd
    152 GRAPHIC 826,0 115 0
    153 DESIGN clock_generator_var_ps
    154 VIEW struct.bd
    155 NO_GRAPHIC 118
    156 DESIGN clock_generator_var_ps
    157 VIEW struct.bd
    158 NO_GRAPHIC 120
    159 DESIGN clock_generator_var_ps
    160 VIEW struct.bd
    161 GRAPHIC 403,0 122 0
    162 DESIGN clock_generator_var_ps
    163 VIEW struct.bd
    164 GRAPHIC 163,0 124 0
    165 DESIGN clock_generator_var_ps
    166 VIEW struct.bd
    167 GRAPHIC 209,0 125 0
    168 DESIGN clock_generator_var_ps
    169 VIEW struct.bd
    170 GRAPHIC 191,0 127 0
    171 DESIGN clock_generator_var_ps
    172 VIEW struct.bd
    173 GRAPHIC 354,0 129 0
    174 DESIGN clock_generator_var_ps
    175 VIEW struct.bd
    176 GRAPHIC 229,0 131 0
    177 DESIGN clock_generator_var_ps
    178 VIEW struct.bd
    179 GRAPHIC 526,0 132 0
    180 DESIGN clock_generator_var_ps
    181 VIEW struct.bd
    182 GRAPHIC 514,0 134 0
    183 DESIGN clock_generator_var_ps
    184 VIEW struct.bd
    185 GRAPHIC 526,0 136 0
    186 DESIGN clock_generator_var_ps
    187 VIEW struct.bd
    188 GRAPHIC 532,0 137 0
    189 DESIGN clock_generator_var_ps
    190 VIEW struct.bd
    191 GRAPHIC 546,0 138 0
    192 DESIGN clock_generator_var_ps
    193 VIEW struct.bd
    194 GRAPHIC 841,0 139 0
    195 DESIGN clock_generator_var_ps
    196 VIEW struct.bd
    197 GRAPHIC 1493,0 140 0
    198 DESIGN clock_generator_var_ps
    199 VIEW struct.bd
    200 GRAPHIC 1254,0 141 0
    201 DESIGN clock_generator_var_ps
    202 VIEW struct.bd
    203 GRAPHIC 602,0 142 0
    204 DESIGN clock_generator_var_ps
    205 VIEW struct.bd
    206 GRAPHIC 588,0 143 0
    207 DESIGN clock_generator_var_ps
    208 VIEW struct.bd
    209 GRAPHIC 826,0 145 0
    210 DESIGN clock_generator_var_ps
    211 VIEW struct.bd
    212 GRAPHIC 1458,0 147 0
    213 DESIGN clock_generator_var_ps
    214 VIEW struct.bd
    215 GRAPHIC 1625,0 148 0
    216 DESIGN clock_generator_var_ps
    217 VIEW struct.bd
    218 GRAPHIC 532,0 149 0
    219 DESIGN clock_generator_var_ps
    220 VIEW struct.bd
    221 GRAPHIC 546,0 150 0
    222 DESIGN clock_generator_var_ps
    223 VIEW struct.bd
    224 GRAPHIC 841,0 151 0
    225 DESIGN clock_generator_var_ps
    226 VIEW struct.bd
    227 GRAPHIC 588,0 152 0
    228 DESIGN clock_generator_var_ps
    229 VIEW struct.bd
    230 GRAPHIC 602,0 153 0
    231 DESIGN clock_generator_var_ps
    232 VIEW struct.bd
    233 GRAPHIC 1272,0 154 0
    234 DESIGN clock_generator_var_ps
    235 VIEW struct.bd
    236 GRAPHIC 1286,0 155 0
    237 DESIGN clock_generator_var_ps
    238 VIEW struct.bd
    239 GRAPHIC 1609,0 158 0
    240 DESIGN clock_generator_var_ps
    241 VIEW struct.bd
    242 GRAPHIC 229,0 163 0
    243 DESIGN clock_generator_var_ps
    244 VIEW struct.bd
    245 NO_GRAPHIC 165
     143NO_GRAPHIC 112
     144DESIGN clock_generator_var_ps
     145VIEW struct.bd
     146GRAPHIC 403,0 115 0
     147DESIGN clock_generator_var_ps
     148VIEW struct.bd
     149GRAPHIC 354,0 116 0
     150DESIGN clock_generator_var_ps
     151VIEW struct.bd
     152GRAPHIC 514,0 117 0
     153DESIGN clock_generator_var_ps
     154VIEW struct.bd
     155GRAPHIC 826,0 118 0
     156DESIGN clock_generator_var_ps
     157VIEW struct.bd
     158NO_GRAPHIC 121
     159DESIGN clock_generator_var_ps
     160VIEW struct.bd
     161NO_GRAPHIC 123
     162DESIGN clock_generator_var_ps
     163VIEW struct.bd
     164GRAPHIC 403,0 125 0
     165DESIGN clock_generator_var_ps
     166VIEW struct.bd
     167GRAPHIC 163,0 127 0
     168DESIGN clock_generator_var_ps
     169VIEW struct.bd
     170GRAPHIC 209,0 128 0
     171DESIGN clock_generator_var_ps
     172VIEW struct.bd
     173GRAPHIC 191,0 130 0
     174DESIGN clock_generator_var_ps
     175VIEW struct.bd
     176GRAPHIC 354,0 132 0
     177DESIGN clock_generator_var_ps
     178VIEW struct.bd
     179GRAPHIC 229,0 134 0
     180DESIGN clock_generator_var_ps
     181VIEW struct.bd
     182GRAPHIC 526,0 135 0
     183DESIGN clock_generator_var_ps
     184VIEW struct.bd
     185GRAPHIC 514,0 137 0
     186DESIGN clock_generator_var_ps
     187VIEW struct.bd
     188GRAPHIC 526,0 139 0
     189DESIGN clock_generator_var_ps
     190VIEW struct.bd
     191GRAPHIC 532,0 140 0
     192DESIGN clock_generator_var_ps
     193VIEW struct.bd
     194GRAPHIC 546,0 141 0
     195DESIGN clock_generator_var_ps
     196VIEW struct.bd
     197GRAPHIC 841,0 142 0
     198DESIGN clock_generator_var_ps
     199VIEW struct.bd
     200GRAPHIC 1981,0 143 0
     201DESIGN clock_generator_var_ps
     202VIEW struct.bd
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     204DESIGN clock_generator_var_ps
     205VIEW struct.bd
     206GRAPHIC 602,0 145 0
     207DESIGN clock_generator_var_ps
     208VIEW struct.bd
     209GRAPHIC 588,0 146 0
     210DESIGN clock_generator_var_ps
     211VIEW struct.bd
     212GRAPHIC 826,0 148 0
     213DESIGN clock_generator_var_ps
     214VIEW struct.bd
     215GRAPHIC 1458,0 150 0
     216DESIGN clock_generator_var_ps
     217VIEW struct.bd
     218GRAPHIC 1981,0 151 0
     219DESIGN clock_generator_var_ps
     220VIEW struct.bd
     221GRAPHIC 532,0 152 0
     222DESIGN clock_generator_var_ps
     223VIEW struct.bd
     224GRAPHIC 546,0 153 0
     225DESIGN clock_generator_var_ps
     226VIEW struct.bd
     227GRAPHIC 841,0 154 0
     228DESIGN clock_generator_var_ps
     229VIEW struct.bd
     230GRAPHIC 588,0 155 0
     231DESIGN clock_generator_var_ps
     232VIEW struct.bd
     233GRAPHIC 602,0 156 0
     234DESIGN clock_generator_var_ps
     235VIEW struct.bd
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     237DESIGN clock_generator_var_ps
     238VIEW struct.bd
     239GRAPHIC 1286,0 158 0
     240DESIGN clock_generator_var_ps
     241VIEW struct.bd
     242GRAPHIC 1493,0 159 0
     243DESIGN clock_generator_var_ps
     244VIEW struct.bd
     245GRAPHIC 1609,0 162 0
     246DESIGN clock_generator_var_ps
     247VIEW struct.bd
     248GRAPHIC 229,0 166 0
     249DESIGN clock_generator_var_ps
     250VIEW struct.bd
     251NO_GRAPHIC 168
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf

    r10129 r10155  
    367367DESIGN @f@a@d_main
    368368VIEW struct.bd
    369 GRAPHIC 10449,0 172 0
     369GRAPHIC 15492,0 172 0
    370370DESIGN @f@a@d_main
    371371VIEW struct.bd
     
    884884DESIGN w5300_modul
    885885VIEW @behavioral
    886 GRAPHIC 566,0 454 0
    887 DESIGN w5300_modul
    888 VIEW @behavioral
    889 GRAPHIC 551,0 455 0
    890 DESIGN w5300_modul
    891 VIEW @behavioral
    892 GRAPHIC 561,0 456 0
    893 DESIGN w5300_modul
    894 VIEW @behavioral
    895 GRAPHIC 571,0 457 0
    896 DESIGN w5300_modul
    897 VIEW @behavioral
    898 GRAPHIC 640,0 458 0
    899 DESIGN w5300_modul
    900 VIEW @behavioral
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    903 VIEW @behavioral
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    909909VIEW @behavioral
     
    911911DESIGN w5300_modul
    912912VIEW @behavioral
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    947947LIBRARY FACT_FAD_lib
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     1362DESIGN @f@a@d_main
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     1365DESIGN @f@a@d_main
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     1368DESIGN @f@a@d_main
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     1371DESIGN @f@a@d_main
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     1374DESIGN @f@a@d_main
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     1377DESIGN @f@a@d_main
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     1380DESIGN @f@a@d_main
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     1383DESIGN @f@a@d_main
     1384VIEW struct.bd
     1385GRAPHIC 12707,0 695 0
     1386DESIGN @f@a@d_main
     1387VIEW struct.bd
     1388GRAPHIC 10707,0 696 0
     1389DESIGN @f@a@d_main
     1390VIEW struct.bd
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     1392DESIGN @f@a@d_main
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     1395DESIGN @f@a@d_main
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     1398DESIGN @f@a@d_main
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     1401DESIGN @f@a@d_main
     1402VIEW struct.bd
     1403GRAPHIC 15379,0 706 0
     1404DESIGN @f@a@d_main
     1405VIEW struct.bd
     1406GRAPHIC 2588,0 707 0
     1407DESIGN @f@a@d_main
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     1410DESIGN @f@a@d_main
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     1413DESIGN @f@a@d_main
     1414VIEW struct.bd
     1415GRAPHIC 5168,0 710 0
     1416DESIGN @f@a@d_main
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     1419DESIGN @f@a@d_main
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     1422DESIGN @f@a@d_main
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     1424GRAPHIC 6018,0 713 0
     1425DESIGN @f@a@d_main
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     1428DESIGN @f@a@d_main
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     1431DESIGN @f@a@d_main
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     1434DESIGN @f@a@d_main
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     1437DESIGN @f@a@d_main
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     1440DESIGN @f@a@d_main
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     1443DESIGN @f@a@d_main
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     1446DESIGN @f@a@d_main
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     1449DESIGN @f@a@d_main
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     1452DESIGN @f@a@d_main
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     1455DESIGN @f@a@d_main
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     1458DESIGN @f@a@d_main
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     1461DESIGN @f@a@d_main
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     1464DESIGN @f@a@d_main
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     1467DESIGN @f@a@d_main
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     1470DESIGN @f@a@d_main
     1471VIEW struct.bd
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     1473DESIGN @f@a@d_main
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     1476DESIGN @f@a@d_main
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     1479DESIGN @f@a@d_main
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     1482DESIGN @f@a@d_main
     1483VIEW struct.bd
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     1485DESIGN @f@a@d_main
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     1488DESIGN @f@a@d_main
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     1491DESIGN @f@a@d_main
     1492VIEW struct.bd
     1493GRAPHIC 5474,0 738 0
     1494DESIGN @f@a@d_main
     1495VIEW struct.bd
     1496GRAPHIC 5821,0 739 0
     1497DESIGN @f@a@d_main
     1498VIEW struct.bd
     1499GRAPHIC 1768,0 741 0
     1500DESIGN @f@a@d_main
     1501VIEW struct.bd
     1502GRAPHIC 1983,0 743 0
     1503DESIGN @f@a@d_main
     1504VIEW struct.bd
     1505GRAPHIC 15498,0 744 0
     1506DESIGN @f@a@d_main
     1507VIEW struct.bd
     1508GRAPHIC 6276,0 745 0
     1509DESIGN @f@a@d_main
     1510VIEW struct.bd
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     1512DESIGN @f@a@d_main
     1513VIEW struct.bd
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     1515DESIGN @f@a@d_main
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     1517GRAPHIC 12643,0 750 0
     1518DESIGN @f@a@d_main
     1519VIEW struct.bd
     1520GRAPHIC 15494,0 751 0
     1521DESIGN @f@a@d_main
     1522VIEW struct.bd
     1523GRAPHIC 6540,0 752 0
     1524DESIGN @f@a@d_main
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     1527DESIGN @f@a@d_main
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     1530DESIGN @f@a@d_main
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     1533DESIGN @f@a@d_main
     1534VIEW struct.bd
     1535GRAPHIC 1613,0 757 1
     1536DESIGN @f@a@d_main
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     1539DESIGN @f@a@d_main
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     1542DESIGN @f@a@d_main
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     1545DESIGN @f@a@d_main
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     1548DESIGN @f@a@d_main
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     1551DESIGN @f@a@d_main
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     1554DESIGN @f@a@d_main
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     1557DESIGN @f@a@d_main
     1558VIEW struct.bd
     1559GRAPHIC 424,0 768 0
     1560DESIGN @f@a@d_main
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     1563DESIGN @f@a@d_main
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     1566DESIGN @f@a@d_main
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     1569DESIGN @f@a@d_main
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     1572DESIGN @f@a@d_main
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     1575DESIGN @f@a@d_main
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     1578DESIGN @f@a@d_main
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     1581DESIGN @f@a@d_main
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     1584DESIGN @f@a@d_main
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     1587DESIGN @f@a@d_main
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     1590DESIGN @f@a@d_main
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     1593DESIGN @f@a@d_main
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     1596DESIGN @f@a@d_main
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     1599DESIGN @f@a@d_main
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     1611DESIGN @f@a@d_main
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     1614DESIGN @f@a@d_main
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     1617DESIGN @f@a@d_main
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     1620DESIGN @f@a@d_main
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     1629DESIGN @f@a@d_main
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     1632DESIGN @f@a@d_main
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     1635DESIGN @f@a@d_main
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  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd

    r10138 r10155  
    2626library "IEEE"
    2727unitName "std_logic_signed"
     28)
     29(DmPackageRef
     30library "UNISIM"
     31unitName "VComponents"
    2832)
    2933]
     
    278282uid 15058,0
    279283)
     284(Instance
     285name "U_0"
     286duLibraryName "FACT_FAD_lib"
     287duName "dna_gen"
     288elements [
     289]
     290mwi 0
     291uid 15728,0
     292)
    280293]
    281294libraryRefs [
     
    333346(vvPair
    334347variable "date"
    335 value "08.02.2011"
     348value "15.02.2011"
    336349)
    337350(vvPair
     
    345358(vvPair
    346359variable "dd"
    347 value "08"
     360value "15"
    348361)
    349362(vvPair
     
    485498(vvPair
    486499variable "time"
    487 value "11:06:22"
     500value "09:27:14"
    488501)
    489502(vvPair
     
    13631376preAdd 0
    13641377posAdd 0
    1365 o 24
     1378o 25
    13661379suid 9,0
    13671380)
     
    13691382)
    13701383*29 (CptPort
    1371 uid 1388,0
    1372 ps "OnEdgeStrategy"
    1373 shape (Triangle
    1374 uid 1389,0
    1375 ro 90
    1376 va (VaSet
    1377 vasetType 1
    1378 fg "0,65535,0"
    1379 )
    1380 xt "-21750,69625,-21000,70375"
    1381 )
    1382 tg (CPTG
    1383 uid 1390,0
    1384 ps "CptPortTextPlaceStrategy"
    1385 stg "VerticalLayoutStrategy"
    1386 f (Text
    1387 uid 1391,0
    1388 va (VaSet
    1389 )
    1390 xt "-20000,69500,-13200,70500"
    1391 st "trigger_id : (47:0)"
    1392 blo "-20000,70300"
    1393 )
    1394 )
    1395 thePort (LogicalPort
    1396 decl (Decl
    1397 n "trigger_id"
    1398 t "std_logic_vector"
    1399 b "(47 downto 0)"
    1400 preAdd 0
    1401 posAdd 0
    1402 o 26
    1403 suid 10,0
    1404 )
    1405 )
    1406 )
    1407 *30 (CptPort
    14081384uid 1392,0
    14091385ps "OnEdgeStrategy"
     
    14361412preAdd 0
    14371413posAdd 0
    1438 o 27
     1414o 28
    14391415suid 11,0
    14401416)
    14411417)
    14421418)
    1443 *31 (CptPort
     1419*30 (CptPort
    14441420uid 1676,0
    14451421ps "OnEdgeStrategy"
     
    14711447t "std_logic_vector"
    14721448b "(1 downto 0)"
    1473 o 25
     1449o 26
    14741450suid 12,0
    14751451)
    14761452)
    14771453)
    1478 *32 (CptPort
     1454*31 (CptPort
    14791455uid 2562,0
    14801456ps "OnEdgeStrategy"
     
    15111487)
    15121488)
    1513 *33 (CptPort
     1489*32 (CptPort
    15141490uid 2566,0
    15151491ps "OnEdgeStrategy"
     
    15491525)
    15501526)
    1551 *34 (CptPort
     1527*33 (CptPort
    15521528uid 2570,0
    15531529ps "OnEdgeStrategy"
     
    15841560)
    15851561)
    1586 *35 (CptPort
     1562*34 (CptPort
    15871563uid 2614,0
    15881564ps "OnEdgeStrategy"
     
    16191595)
    16201596)
    1621 *36 (CptPort
     1597*35 (CptPort
    16221598uid 2624,0
    16231599ps "OnEdgeStrategy"
     
    16551631)
    16561632)
    1657 *37 (CptPort
     1633*36 (CptPort
    16581634uid 2760,0
    16591635ps "OnEdgeStrategy"
     
    16851661n "adc_oeb"
    16861662t "std_logic"
    1687 o 31
     1663o 32
    16881664suid 23,0
    16891665i "'1'"
     
    16911667)
    16921668)
    1693 *38 (CptPort
     1669*37 (CptPort
    16941670uid 2764,0
    16951671ps "OnEdgeStrategy"
     
    17211697t "std_logic_vector"
    17221698b "(3 downto 0)"
    1723 o 33
     1699o 34
    17241700suid 24,0
    17251701)
    17261702)
    17271703)
    1728 *39 (CptPort
     1704*38 (CptPort
    17291705uid 3918,0
    17301706ps "OnEdgeStrategy"
     
    17581734b "(3 downto 0)"
    17591735posAdd 0
    1760 o 34
     1736o 35
    17611737suid 25,0
    17621738i "(others => '0')"
     
    17641740)
    17651741)
    1766 *40 (CptPort
     1742*39 (CptPort
    17671743uid 3922,0
    17681744ps "OnEdgeStrategy"
     
    17971773preAdd 0
    17981774posAdd 0
    1799 o 37
     1775o 38
    18001776suid 26,0
    18011777i "'0'"
     
    18031779)
    18041780)
    1805 *41 (CptPort
     1781*40 (CptPort
    18061782uid 3930,0
    18071783ps "OnEdgeStrategy"
     
    18351811prec "-- --"
    18361812preAdd 0
    1837 o 38
     1813o 39
    18381814suid 33,0
    18391815i "'0'"
     
    18411817)
    18421818)
    1843 *42 (CptPort
     1819*41 (CptPort
    18441820uid 3934,0
    18451821ps "OnEdgeStrategy"
     
    18701846n "drs_read_s_cell_ready"
    18711847t "std_logic"
    1872 o 43
     1848o 44
    18731849suid 34,0
    18741850)
    18751851)
    18761852)
    1877 *43 (CptPort
     1853*42 (CptPort
    18781854uid 3938,0
    18791855ps "OnEdgeStrategy"
     
    19041880n "drs_s_cell_array"
    19051881t "drs_s_cell_array_type"
    1906 o 44
     1882o 45
    19071883suid 35,0
    19081884)
    19091885)
    19101886)
    1911 *44 (CptPort
     1887*43 (CptPort
    19121888uid 4246,0
    19131889ps "OnEdgeStrategy"
     
    19381914n "adc_data_array"
    19391915t "adc_data_array_type"
    1940 o 30
     1916o 31
    19411917suid 37,0
    19421918)
    19431919)
    19441920)
    1945 *45 (CptPort
     1921*44 (CptPort
    19461922uid 5174,0
    19471923ps "OnEdgeStrategy"
     
    19781954)
    19791955)
    1980 *46 (CptPort
     1956*45 (CptPort
    19811957uid 5178,0
    19821958ps "OnEdgeStrategy"
     
    20181994)
    20191995)
    2020 *47 (CptPort
     1996*46 (CptPort
    20211997uid 5392,0
    20221998ps "OnEdgeStrategy"
     
    20532029)
    20542030)
    2055 *48 (CptPort
     2031*47 (CptPort
    20562032uid 5396,0
    20572033ps "OnEdgeStrategy"
     
    20882064)
    20892065)
    2090 *49 (CptPort
     2066*48 (CptPort
    20912067uid 5464,0
    20922068ps "OnEdgeStrategy"
     
    21232099)
    21242100)
    2125 *50 (CptPort
     2101*49 (CptPort
    21262102uid 5468,0
    21272103ps "OnEdgeStrategy"
     
    21582134)
    21592135)
    2160 *51 (CptPort
     2136*50 (CptPort
    21612137uid 5735,0
    21622138ps "OnEdgeStrategy"
     
    21982174)
    21992175)
    2200 *52 (CptPort
     2176*51 (CptPort
    22012177uid 5739,0
    22022178ps "OnEdgeStrategy"
     
    22372213)
    22382214)
    2239 *53 (CptPort
     2215*52 (CptPort
    22402216uid 5916,0
    22412217ps "OnEdgeStrategy"
     
    22682244n "config_started"
    22692245t "std_logic"
    2270 o 29
     2246o 30
    22712247suid 48,0
    22722248i "'0'"
     
    22742250)
    22752251)
    2276 *54 (CptPort
     2252*53 (CptPort
    22772253uid 5920,0
    22782254ps "OnEdgeStrategy"
     
    23062282prec "--      s_trigger      : in std_logic;"
    23072283preAdd 0
    2308 o 28
     2284o 29
    23092285suid 49,0
    23102286)
    23112287)
    23122288)
    2313 *55 (CptPort
     2289*54 (CptPort
    23142290uid 5974,0
    23152291ps "OnEdgeStrategy"
     
    23462322)
    23472323)
    2348 *56 (CptPort
     2324*55 (CptPort
    23492325uid 5978,0
    23502326ps "OnEdgeStrategy"
     
    23812357)
    23822358)
    2383 *57 (CptPort
     2359*56 (CptPort
    23842360uid 5982,0
    23852361ps "OnEdgeStrategy"
     
    24162392)
    24172393)
    2418 *58 (CptPort
     2394*57 (CptPort
    24192395uid 6060,0
    24202396ps "OnEdgeStrategy"
     
    24512427)
    24522428)
    2453 *59 (CptPort
     2429*58 (CptPort
    24542430uid 9000,0
    24552431ps "OnEdgeStrategy"
     
    24812457n "adc_clk_en"
    24822458t "std_logic"
    2483 o 32
     2459o 33
    24842460suid 54,0
    24852461i "'0'"
     
    24872463)
    24882464)
    2489 *60 (CptPort
     2465*59 (CptPort
    24902466uid 10244,0
    24912467ps "OnEdgeStrategy"
     
    25182494t "std_logic_vector"
    25192495b "(7 downto 0)"
    2520 o 41
     2496o 42
    25212497suid 56,0
    25222498i "(others => '0')"
     
    25242500)
    25252501)
    2526 *61 (CptPort
     2502*60 (CptPort
    25272503uid 10248,0
    25282504ps "OnEdgeStrategy"
     
    25542530n "drs_srin_write_8b"
    25552531t "std_logic"
    2556 o 39
     2532o 40
    25572533suid 57,0
    25582534i "'0'"
     
    25602536)
    25612537)
    2562 *62 (CptPort
     2538*61 (CptPort
    25632539uid 10252,0
    25642540ps "OnEdgeStrategy"
     
    25892565n "drs_srin_write_ack"
    25902566t "std_logic"
    2591 o 40
     2567o 41
    25922568suid 58,0
    25932569)
    25942570)
    25952571)
    2596 *63 (CptPort
     2572*62 (CptPort
    25972573uid 10256,0
    25982574ps "OnEdgeStrategy"
     
    26232599n "drs_srin_write_ready"
    26242600t "std_logic"
    2625 o 42
     2601o 43
    26262602suid 59,0
    26272603)
    26282604)
    26292605)
    2630 *64 (CptPort
     2606*63 (CptPort
    26312607uid 10260,0
    26322608ps "OnEdgeStrategy"
     
    26662642)
    26672643)
    2668 *65 (CptPort
     2644*64 (CptPort
    26692645uid 11385,0
    26702646ps "OnEdgeStrategy"
     
    26972673n "drs_readout_started"
    26982674t "std_logic"
    2699 o 45
     2675o 46
    27002676suid 61,0
    27012677i "'0'"
     
    27032679)
    27042680)
    2705 *66 (CptPort
     2681*65 (CptPort
    27062682uid 12597,0
    27072683ps "OnEdgeStrategy"
     
    27372713preAdd 0
    27382714posAdd 0
    2739 o 35
     2715o 36
    27402716suid 62,0
    27412717i "'0'"
     
    27432719)
    27442720)
    2745 *67 (CptPort
     2721*66 (CptPort
    27462722uid 12601,0
    27472723ps "OnEdgeStrategy"
     
    27722748n "drs_readout_ready_ack"
    27732749t "std_logic"
    2774 o 36
     2750o 37
    27752751suid 63,0
     2752)
     2753)
     2754)
     2755*67 (CptPort
     2756uid 15740,0
     2757ps "OnEdgeStrategy"
     2758shape (Triangle
     2759uid 15741,0
     2760ro 90
     2761va (VaSet
     2762vasetType 1
     2763fg "0,65535,0"
     2764)
     2765xt "-21750,69625,-21000,70375"
     2766)
     2767tg (CPTG
     2768uid 15742,0
     2769ps "CptPortTextPlaceStrategy"
     2770stg "VerticalLayoutStrategy"
     2771f (Text
     2772uid 15743,0
     2773va (VaSet
     2774)
     2775xt "-20000,69500,-10200,70500"
     2776st "fad_event_counter : (31:0)"
     2777blo "-20000,70300"
     2778)
     2779)
     2780thePort (LogicalPort
     2781decl (Decl
     2782n "fad_event_counter"
     2783t "std_logic_vector"
     2784b "(31 downto 0)"
     2785o 27
     2786suid 65,0
     2787)
     2788)
     2789)
     2790*68 (CptPort
     2791uid 15744,0
     2792ps "OnEdgeStrategy"
     2793shape (Triangle
     2794uid 15745,0
     2795ro 90
     2796va (VaSet
     2797vasetType 1
     2798fg "0,65535,0"
     2799)
     2800xt "-21750,95625,-21000,96375"
     2801)
     2802tg (CPTG
     2803uid 15746,0
     2804ps "CptPortTextPlaceStrategy"
     2805stg "VerticalLayoutStrategy"
     2806f (Text
     2807uid 15747,0
     2808va (VaSet
     2809)
     2810xt "-20000,95500,-14500,96500"
     2811st "pll_lock : (3:0)"
     2812blo "-20000,96300"
     2813)
     2814)
     2815thePort (LogicalPort
     2816decl (Decl
     2817n "pll_lock"
     2818t "std_logic_vector"
     2819b "( 3 downto 0)"
     2820o 24
     2821suid 64,0
    27762822)
    27772823)
     
    27942840stg "VerticalLayoutStrategy"
    27952841textVec [
    2796 *68 (Text
     2842*69 (Text
    27972843uid 1402,0
    27982844va (VaSet
     
    28042850tm "BdLibraryNameMgr"
    28052851)
    2806 *69 (Text
     2852*70 (Text
    28072853uid 1403,0
    28082854va (VaSet
     
    28142860tm "CptNameMgr"
    28152861)
    2816 *70 (Text
     2862*71 (Text
    28172863uid 1404,0
    28182864va (VaSet
     
    28672913archFileType "UNKNOWN"
    28682914)
    2869 *71 (Net
     2915*72 (Net
    28702916uid 1409,0
    28712917decl (Decl
     
    28862932)
    28872933)
    2888 *72 (Net
     2934*73 (Net
    28892935uid 1423,0
    28902936decl (Decl
     
    29062952)
    29072953)
    2908 *73 (PortIoIn
     2954*74 (PortIoIn
    29092955uid 1443,0
    29102956shape (CompositeShape
     
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    29522998)
    2953 *74 (SaComponent
     2999*75 (SaComponent
    29543000uid 1606,0
    29553001optionalChildren [
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     3002*76 (CptPort
    29573003uid 1542,0
    29583004ps "OnEdgeStrategy"
     
    29903036)
    29913037)
    2992 *76 (CptPort
     3038*77 (CptPort
    29933039uid 1546,0
    29943040ps "OnEdgeStrategy"
     
    30293075)
    30303076)
    3031 *77 (CptPort
     3077*78 (CptPort
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    30333079ps "OnEdgeStrategy"
     
    30683114)
    30693115)
    3070 *78 (CptPort
     3116*79 (CptPort
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    30723118ps "OnEdgeStrategy"
     
    31073153)
    31083154)
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     3155*80 (CptPort
    31103156uid 1558,0
    31113157ps "OnEdgeStrategy"
     
    31463192)
    31473193)
    3148 *80 (CptPort
     3194*81 (CptPort
    31493195uid 1562,0
    31503196ps "OnEdgeStrategy"
     
    31853231)
    31863232)
    3187 *81 (CptPort
     3233*82 (CptPort
    31883234uid 1570,0
    31893235ps "OnEdgeStrategy"
     
    32243270)
    32253271)
    3226 *82 (CptPort
     3272*83 (CptPort
    32273273uid 1574,0
    32283274ps "OnEdgeStrategy"
     
    32613307)
    32623308)
    3263 *83 (CptPort
     3309*84 (CptPort
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    32653311ps "OnEdgeStrategy"
     
    32983344)
    32993345)
    3300 *84 (CptPort
     3346*85 (CptPort
    33013347uid 1582,0
    33023348ps "OnEdgeStrategy"
     
    33353381)
    33363382)
    3337 *85 (CptPort
     3383*86 (CptPort
    33383384uid 1586,0
    33393385ps "OnEdgeStrategy"
     
    33723418)
    33733419)
    3374 *86 (CptPort
     3420*87 (CptPort
    33753421uid 1590,0
    33763422ps "OnEdgeStrategy"
     
    34103456)
    34113457)
    3412 *87 (CptPort
     3458*88 (CptPort
    34133459uid 1594,0
    34143460ps "OnEdgeStrategy"
     
    34463492)
    34473493)
    3448 *88 (CptPort
     3494*89 (CptPort
    34493495uid 1598,0
    34503496ps "OnEdgeStrategy"
     
    34843530)
    34853531)
    3486 *89 (CptPort
     3532*90 (CptPort
    34873533uid 2218,0
    34883534ps "OnEdgeStrategy"
     
    35203566)
    35213567)
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     3568*91 (CptPort
    35233569uid 2222,0
    35243570ps "OnEdgeStrategy"
     
    35543600)
    35553601)
    3556 *91 (CptPort
     3602*92 (CptPort
    35573603uid 2226,0
    35583604ps "OnEdgeStrategy"
     
    35883634)
    35893635)
    3590 *92 (CptPort
     3636*93 (CptPort
    35913637uid 5216,0
    35923638ps "OnEdgeStrategy"
     
    36273673)
    36283674)
    3629 *93 (CptPort
     3675*94 (CptPort
    36303676uid 5275,0
    36313677ps "OnEdgeStrategy"
     
    36653711)
    36663712)
    3667 *94 (CptPort
     3713*95 (CptPort
    36683714uid 5924,0
    36693715ps "OnEdgeStrategy"
     
    37013747)
    37023748)
    3703 *95 (CptPort
     3749*96 (CptPort
    37043750uid 5928,0
    37053751ps "OnEdgeStrategy"
     
    37373783)
    37383784)
    3739 *96 (CptPort
     3785*97 (CptPort
    37403786uid 5932,0
    37413787ps "OnEdgeStrategy"
     
    37743820)
    37753821)
    3776 *97 (CptPort
     3822*98 (CptPort
    37773823uid 5936,0
    37783824ps "OnEdgeStrategy"
     
    38083854)
    38093855)
    3810 *98 (CptPort
     3856*99 (CptPort
    38113857uid 5940,0
    38123858ps "OnEdgeStrategy"
     
    38443890)
    38453891)
    3846 *99 (CptPort
     3892*100 (CptPort
    38473893uid 5944,0
    38483894ps "OnEdgeStrategy"
     
    38823928)
    38833929)
    3884 *100 (CptPort
     3930*101 (CptPort
    38853931uid 5970,0
    38863932ps "OnEdgeStrategy"
     
    39193965)
    39203966)
    3921 *101 (CptPort
     3967*102 (CptPort
    39223968uid 6356,0
    39233969ps "OnEdgeStrategy"
     
    39584004)
    39594005)
    3960 *102 (CptPort
     4006*103 (CptPort
    39614007uid 6446,0
    39624008ps "OnEdgeStrategy"
     
    39984044)
    39994045)
    4000 *103 (CptPort
     4046*104 (CptPort
    40014047uid 8406,0
    40024048ps "OnEdgeStrategy"
     
    40344080)
    40354081)
    4036 *104 (CptPort
     4082*105 (CptPort
    40374083uid 8748,0
    40384084ps "OnEdgeStrategy"
     
    40734119)
    40744120)
    4075 *105 (CptPort
     4121*106 (CptPort
    40764122uid 9223,0
    40774123ps "OnEdgeStrategy"
     
    41124158)
    41134159)
    4114 *106 (CptPort
     4160*107 (CptPort
    41154161uid 9227,0
    41164162ps "OnEdgeStrategy"
     
    41524198)
    41534199)
    4154 *107 (CptPort
     4200*108 (CptPort
    41554201uid 9933,0
    41564202ps "OnEdgeStrategy"
     
    41914237)
    41924238)
    4193 *108 (CptPort
     4239*109 (CptPort
    41944240uid 9937,0
    41954241ps "OnEdgeStrategy"
     
    42304276)
    42314277)
    4232 *109 (CptPort
     4278*110 (CptPort
    42334279uid 10212,0
    42344280ps "OnEdgeStrategy"
     
    42674313)
    42684314)
    4269 *110 (CptPort
     4315*111 (CptPort
    42704316uid 10216,0
    42714317ps "OnEdgeStrategy"
     
    43044350)
    43054351)
    4306 *111 (CptPort
     4352*112 (CptPort
    43074353uid 10619,0
    43084354ps "OnEdgeStrategy"
     
    43404386)
    43414387)
    4342 *112 (CptPort
     4388*113 (CptPort
    43434389uid 10623,0
    43444390ps "OnEdgeStrategy"
     
    43774423)
    43784424)
    4379 *113 (CptPort
     4425*114 (CptPort
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    43814427ps "OnEdgeStrategy"
     
    44164462)
    44174463)
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     4464*115 (CptPort
    44194465uid 13149,0
    44204466ps "OnEdgeStrategy"
     
    44524498)
    44534499)
    4454 *115 (CptPort
     4500*116 (CptPort
    44554501uid 13153,0
    44564502ps "OnEdgeStrategy"
     
    44914537)
    44924538)
    4493 *116 (CptPort
     4539*117 (CptPort
    44944540uid 13806,0
    44954541ps "OnEdgeStrategy"
     
    45264572)
    45274573)
    4528 *117 (CptPort
     4574*118 (CptPort
    45294575uid 13911,0
    45304576ps "OnEdgeStrategy"
     
    45614607)
    45624608)
    4563 *118 (CptPort
     4609*119 (CptPort
    45644610uid 13915,0
    45654611ps "OnEdgeStrategy"
     
    46134659stg "VerticalLayoutStrategy"
    46144660textVec [
    4615 *119 (Text
     4661*120 (Text
    46164662uid 1609,0
    46174663va (VaSet
     
    46234669tm "BdLibraryNameMgr"
    46244670)
    4625 *120 (Text
     4671*121 (Text
    46264672uid 1610,0
    46274673va (VaSet
     
    46334679tm "CptNameMgr"
    46344680)
    4635 *121 (Text
     4681*122 (Text
    46364682uid 1611,0
    46374683va (VaSet
     
    46864732archFileType "UNKNOWN"
    46874733)
    4688 *122 (Net
     4734*123 (Net
    46894735uid 1680,0
    46904736decl (Decl
     
    47054751)
    47064752)
    4707 *123 (SaComponent
     4753*124 (SaComponent
    47084754uid 1768,0
    47094755optionalChildren [
    4710 *124 (CptPort
     4756*125 (CptPort
    47114757uid 1760,0
    47124758ps "OnEdgeStrategy"
     
    47294775)
    47304776xt "-48800,68500,-42000,69500"
    4731 st "trigger_id : (47:0)"
     4777st "trigger_id : (31:0)"
    47324778ju 2
    47334779blo "-42000,69300"
     
    47404786n "trigger_id"
    47414787t "std_logic_vector"
    4742 b "(47 downto 0)"
     4788b "(31 downto 0)"
    47434789preAdd 0
    47444790posAdd 0
     
    47484794)
    47494795)
    4750 *125 (CptPort
     4796*126 (CptPort
    47514797uid 1764,0
    47524798ps "OnEdgeStrategy"
     
    47854831)
    47864832)
    4787 *126 (CptPort
     4833*127 (CptPort
    47884834uid 6207,0
    47894835ps "OnEdgeStrategy"
     
    48374883stg "VerticalLayoutStrategy"
    48384884textVec [
    4839 *127 (Text
     4885*128 (Text
    48404886uid 1771,0
    48414887va (VaSet
     
    48484894tm "BdLibraryNameMgr"
    48494895)
    4850 *128 (Text
     4896*129 (Text
    48514897uid 1772,0
    48524898va (VaSet
     
    48594905tm "CptNameMgr"
    48604906)
    4861 *129 (Text
     4907*130 (Text
    48624908uid 1773,0
    48634909va (VaSet
     
    49074953)
    49084954archFileType "UNKNOWN"
    4909 )
    4910 *130 (Net
    4911 uid 1981,0
    4912 lang 2
    4913 decl (Decl
    4914 n "trigger_id"
    4915 t "std_logic_vector"
    4916 b "(47 downto 0)"
    4917 preAdd 0
    4918 posAdd 0
    4919 o 119
    4920 suid 34,0
    4921 )
    4922 declText (MLText
    4923 uid 1982,0
    4924 va (VaSet
    4925 font "Courier New,8,0"
    4926 )
    4927 xt "-172000,98800,-139500,99600"
    4928 st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)
    4929 "
    4930 )
    49314955)
    49324956*131 (Net
     
    1701117035)
    1701217036)
    17013 *599 (Wire
     17037*599 (SaComponent
     17038uid 15728,0
     17039optionalChildren [
     17040*600 (CptPort
     17041uid 15712,0
     17042ps "OnEdgeStrategy"
     17043shape (Triangle
     17044uid 15713,0
     17045ro 90
     17046va (VaSet
     17047vasetType 1
     17048fg "0,65535,0"
     17049)
     17050xt "-83750,113625,-83000,114375"
     17051)
     17052tg (CPTG
     17053uid 15714,0
     17054ps "CptPortTextPlaceStrategy"
     17055stg "VerticalLayoutStrategy"
     17056f (Text
     17057uid 15715,0
     17058va (VaSet
     17059)
     17060xt "-82000,113500,-80700,114500"
     17061st "clk"
     17062blo "-82000,114300"
     17063)
     17064)
     17065thePort (LogicalPort
     17066decl (Decl
     17067n "clk"
     17068t "STD_LOGIC"
     17069preAdd 0
     17070posAdd 0
     17071o 1
     17072suid 1,0
     17073)
     17074)
     17075)
     17076*601 (CptPort
     17077uid 15716,0
     17078ps "OnEdgeStrategy"
     17079shape (Triangle
     17080uid 15717,0
     17081ro 90
     17082va (VaSet
     17083vasetType 1
     17084fg "0,65535,0"
     17085)
     17086xt "-83750,115625,-83000,116375"
     17087)
     17088tg (CPTG
     17089uid 15718,0
     17090ps "CptPortTextPlaceStrategy"
     17091stg "VerticalLayoutStrategy"
     17092f (Text
     17093uid 15719,0
     17094va (VaSet
     17095)
     17096xt "-82000,115500,-80100,116500"
     17097st "start"
     17098blo "-82000,116300"
     17099)
     17100)
     17101thePort (LogicalPort
     17102decl (Decl
     17103n "start"
     17104t "STD_LOGIC"
     17105preAdd 0
     17106posAdd 0
     17107o 2
     17108suid 2,0
     17109)
     17110)
     17111)
     17112*602 (CptPort
     17113uid 15720,0
     17114ps "OnEdgeStrategy"
     17115shape (Triangle
     17116uid 15721,0
     17117ro 90
     17118va (VaSet
     17119vasetType 1
     17120fg "0,65535,0"
     17121)
     17122xt "-73000,113625,-72250,114375"
     17123)
     17124tg (CPTG
     17125uid 15722,0
     17126ps "CptPortTextPlaceStrategy"
     17127stg "RightVerticalLayoutStrategy"
     17128f (Text
     17129uid 15723,0
     17130va (VaSet
     17131)
     17132xt "-78600,113500,-74000,114500"
     17133st "dna : (63:0)"
     17134ju 2
     17135blo "-74000,114300"
     17136)
     17137t (Text
     17138uid 15738,0
     17139va (VaSet
     17140)
     17141xt "-79700,114500,-74000,115500"
     17142st "(others => '0')"
     17143ju 2
     17144blo "-74000,115300"
     17145)
     17146)
     17147thePort (LogicalPort
     17148m 1
     17149decl (Decl
     17150n "dna"
     17151t "STD_LOGIC_VECTOR"
     17152b "(63 downto 0)"
     17153preAdd 0
     17154posAdd 0
     17155o 3
     17156suid 3,0
     17157i "(others => '0')"
     17158)
     17159)
     17160)
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