- Timestamp:
- Feb 15, 2011, 12:07:05 PM (9 years ago)
- Location:
- firmware/FAD
- Files:
-
- 5 added
- 25 edited
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FACT_FAD_20MHz_VAR_PS/FACT_FAD.hdp (modified) (1 diff)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/.cache.dat (modified) (previous)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd (modified) (8 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd (modified) (2 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd (modified) (7 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/dna_gen.vhd (added)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (modified) (2 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (modified) (1 diff)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (modified) (4 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd (modified) (2 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd (modified) (3 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd (modified) (2 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/trigger_counter_beha.vhd (modified) (2 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.cache.dat (modified) (previous)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/clock_generator_var_ps_struct.xrf (modified) (1 diff)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf (modified) (4 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd (modified) (526 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak (modified) (449 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb (modified) (4 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/_dna_gen._epf (added)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/struct.bd (modified) (86 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/struct.bd.bak (modified) (29 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/symbol.sb (modified) (3 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/data_generator/symbol.sb (modified) (184 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/dna_gen (added)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/dna_gen/@behavioral.bd (added)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/dna_gen/symbol.sb (added)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/phase_shifter/symbol.sb (modified) (36 diffs)
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FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/trigger_counter/symbol.sb (modified) (17 diffs)
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doc/memory_manager.tex (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD.hdp
r10129 r10155 5 5 FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/work 6 6 secureip = D:/unisim/secureip 7 simprim = D:/unisim/simprim8 unimacro = D:/unisim/unimacro9 unisim = D:/unisim/unisim10 XilinxCoreLib = D:/unisim/xilinxcorelib7 simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim 8 unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro 9 unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim 10 XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib 11 11 [QuestaSim] 12 12 secureip = D:/unisim/secureip 13 simprim = D:/unisim/simprim14 unimacro = D:/unisim/unimacro15 unisim = D:/unisim/unisim16 XilinxCoreLib = D:/unisim/xilinxcorelib13 simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim 14 unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro 15 unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim 16 XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib 17 17 [XilinxISE] 18 18 FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/ise 19 FACT_FAD_TB_lib = $HDS_PROJECT_DIR \FACT_FAD_TB_lib\ise19 FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise 20 20 [hdl] 21 21 FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hdl -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd
r10129 r10155 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 5:27:49 04.02.20115 -- at - 13:26:27 14.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 32 32 -- Created: 33 33 -- by - dneise.UNKNOWN (E5B-LABOR6) 34 -- at - 1 5:27:49 04.02.201134 -- at - 13:26:27 14.02.2011 35 35 -- 36 36 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 42 42 LIBRARY UNISIM; 43 43 --USE UNISIM.Vcomponents.all; 44 LIBRARY FACT_FAD_lib; 45 USE FACT_FAD_lib.fad_definitions.all; 44 46 45 47 LIBRARY FACT_FAD_lib; … … 56 58 SIGNAL PSEN_IN : std_logic; 57 59 SIGNAL PSINCDEC_IN : std_logic; 60 SIGNAL rst : std_logic := '0'; --asynch in of DCM 58 61 59 62 -- Implicit buffer signal declarations … … 91 94 PORT ( 92 95 CLK : IN std_logic ; 93 rst : IN std_logic ;--asynch in of DCM96 rst : OUT std_logic := '0'; --asynch in of DCM 94 97 -- interface to: clock_generator_variable_PS_struct.vhd 95 98 PSCLK : OUT std_logic ; 96 99 PSEN : OUT std_logic := '0'; 97 PSINCDEC : OUT std_logic := '1'; 98 PSDONE : IN std_logic ; 99 LOCKED : IN std_logic ; 100 PSINCDEC : OUT std_logic := '1'; -- default is 'incrementing' 101 PSDONE : IN std_logic ; -- will pulse once, if phase shifting was done. 102 LOCKED : IN std_logic ; -- when is this going high? 100 103 -- interface to: w5300_modul.vhd 101 104 shift_phase : IN std_logic ; 102 direction : IN std_logic ; -- corresponds TO 'PSINCDEC' 105 direction : IN std_logic ; -- corresponds TO 'PSINCDEC' 106 reset_DCM : IN std_logic ; -- asynch in: orders us, TO reset the DCM 103 107 -- status: 104 108 shifting : OUT std_logic := '0'; 105 109 ready : OUT std_logic := '0'; 106 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 107 DCM_locked : OUT std_logic 110 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') 108 111 ); 109 112 END COMPONENT; … … 139 142 PSEN_IN => PSEN_IN, 140 143 PSINCDEC_IN => PSINCDEC_IN, 141 RST_IN => RST_IN,144 RST_IN => rst, 142 145 CLK0_OUT => CLK_25_PS, 143 146 LOCKED_OUT => LOCKED_OUT, … … 147 150 PORT MAP ( 148 151 CLK => CLK0_OUT, 149 rst => RST_IN,152 rst => rst, 150 153 PSCLK => PSCLK_IN, 151 154 PSEN => PSEN_IN, … … 155 158 shift_phase => do_shift, 156 159 direction => direction, 160 reset_DCM => RST_IN, 157 161 shifting => OPEN, 158 162 ready => OPEN, 159 offset => offset, 160 DCM_locked => OPEN 163 offset => offset 161 164 ); 162 165 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd
r10129 r10155 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 1:39:13 04.02.20115 -- at - 13:10:37 12.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 42 42 -- Created: 43 43 -- by - dneise.UNKNOWN (E5B-LABOR6) 44 -- at - 1 1:39:13 04.02.201144 -- at - 13:10:37 12.02.2011 45 45 -- 46 46 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10138 r10155 45 45 sensor_ready : in std_logic; 46 46 dac_array : in dac_array_type; 47 48 -- EVT HEADER - part 1 47 49 package_length : in std_logic_vector (15 downto 0); 50 pll_lock : in std_logic_vector ( 3 downto 0); 51 -- 52 53 -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... 54 -- during EVT header wrinting, this field is left out ... and only written into event header, 55 -- when the DRS chip were read out already. 56 FTM_RS485_ready : in std_logic; 57 FTM_trigger_info : in std_logic_vector (55 downto 0); --7 byte 58 -- 59 60 -- EVT HEADER - part 3 61 fad_event_counter : in std_logic_vector (31 downto 0); 62 refclk_counter : in std_logic_vector (11 downto 0); 63 refclk_too_high: in std_logic; 64 refclk_too_low : in std_logic; 65 -- 66 67 -- EVT HEADER - part 4 48 68 board_id : in std_logic_vector (3 downto 0); 49 69 crate_id : in std_logic_vector (1 downto 0); 50 trigger_id : in std_logic_vector (47 downto 0); 70 DCM_PS_status : in std_logic_vector (7 downto 0); 71 TRG_GEN_no : in std_logic_vector (15 downto 0); 72 TRG_GEN_div : in std_logic_vector (15 downto 0); 73 -- 74 75 -- EVT HEADER - part 5 76 dna : in std_logic_vector (63 downto 0); 77 -- 78 79 -- EVT HEADER - part 6 80 timer_value : in std_logic_vector (31 downto 0); -- time in units of 100us 81 -- 82 51 83 trigger : in std_logic; 52 84 -- s_trigger : in std_logic; … … 79 111 architecture Behavioral of data_generator is 80 112 81 type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES, 82 WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT, 83 WRITE_END_FLAG, WRITE_DATA_STOP, WRITE_DATA_STOP1, 84 WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING); 113 type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, 114 WRITE_DATA_IDLE, 115 WRITE_HEADER, WRITE_FTM_INFO, WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER, WRITE_BOARD_ID, 116 WRITE_DNA, WRITE_TIMER, WRITE_TEMPERATURES, 117 WRITE_DAC1, WRITE_DAC2, 118 WAIT_FOR_STOP_CELL, 119 START_DRS_READING, 120 WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_FILLING, 121 WAIT_FOR_ADC, WRITE_ADC_DATA, 122 WRITE_EXTERNAL_TRIGGER, 123 WRITE_END_FLAG, 124 WRITE_DATA_END, WRITE_DATA_END_WAIT, 125 WRITE_DATA_STOP, WRITE_DATA_STOP1); 85 126 86 127 signal state_generate : state_generate_type := INIT; … … 199 240 when WRITE_HEADER => 200 241 write_ea <= "1"; 201 data_out <= X"0000" & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01"; 202 addr_cntr <= addr_cntr + 3; 203 state_generate <= WRITE_BOARD_ID; 204 when WRITE_BOARD_ID => -- crate ID & board ID 205 data_out <= (63 downto 10 => '0') & crate_id & "1000" & board_id; 206 addr_cntr <= addr_cntr + 1; 207 state_generate <= WRITE_TEMPERATURES; 242 data_out <= X"000" & pll_lock & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01"; 243 addr_cntr <= addr_cntr + 1; 244 state_generate <= WRITE_FTM_INFO; 245 246 when WRITE_FTM_INFO => 247 -- here we do not write the FTM info ... just jump over it. 248 addr_cntr <= addr_cntr + 1; 249 state_generate <= WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER; 250 251 when WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER => 252 data_out <= X"0000" & 253 refclk_too_high & refclk_too_low & "00" & refclk_counter & 254 fad_event_counter(15 downto 0) & 255 fad_event_counter(31 downto 16) ; 256 addr_cntr <= addr_cntr + 1; 257 state_generate <= WRITE_BOARD_ID; 258 -- crate ID & board ID 259 -- and a lot more... 260 -- info about the phase shifter 261 -- status of the trigger generator 262 when WRITE_BOARD_ID => 263 data_out <= TRG_GEN_div & TRG_GEN_no & X"00" & DCM_PS_status & "000000" & crate_id & "1000" & board_id; 264 addr_cntr <= addr_cntr + 1; 265 state_generate <= WRITE_DNA; 266 267 when WRITE_DNA => 268 data_out <= X"00" & dna(55 downto 0); 269 addr_cntr <= addr_cntr + 1; 270 state_generate <= WRITE_TIMER; 271 272 when WRITE_TIMER => 273 data_out <= X"0000" & X"0000" & timer_value; -- 2times 16bit reserved for additional status info 274 addr_cntr <= addr_cntr + 1; 275 state_generate <= WRITE_TEMPERATURES; 276 208 277 when WRITE_TEMPERATURES => -- temperatures 209 278 if (sensor_ready = '1') then … … 248 317 249 318 when WRITE_CHANNEL_ID => -- write DRS and Channel IDs 250 data_out <= conv_std_logic_vector(0,10) & conv_std_logic_vector(3,2) & conv_std_logic_vector(channel_id,4)251 & conv_std_logic_vector(0,10) & conv_std_logic_vector(2,2) & conv_std_logic_vector(channel_id,4)252 & conv_std_logic_vector(0,10) & conv_std_logic_vector(1,2) & conv_std_logic_vector(channel_id,4)253 & conv_std_logic_vector(0,10) & conv_std_logic_vector(0,2) & conv_std_logic_vector(channel_id,4);319 data_out <= conv_std_logic_vector(3,12) & conv_std_logic_vector(channel_id,4) 320 & conv_std_logic_vector(2,12) & conv_std_logic_vector(channel_id,4) 321 & conv_std_logic_vector(1,12) & conv_std_logic_vector(channel_id,4) 322 & conv_std_logic_vector(0,12) & conv_std_logic_vector(channel_id,4); 254 323 addr_cntr <= addr_cntr + 1; 255 324 state_generate <= WRITE_START_CELL; … … 267 336 & "00000" & conv_std_logic_vector (roi_array((0) * 9 + channel_id), 11); 268 337 addr_cntr <= addr_cntr + 1; 269 state_generate <= WAIT_FOR_ADC; 338 state_generate <= WRITE_FILLING; 339 340 when WRITE_FILLING => -- write FILLING 341 data_out <= conv_std_logic_vector(0,64); -- filling 342 addr_cntr <= addr_cntr + 1; 343 state_generate <= WAIT_FOR_ADC; 344 270 345 when WAIT_FOR_ADC => 271 346 -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! … … 281 356 & "000" & adc_otr(1) & adc_data_array(1) 282 357 & "000" & adc_otr(0) & adc_data_array(0); 283 358 -- data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) 284 359 -- & "00010" & conv_std_logic_vector (data_cntr, 11) 285 360 -- & "00100" & conv_std_logic_vector (data_cntr, 11) … … 303 378 end if; 304 379 305 306 380 when WRITE_EXTERNAL_TRIGGER => -- external trigger ID 307 381 addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH); 308 -- data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16); 309 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16); 310 state_generate <= WRITE_INTERNAL_TRIGGER; 311 when WRITE_INTERNAL_TRIGGER => -- internal trigger ID 312 addr_out <= start_addr + conv_std_logic_vector(2, RAM_ADDR_WIDTH); 313 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16); 382 data_out <= FTM_trigger_info(15 downto 0) 383 & FTM_trigger_info(31 downto 16) 384 & FTM_trigger_info(47 downto 32) 385 & X"00" & FTM_trigger_info(55 downto 48); 314 386 state_generate <= WRITE_END_FLAG; 387 315 388 when WRITE_END_FLAG => 316 389 data_out <= (63 downto 32 => '0') & X"04FE" & X"4242"; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10129 r10155 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 5:27:51 04.02.20115 -- at - 13:26:28 14.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 76 76 -- Created: 77 77 -- by - dneise.UNKNOWN (E5B-LABOR6) 78 -- at - 1 5:27:51 04.02.201178 -- at - 13:26:28 14.02.2011 79 79 -- 80 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10138 r10155 56 56 constant PACKAGE_HEADER_LENGTH : integer := 22; 57 57 constant PACKAGE_END_LENGTH : integer := 2; -- CRC and END-Flag 58 constant CHANNEL_HEADER_SIZE : integer := 3; 58 59 59 60 constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10129 r10155 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 5:27:49 04.02.20115 -- at - 13:26:27 14.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 72 72 -- Created: 73 73 -- by - dneise.UNKNOWN (E5B-LABOR6) 74 -- at - 1 5:27:50 04.02.201174 -- at - 13:26:28 14.02.2011 75 75 -- 76 76 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 171 171 SIGNAL trigger_enable : std_logic; 172 172 SIGNAL trigger_id : std_logic_vector(47 DOWNTO 0); 173 SIGNAL trigger_out : std_logic ;173 SIGNAL trigger_out : std_logic := '0'; 174 174 SIGNAL wiz_ack : std_logic; 175 175 SIGNAL wiz_busy : std_logic; … … 451 451 c_trigger_enable : OUT std_logic := '0'; 452 452 c_trigger_mult : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '1'); --subject TO changes 453 -- 453 -- FAD configuration signals: 454 ------------------------------------------------------------------------------ 455 -- start entire configuration chain 454 456 new_config : OUT std_logic := '0'; 455 457 config_started : IN std_logic ; 458 -- read/write configRAM 456 459 config_addr : OUT std_logic_vector (7 DOWNTO 0); 457 460 config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); 458 461 config_wr_en : OUT std_logic := '0'; 459 462 config_rd_en : OUT std_logic := '0'; 460 -- --461 463 config_rw_ack : IN std_logic ; 462 -- --463 464 config_rw_ready : IN std_logic ; 464 -- --465 465 config_busy : IN std_logic ; 466 ------------------------------------------------------------------------------ 467 468 -- MAC/IP calculation signals: 469 ------------------------------------------------------------------------------ 466 470 MAC_jumper : IN std_logic_vector (1 DOWNTO 0); 467 471 BoardID : IN std_logic_vector (3 DOWNTO 0); 468 472 CrateID : IN std_logic_vector (1 DOWNTO 0); 473 ------------------------------------------------------------------------------ 474 475 -- user controllable enable signals 476 ------------------------------------------------------------------------------ 477 trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted 469 478 denable : OUT std_logic := '0'; -- default domino wave off 470 479 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. 471 480 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. 481 srclk_enable : OUT std_logic := '1'; -- default SRCLK on. 482 ------------------------------------------------------------------------------ 483 484 -- ADC CLK generator, is able to shift phase with respect to X_50M 485 -- these signals control the behavior of the digital clock manager (DCM) 486 ------------------------------------------------------------------------------ 472 487 ps_direction : OUT std_logic := '1'; -- default phase shift upwards 473 488 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once 474 489 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift 475 srclk_enable : OUT std_logic := '1'; -- default SRCLK on. 476 trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted 490 ------------------------------------------------------------------------------ 491 492 -- signals used to control FAD LED bahavior: 493 -- one of the three LEDs is used for com-status info 494 ------------------------------------------------------------------------------ 477 495 socks_waiting : OUT std_logic ; 478 496 socks_connected : OUT std_logic 497 ------------------------------------------------------------------------------ 479 498 ); 480 499 END COMPONENT; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd
r10072 r10155 51 51 wiz_write_end : OUT std_logic := '0'; 52 52 wiz_busy : IN std_logic; 53 wiz_ack : IN std_logic;53 wiz_ack : IN std_logic; 54 54 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') 55 55 ); … … 134 134 roi_max_array (channel_id) <= temp_roi; 135 135 end if; 136 channel_size (channel_id) <= channel_size (channel_id) + temp_roi + 3;136 channel_size (channel_id) <= channel_size (channel_id) + temp_roi + CHANNEL_HEADER_SIZE; 137 137 drs_id <= drs_id + 1; 138 138 state_mm <= MAX_ROI; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd
r10154 r10155 35 35 shifting : OUT std_logic := '0'; 36 36 ready : OUT std_logic := '0'; 37 37 38 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') 38 39 … … 93 94 94 95 -- MAIN FSM 95 FSM: process( state, PSDONE, LOCKED, shift_phase, direction, local_direction)96 FSM: process(CLK) 96 97 begin 97 98 … … 144 145 end if; 145 146 146 if (reset_dcm_sr = "01") then 147 if (reset_dcm_sr = "01") then 147 148 state <= RESET_STATE; 148 149 end if; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd
r10129 r10155 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 6:13:08 03.02.20115 -- at - 13:10:37 12.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 38 38 -- Created: 39 39 -- by - dneise.UNKNOWN (E5B-LABOR6) 40 -- at - 1 6:13:08 03.02.201140 -- at - 13:10:37 12.02.2011 41 41 -- 42 42 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/trigger_counter_beha.vhd
r9912 r10155 16 16 entity trigger_counter is 17 17 port( 18 trigger_id : out std_logic_vector( 47downto 0);18 trigger_id : out std_logic_vector(31 downto 0); 19 19 trigger : in std_logic; 20 20 clk : in std_logic … … 29 29 begin 30 30 31 trigger_id <= X"AA55" &conv_std_logic_vector(temp_id, 32);31 trigger_id <= conv_std_logic_vector(temp_id, 32); 32 32 33 33 trigger_incr_proc: process(clk) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/clock_generator_var_ps_struct.xrf
r10129 r10155 43 43 DESIGN clock_generator_var_ps 44 44 VIEW struct.bd 45 NO_GRAPHIC 43 46 DESIGN clock_generator_var_ps 47 VIEW struct.bd 48 GRAPHIC 0,0 46 2 49 DESIGN clock_generator_var_ps 50 VIEW struct.bd 51 GRAPHIC 524,0 51 0 52 DESIGN clock_generator_var_ps 53 VIEW struct.bd 54 GRAPHIC 600,0 52 0 55 DESIGN clock_generator_var_ps 56 VIEW struct.bd 57 GRAPHIC 530,0 53 0 58 DESIGN clock_generator_var_ps 59 VIEW struct.bd 60 GRAPHIC 586,0 54 0 61 DESIGN clock_generator_var_ps 62 VIEW struct.bd 63 GRAPHIC 544,0 55 0 64 DESIGN clock_generator_var_ps 65 VIEW struct.bd 66 GRAPHIC 558,0 56 0 67 DESIGN clock_generator_var_ps 68 VIEW struct.bd 69 NO_GRAPHIC 57 70 DESIGN clock_generator_var_ps 71 VIEW struct.bd 72 GRAPHIC 229,0 59 0 73 DESIGN clock_generator_var_ps 74 VIEW struct.bd 75 NO_GRAPHIC 61 45 NO_GRAPHIC 45 46 DESIGN clock_generator_var_ps 47 VIEW struct.bd 48 GRAPHIC 0,0 48 2 49 DESIGN clock_generator_var_ps 50 VIEW struct.bd 51 GRAPHIC 524,0 53 0 52 DESIGN clock_generator_var_ps 53 VIEW struct.bd 54 GRAPHIC 600,0 54 0 55 DESIGN clock_generator_var_ps 56 VIEW struct.bd 57 GRAPHIC 530,0 55 0 58 DESIGN clock_generator_var_ps 59 VIEW struct.bd 60 GRAPHIC 586,0 56 0 61 DESIGN clock_generator_var_ps 62 VIEW struct.bd 63 GRAPHIC 544,0 57 0 64 DESIGN clock_generator_var_ps 65 VIEW struct.bd 66 GRAPHIC 558,0 58 0 67 DESIGN clock_generator_var_ps 68 VIEW struct.bd 69 GRAPHIC 1979,0 59 0 70 DESIGN clock_generator_var_ps 71 VIEW struct.bd 72 NO_GRAPHIC 60 73 DESIGN clock_generator_var_ps 74 VIEW struct.bd 75 GRAPHIC 229,0 62 0 76 DESIGN clock_generator_var_ps 77 VIEW struct.bd 78 NO_GRAPHIC 64 76 79 LIBRARY FACT_FAD_lib 77 80 DESIGN dcm_50_to_25 78 81 VIEW @b@e@h@a@v@i@o@r@a@l 79 GRAPHIC 403,0 6 3080 DESIGN clock_generator_var_ps 81 VIEW struct.bd 82 NO_GRAPHIC 6983 DESIGN clock_generator_var_ps 84 VIEW struct.bd 85 GRAPHIC 354,0 7 1086 DESIGN clock_generator_var_ps 87 VIEW struct.bd 88 NO_GRAPHIC 7 589 DESIGN clock_generator_var_ps 90 VIEW struct.bd 91 GRAPHIC 514,0 77092 DESIGN clock_generator_var_ps 93 VIEW struct.bd 94 NO_GRAPHIC 8795 DESIGN clock_generator_var_ps 96 VIEW struct.bd 97 GRAPHIC 826,0 89098 DESIGN phase_shifter 99 VIEW first_behave 100 GRAPHIC 48,0 9 10101 DESIGN phase_shifter 102 VIEW first_behave 103 GRAPHIC 281,0 9 20104 DESIGN phase_shifter 105 VIEW first_behave 106 GRAPHIC 53,0 9 30107 DESIGN phase_shifter 108 VIEW first_behave 109 GRAPHIC 58,0 9 50110 DESIGN phase_shifter 111 VIEW first_behave 112 GRAPHIC 63,0 9 60113 DESIGN phase_shifter 114 VIEW first_behave 115 GRAPHIC 68,0 970116 DESIGN phase_shifter 117 VIEW first_behave 118 GRAPHIC 73,0 980119 DESIGN phase_shifter 120 VIEW first_behave 121 GRAPHIC 83,0 990122 DESIGN phase_shifter 123 VIEW first_behave 124 GRAPHIC 88,0 10 10125 DESIGN phase_shifter 126 VIEW first_behave 127 GRAPHIC 93,0 1020128 DESIGN phase_shifter 129 VIEW first_behave 130 GRAPHIC 9 8,0 1040131 DESIGN phase_shifter 132 VIEW first_behave 133 GRAPHIC 103,0 1050134 DESIGN phase_shifter 135 VIEW first_behave 136 GRAPHIC 10 8,0 106082 GRAPHIC 403,0 66 0 83 DESIGN clock_generator_var_ps 84 VIEW struct.bd 85 NO_GRAPHIC 72 86 DESIGN clock_generator_var_ps 87 VIEW struct.bd 88 GRAPHIC 354,0 74 0 89 DESIGN clock_generator_var_ps 90 VIEW struct.bd 91 NO_GRAPHIC 78 92 DESIGN clock_generator_var_ps 93 VIEW struct.bd 94 GRAPHIC 514,0 80 0 95 DESIGN clock_generator_var_ps 96 VIEW struct.bd 97 NO_GRAPHIC 90 98 DESIGN clock_generator_var_ps 99 VIEW struct.bd 100 GRAPHIC 826,0 92 0 101 DESIGN phase_shifter 102 VIEW first_behave 103 GRAPHIC 48,0 94 0 104 DESIGN phase_shifter 105 VIEW first_behave 106 GRAPHIC 281,0 95 0 107 DESIGN phase_shifter 108 VIEW first_behave 109 GRAPHIC 53,0 96 0 110 DESIGN phase_shifter 111 VIEW first_behave 112 GRAPHIC 58,0 98 0 113 DESIGN phase_shifter 114 VIEW first_behave 115 GRAPHIC 63,0 99 0 116 DESIGN phase_shifter 117 VIEW first_behave 118 GRAPHIC 68,0 100 0 119 DESIGN phase_shifter 120 VIEW first_behave 121 GRAPHIC 73,0 101 0 122 DESIGN phase_shifter 123 VIEW first_behave 124 GRAPHIC 83,0 102 0 125 DESIGN phase_shifter 126 VIEW first_behave 127 GRAPHIC 88,0 104 0 128 DESIGN phase_shifter 129 VIEW first_behave 130 GRAPHIC 362,0 105 0 131 DESIGN phase_shifter 132 VIEW first_behave 133 GRAPHIC 93,0 106 0 134 DESIGN phase_shifter 135 VIEW first_behave 136 GRAPHIC 98,0 108 0 137 DESIGN phase_shifter 138 VIEW first_behave 139 GRAPHIC 103,0 109 0 137 140 LIBRARY FACT_FAD_lib 138 141 DESIGN clock_generator_var_ps 139 142 VIEW struct.bd 140 NO_GRAPHIC 109 141 DESIGN clock_generator_var_ps 142 VIEW struct.bd 143 GRAPHIC 403,0 112 0 144 DESIGN clock_generator_var_ps 145 VIEW struct.bd 146 GRAPHIC 354,0 113 0 147 DESIGN clock_generator_var_ps 148 VIEW struct.bd 149 GRAPHIC 514,0 114 0 150 DESIGN clock_generator_var_ps 151 VIEW struct.bd 152 GRAPHIC 826,0 115 0 153 DESIGN clock_generator_var_ps 154 VIEW struct.bd 155 NO_GRAPHIC 118 156 DESIGN clock_generator_var_ps 157 VIEW struct.bd 158 NO_GRAPHIC 120 159 DESIGN clock_generator_var_ps 160 VIEW struct.bd 161 GRAPHIC 403,0 122 0 162 DESIGN clock_generator_var_ps 163 VIEW struct.bd 164 GRAPHIC 163,0 124 0 165 DESIGN clock_generator_var_ps 166 VIEW struct.bd 167 GRAPHIC 209,0 125 0 168 DESIGN clock_generator_var_ps 169 VIEW struct.bd 170 GRAPHIC 191,0 127 0 171 DESIGN clock_generator_var_ps 172 VIEW struct.bd 173 GRAPHIC 354,0 129 0 174 DESIGN clock_generator_var_ps 175 VIEW struct.bd 176 GRAPHIC 229,0 131 0 177 DESIGN clock_generator_var_ps 178 VIEW struct.bd 179 GRAPHIC 526,0 132 0 180 DESIGN clock_generator_var_ps 181 VIEW struct.bd 182 GRAPHIC 514,0 134 0 183 DESIGN clock_generator_var_ps 184 VIEW struct.bd 185 GRAPHIC 526,0 136 0 186 DESIGN clock_generator_var_ps 187 VIEW struct.bd 188 GRAPHIC 532,0 137 0 189 DESIGN clock_generator_var_ps 190 VIEW struct.bd 191 GRAPHIC 546,0 138 0 192 DESIGN clock_generator_var_ps 193 VIEW struct.bd 194 GRAPHIC 841,0 139 0 195 DESIGN clock_generator_var_ps 196 VIEW struct.bd 197 GRAPHIC 1493,0 140 0 198 DESIGN clock_generator_var_ps 199 VIEW struct.bd 200 GRAPHIC 1254,0 141 0 201 DESIGN clock_generator_var_ps 202 VIEW struct.bd 203 GRAPHIC 602,0 142 0 204 DESIGN clock_generator_var_ps 205 VIEW struct.bd 206 GRAPHIC 588,0 143 0 207 DESIGN clock_generator_var_ps 208 VIEW struct.bd 209 GRAPHIC 826,0 145 0 210 DESIGN clock_generator_var_ps 211 VIEW struct.bd 212 GRAPHIC 1458,0 147 0 213 DESIGN clock_generator_var_ps 214 VIEW struct.bd 215 GRAPHIC 1625,0 148 0 216 DESIGN clock_generator_var_ps 217 VIEW struct.bd 218 GRAPHIC 532,0 149 0 219 DESIGN clock_generator_var_ps 220 VIEW struct.bd 221 GRAPHIC 546,0 150 0 222 DESIGN clock_generator_var_ps 223 VIEW struct.bd 224 GRAPHIC 841,0 151 0 225 DESIGN clock_generator_var_ps 226 VIEW struct.bd 227 GRAPHIC 588,0 152 0 228 DESIGN clock_generator_var_ps 229 VIEW struct.bd 230 GRAPHIC 602,0 153 0 231 DESIGN clock_generator_var_ps 232 VIEW struct.bd 233 GRAPHIC 1272,0 154 0 234 DESIGN clock_generator_var_ps 235 VIEW struct.bd 236 GRAPHIC 1286,0 155 0 237 DESIGN clock_generator_var_ps 238 VIEW struct.bd 239 GRAPHIC 1609,0 158 0 240 DESIGN clock_generator_var_ps 241 VIEW struct.bd 242 GRAPHIC 229,0 163 0 243 DESIGN clock_generator_var_ps 244 VIEW struct.bd 245 NO_GRAPHIC 165 143 NO_GRAPHIC 112 144 DESIGN clock_generator_var_ps 145 VIEW struct.bd 146 GRAPHIC 403,0 115 0 147 DESIGN clock_generator_var_ps 148 VIEW struct.bd 149 GRAPHIC 354,0 116 0 150 DESIGN clock_generator_var_ps 151 VIEW struct.bd 152 GRAPHIC 514,0 117 0 153 DESIGN clock_generator_var_ps 154 VIEW struct.bd 155 GRAPHIC 826,0 118 0 156 DESIGN clock_generator_var_ps 157 VIEW struct.bd 158 NO_GRAPHIC 121 159 DESIGN clock_generator_var_ps 160 VIEW struct.bd 161 NO_GRAPHIC 123 162 DESIGN clock_generator_var_ps 163 VIEW struct.bd 164 GRAPHIC 403,0 125 0 165 DESIGN clock_generator_var_ps 166 VIEW struct.bd 167 GRAPHIC 163,0 127 0 168 DESIGN clock_generator_var_ps 169 VIEW struct.bd 170 GRAPHIC 209,0 128 0 171 DESIGN clock_generator_var_ps 172 VIEW struct.bd 173 GRAPHIC 191,0 130 0 174 DESIGN clock_generator_var_ps 175 VIEW struct.bd 176 GRAPHIC 354,0 132 0 177 DESIGN clock_generator_var_ps 178 VIEW struct.bd 179 GRAPHIC 229,0 134 0 180 DESIGN clock_generator_var_ps 181 VIEW struct.bd 182 GRAPHIC 526,0 135 0 183 DESIGN clock_generator_var_ps 184 VIEW struct.bd 185 GRAPHIC 514,0 137 0 186 DESIGN clock_generator_var_ps 187 VIEW struct.bd 188 GRAPHIC 526,0 139 0 189 DESIGN clock_generator_var_ps 190 VIEW struct.bd 191 GRAPHIC 532,0 140 0 192 DESIGN clock_generator_var_ps 193 VIEW struct.bd 194 GRAPHIC 546,0 141 0 195 DESIGN clock_generator_var_ps 196 VIEW struct.bd 197 GRAPHIC 841,0 142 0 198 DESIGN clock_generator_var_ps 199 VIEW struct.bd 200 GRAPHIC 1981,0 143 0 201 DESIGN clock_generator_var_ps 202 VIEW struct.bd 203 GRAPHIC 1254,0 144 0 204 DESIGN clock_generator_var_ps 205 VIEW struct.bd 206 GRAPHIC 602,0 145 0 207 DESIGN clock_generator_var_ps 208 VIEW struct.bd 209 GRAPHIC 588,0 146 0 210 DESIGN clock_generator_var_ps 211 VIEW struct.bd 212 GRAPHIC 826,0 148 0 213 DESIGN clock_generator_var_ps 214 VIEW struct.bd 215 GRAPHIC 1458,0 150 0 216 DESIGN clock_generator_var_ps 217 VIEW struct.bd 218 GRAPHIC 1981,0 151 0 219 DESIGN clock_generator_var_ps 220 VIEW struct.bd 221 GRAPHIC 532,0 152 0 222 DESIGN clock_generator_var_ps 223 VIEW struct.bd 224 GRAPHIC 546,0 153 0 225 DESIGN clock_generator_var_ps 226 VIEW struct.bd 227 GRAPHIC 841,0 154 0 228 DESIGN clock_generator_var_ps 229 VIEW struct.bd 230 GRAPHIC 588,0 155 0 231 DESIGN clock_generator_var_ps 232 VIEW struct.bd 233 GRAPHIC 602,0 156 0 234 DESIGN clock_generator_var_ps 235 VIEW struct.bd 236 GRAPHIC 1272,0 157 0 237 DESIGN clock_generator_var_ps 238 VIEW struct.bd 239 GRAPHIC 1286,0 158 0 240 DESIGN clock_generator_var_ps 241 VIEW struct.bd 242 GRAPHIC 1493,0 159 0 243 DESIGN clock_generator_var_ps 244 VIEW struct.bd 245 GRAPHIC 1609,0 162 0 246 DESIGN clock_generator_var_ps 247 VIEW struct.bd 248 GRAPHIC 229,0 166 0 249 DESIGN clock_generator_var_ps 250 VIEW struct.bd 251 NO_GRAPHIC 168 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf
r10129 r10155 367 367 DESIGN @f@a@d_main 368 368 VIEW struct.bd 369 GRAPHIC 1 0449,0 172 0369 GRAPHIC 15492,0 172 0 370 370 DESIGN @f@a@d_main 371 371 VIEW struct.bd … … 884 884 DESIGN w5300_modul 885 885 VIEW @behavioral 886 GRAPHIC 566,0 45 40887 DESIGN w5300_modul 888 VIEW @behavioral 889 GRAPHIC 551,0 45 50890 DESIGN w5300_modul 891 VIEW @behavioral 892 GRAPHIC 561,0 45 60893 DESIGN w5300_modul 894 VIEW @behavioral 895 GRAPHIC 571,0 4 570896 DESIGN w5300_modul 897 VIEW @behavioral 898 GRAPHIC 640,0 4 580899 DESIGN w5300_modul 900 VIEW @behavioral 901 GRAPHIC 1052,0 4 590902 DESIGN w5300_modul 903 VIEW @behavioral 904 GRAPHIC 1057,0 46 10905 DESIGN w5300_modul 906 VIEW @behavioral 907 GRAPHIC 556,0 46 30886 GRAPHIC 566,0 456 0 887 DESIGN w5300_modul 888 VIEW @behavioral 889 GRAPHIC 551,0 457 0 890 DESIGN w5300_modul 891 VIEW @behavioral 892 GRAPHIC 561,0 459 0 893 DESIGN w5300_modul 894 VIEW @behavioral 895 GRAPHIC 571,0 460 0 896 DESIGN w5300_modul 897 VIEW @behavioral 898 GRAPHIC 640,0 461 0 899 DESIGN w5300_modul 900 VIEW @behavioral 901 GRAPHIC 1052,0 462 0 902 DESIGN w5300_modul 903 VIEW @behavioral 904 GRAPHIC 1057,0 463 0 905 DESIGN w5300_modul 906 VIEW @behavioral 907 GRAPHIC 556,0 464 0 908 908 DESIGN w5300_modul 909 909 VIEW @behavioral … … 911 911 DESIGN w5300_modul 912 912 VIEW @behavioral 913 GRAPHIC 1315,0 4 660914 DESIGN w5300_modul 915 VIEW @behavioral 916 GRAPHIC 1320,0 4 670917 DESIGN w5300_modul 918 VIEW @behavioral 919 GRAPHIC 670,0 4680920 DESIGN w5300_modul 921 VIEW @behavioral 922 GRAPHIC 723,0 4690923 DESIGN w5300_modul 924 VIEW @behavioral 925 GRAPHIC 917,0 4700926 DESIGN w5300_modul 927 VIEW @behavioral 928 GRAPHIC 9 49,0 4710929 DESIGN w5300_modul 930 VIEW @behavioral 931 GRAPHIC 954,0 4720932 DESIGN w5300_modul 933 VIEW @behavioral 934 GRAPHIC 9 88,0 4730935 DESIGN w5300_modul 936 VIEW @behavioral 937 GRAPHIC 1020,0 4740938 DESIGN w5300_modul 939 VIEW @behavioral 940 GRAPHIC 1130,0 4750941 DESIGN w5300_modul 942 VIEW @behavioral 943 GRAPHIC 1096,0 4 760944 DESIGN w5300_modul 945 VIEW @behavioral 946 GRAPHIC 1091,0 4 770913 GRAPHIC 1315,0 470 0 914 DESIGN w5300_modul 915 VIEW @behavioral 916 GRAPHIC 1320,0 471 0 917 DESIGN w5300_modul 918 VIEW @behavioral 919 GRAPHIC 1130,0 472 0 920 DESIGN w5300_modul 921 VIEW @behavioral 922 GRAPHIC 670,0 477 0 923 DESIGN w5300_modul 924 VIEW @behavioral 925 GRAPHIC 723,0 478 0 926 DESIGN w5300_modul 927 VIEW @behavioral 928 GRAPHIC 917,0 479 0 929 DESIGN w5300_modul 930 VIEW @behavioral 931 GRAPHIC 1020,0 480 0 932 DESIGN w5300_modul 933 VIEW @behavioral 934 GRAPHIC 949,0 481 0 935 DESIGN w5300_modul 936 VIEW @behavioral 937 GRAPHIC 954,0 487 0 938 DESIGN w5300_modul 939 VIEW @behavioral 940 GRAPHIC 988,0 488 0 941 DESIGN w5300_modul 942 VIEW @behavioral 943 GRAPHIC 1096,0 489 0 944 DESIGN w5300_modul 945 VIEW @behavioral 946 GRAPHIC 1091,0 495 0 947 947 LIBRARY FACT_FAD_lib 948 948 DESIGN @f@a@d_main 949 949 VIEW struct.bd 950 NO_GRAPHIC 480951 DESIGN @f@a@d_main952 VIEW struct.bd953 GRAPHIC 14417,0 483 0954 DESIGN @f@a@d_main955 VIEW struct.bd956 GRAPHIC 5678,0 484 0957 DESIGN @f@a@d_main958 VIEW struct.bd959 GRAPHIC 9175,0 485 0960 DESIGN @f@a@d_main961 VIEW struct.bd962 GRAPHIC 13117,0 486 0963 DESIGN @f@a@d_main964 VIEW struct.bd965 GRAPHIC 5072,0 487 0966 DESIGN @f@a@d_main967 VIEW struct.bd968 GRAPHIC 8277,0 488 0969 DESIGN @f@a@d_main970 VIEW struct.bd971 GRAPHIC 1399,0 489 0972 DESIGN @f@a@d_main973 VIEW struct.bd974 GRAPHIC 4903,0 490 0975 DESIGN @f@a@d_main976 VIEW struct.bd977 GRAPHIC 11209,0 491 0978 DESIGN @f@a@d_main979 VIEW struct.bd980 GRAPHIC 2311,0 492 0981 DESIGN @f@a@d_main982 VIEW struct.bd983 GRAPHIC 5793,0 493 0984 DESIGN @f@a@d_main985 VIEW struct.bd986 GRAPHIC 1768,0 494 0987 DESIGN @f@a@d_main988 VIEW struct.bd989 GRAPHIC 12625,0 495 0990 DESIGN @f@a@d_main991 VIEW struct.bd992 GRAPHIC 1606,0 496 0993 DESIGN @f@a@d_main994 VIEW struct.bd995 950 NO_GRAPHIC 499 996 951 DESIGN @f@a@d_main 997 952 VIEW struct.bd 998 GRAPHIC 6529,0 501 0 999 DESIGN @f@a@d_main 1000 VIEW struct.bd 1001 GRAPHIC 9957,0 504 0 1002 DESIGN @f@a@d_main 1003 VIEW struct.bd 1004 GRAPHIC 8721,0 507 0 1005 DESIGN @f@a@d_main 1006 VIEW struct.bd 1007 GRAPHIC 14991,0 510 0 1008 DESIGN @f@a@d_main 1009 VIEW struct.bd 1010 GRAPHIC 12295,0 513 0 1011 DESIGN @f@a@d_main 1012 VIEW struct.bd 1013 GRAPHIC 15058,0 516 0 1014 DESIGN @f@a@d_main 1015 VIEW struct.bd 1016 GRAPHIC 15036,0 519 0 1017 DESIGN @f@a@d_main 1018 VIEW struct.bd 1019 GRAPHIC 10380,0 523 0 1020 DESIGN @f@a@d_main 1021 VIEW struct.bd 1022 GRAPHIC 13266,0 526 0 1023 DESIGN @f@a@d_main 1024 VIEW struct.bd 1025 NO_GRAPHIC 529 1026 DESIGN @f@a@d_main 1027 VIEW struct.bd 1028 GRAPHIC 14417,0 531 0 1029 DESIGN @f@a@d_main 1030 VIEW struct.bd 1031 GRAPHIC 14427,0 533 0 1032 DESIGN @f@a@d_main 1033 VIEW struct.bd 1034 GRAPHIC 14048,0 534 0 1035 DESIGN @f@a@d_main 1036 VIEW struct.bd 1037 GRAPHIC 14622,0 535 0 1038 DESIGN @f@a@d_main 1039 VIEW struct.bd 1040 GRAPHIC 14479,0 536 0 1041 DESIGN @f@a@d_main 1042 VIEW struct.bd 1043 GRAPHIC 14493,0 537 0 1044 DESIGN @f@a@d_main 1045 VIEW struct.bd 1046 GRAPHIC 5678,0 539 0 1047 DESIGN @f@a@d_main 1048 VIEW struct.bd 1049 GRAPHIC 5646,0 541 0 1050 DESIGN @f@a@d_main 1051 VIEW struct.bd 1052 GRAPHIC 4272,0 542 0 1053 DESIGN @f@a@d_main 1054 VIEW struct.bd 1055 GRAPHIC 2786,0 543 0 1056 DESIGN @f@a@d_main 1057 VIEW struct.bd 1058 GRAPHIC 5626,0 544 0 1059 DESIGN @f@a@d_main 1060 VIEW struct.bd 1061 GRAPHIC 5634,0 545 0 1062 DESIGN @f@a@d_main 1063 VIEW struct.bd 1064 GRAPHIC 9175,0 547 0 1065 DESIGN @f@a@d_main 1066 VIEW struct.bd 1067 GRAPHIC 4042,0 549 0 1068 DESIGN @f@a@d_main 1069 VIEW struct.bd 1070 GRAPHIC 10036,0 550 0 1071 DESIGN @f@a@d_main 1072 VIEW struct.bd 1073 GRAPHIC 9253,0 551 0 1074 DESIGN @f@a@d_main 1075 VIEW struct.bd 1076 GRAPHIC 9261,0 552 0 1077 DESIGN @f@a@d_main 1078 VIEW struct.bd 1079 GRAPHIC 6072,0 553 0 1080 DESIGN @f@a@d_main 1081 VIEW struct.bd 1082 GRAPHIC 3984,0 554 0 1083 DESIGN @f@a@d_main 1084 VIEW struct.bd 1085 GRAPHIC 3888,0 555 0 1086 DESIGN @f@a@d_main 1087 VIEW struct.bd 1088 GRAPHIC 13117,0 558 0 1089 DESIGN @f@a@d_main 1090 VIEW struct.bd 1091 GRAPHIC 13124,0 559 1 1092 DESIGN @f@a@d_main 1093 VIEW struct.bd 1094 GRAPHIC 13143,0 563 0 1095 DESIGN @f@a@d_main 1096 VIEW struct.bd 1097 GRAPHIC 13159,0 564 0 1098 DESIGN @f@a@d_main 1099 VIEW struct.bd 1100 GRAPHIC 13165,0 565 0 1101 DESIGN @f@a@d_main 1102 VIEW struct.bd 1103 GRAPHIC 13210,0 566 0 1104 DESIGN @f@a@d_main 1105 VIEW struct.bd 1106 GRAPHIC 5072,0 568 0 1107 DESIGN @f@a@d_main 1108 VIEW struct.bd 1109 GRAPHIC 5582,0 570 0 1110 DESIGN @f@a@d_main 1111 VIEW struct.bd 1112 GRAPHIC 5090,0 571 0 1113 DESIGN @f@a@d_main 1114 VIEW struct.bd 1115 GRAPHIC 5130,0 572 0 1116 DESIGN @f@a@d_main 1117 VIEW struct.bd 1118 GRAPHIC 5184,0 573 0 1119 DESIGN @f@a@d_main 1120 VIEW struct.bd 1121 GRAPHIC 5122,0 574 0 1122 DESIGN @f@a@d_main 1123 VIEW struct.bd 1124 GRAPHIC 5106,0 575 0 1125 DESIGN @f@a@d_main 1126 VIEW struct.bd 1127 GRAPHIC 5098,0 576 0 1128 DESIGN @f@a@d_main 1129 VIEW struct.bd 1130 GRAPHIC 5190,0 577 0 1131 DESIGN @f@a@d_main 1132 VIEW struct.bd 1133 GRAPHIC 10194,0 578 0 1134 DESIGN @f@a@d_main 1135 VIEW struct.bd 1136 GRAPHIC 10202,0 579 0 1137 DESIGN @f@a@d_main 1138 VIEW struct.bd 1139 GRAPHIC 6002,0 580 0 1140 DESIGN @f@a@d_main 1141 VIEW struct.bd 1142 GRAPHIC 5146,0 581 0 1143 DESIGN @f@a@d_main 1144 VIEW struct.bd 1145 GRAPHIC 5138,0 582 0 1146 DESIGN @f@a@d_main 1147 VIEW struct.bd 1148 GRAPHIC 5114,0 583 0 1149 DESIGN @f@a@d_main 1150 VIEW struct.bd 1151 GRAPHIC 8277,0 585 0 1152 DESIGN @f@a@d_main 1153 VIEW struct.bd 1154 GRAPHIC 5602,0 587 0 1155 DESIGN @f@a@d_main 1156 VIEW struct.bd 1157 GRAPHIC 334,0 588 0 1158 DESIGN @f@a@d_main 1159 VIEW struct.bd 1160 GRAPHIC 328,0 589 0 1161 DESIGN @f@a@d_main 1162 VIEW struct.bd 1163 GRAPHIC 322,0 590 0 1164 DESIGN @f@a@d_main 1165 VIEW struct.bd 1166 GRAPHIC 4240,0 591 0 1167 DESIGN @f@a@d_main 1168 VIEW struct.bd 1169 GRAPHIC 364,0 592 0 1170 DESIGN @f@a@d_main 1171 VIEW struct.bd 1172 GRAPHIC 370,0 593 0 1173 DESIGN @f@a@d_main 1174 VIEW struct.bd 1175 GRAPHIC 1399,0 595 0 1176 DESIGN @f@a@d_main 1177 VIEW struct.bd 1178 GRAPHIC 1406,0 596 1 1179 DESIGN @f@a@d_main 1180 VIEW struct.bd 1181 GRAPHIC 5602,0 600 0 1182 DESIGN @f@a@d_main 1183 VIEW struct.bd 1184 GRAPHIC 334,0 601 0 1185 DESIGN @f@a@d_main 1186 VIEW struct.bd 1187 GRAPHIC 328,0 602 0 1188 DESIGN @f@a@d_main 1189 VIEW struct.bd 1190 GRAPHIC 322,0 603 0 1191 DESIGN @f@a@d_main 1192 VIEW struct.bd 1193 GRAPHIC 2299,0 604 0 1194 DESIGN @f@a@d_main 1195 VIEW struct.bd 1196 GRAPHIC 2576,0 605 0 1197 DESIGN @f@a@d_main 1198 VIEW struct.bd 1199 GRAPHIC 2582,0 606 0 1200 DESIGN @f@a@d_main 1201 VIEW struct.bd 1202 GRAPHIC 10467,0 607 0 1203 DESIGN @f@a@d_main 1204 VIEW struct.bd 1205 GRAPHIC 2588,0 608 0 1206 DESIGN @f@a@d_main 1207 VIEW struct.bd 1208 GRAPHIC 5184,0 609 0 1209 DESIGN @f@a@d_main 1210 VIEW struct.bd 1211 GRAPHIC 5745,0 610 0 1212 DESIGN @f@a@d_main 1213 VIEW struct.bd 1214 GRAPHIC 2594,0 611 0 1215 DESIGN @f@a@d_main 1216 VIEW struct.bd 1217 GRAPHIC 5190,0 612 0 1218 DESIGN @f@a@d_main 1219 VIEW struct.bd 1220 GRAPHIC 5404,0 613 0 1221 DESIGN @f@a@d_main 1222 VIEW struct.bd 1223 GRAPHIC 6018,0 614 0 1224 DESIGN @f@a@d_main 1225 VIEW struct.bd 1226 GRAPHIC 6002,0 615 0 1227 DESIGN @f@a@d_main 1228 VIEW struct.bd 1229 GRAPHIC 6008,0 616 0 1230 DESIGN @f@a@d_main 1231 VIEW struct.bd 1232 GRAPHIC 5138,0 617 0 1233 DESIGN @f@a@d_main 1234 VIEW struct.bd 1235 GRAPHIC 2600,0 618 0 1236 DESIGN @f@a@d_main 1237 VIEW struct.bd 1238 GRAPHIC 5480,0 619 0 1239 DESIGN @f@a@d_main 1240 VIEW struct.bd 1241 GRAPHIC 5474,0 620 0 1242 DESIGN @f@a@d_main 1243 VIEW struct.bd 1244 GRAPHIC 6064,0 621 0 1245 DESIGN @f@a@d_main 1246 VIEW struct.bd 1247 GRAPHIC 2642,0 622 0 1248 DESIGN @f@a@d_main 1249 VIEW struct.bd 1250 GRAPHIC 1411,0 623 0 1251 DESIGN @f@a@d_main 1252 VIEW struct.bd 1253 GRAPHIC 1682,0 624 0 1254 DESIGN @f@a@d_main 1255 VIEW struct.bd 1256 GRAPHIC 1983,0 625 0 1257 DESIGN @f@a@d_main 1258 VIEW struct.bd 1259 GRAPHIC 10439,0 626 0 1260 DESIGN @f@a@d_main 1261 VIEW struct.bd 1262 GRAPHIC 5950,0 627 0 1263 DESIGN @f@a@d_main 1264 VIEW struct.bd 1265 GRAPHIC 5962,0 628 0 1266 DESIGN @f@a@d_main 1267 VIEW struct.bd 1268 GRAPHIC 5626,0 629 0 1269 DESIGN @f@a@d_main 1270 VIEW struct.bd 1271 GRAPHIC 2778,0 630 0 1272 DESIGN @f@a@d_main 1273 VIEW struct.bd 1274 GRAPHIC 9006,0 631 0 1275 DESIGN @f@a@d_main 1276 VIEW struct.bd 1277 GRAPHIC 5634,0 632 0 1278 DESIGN @f@a@d_main 1279 VIEW struct.bd 1280 GRAPHIC 4537,0 633 0 1281 DESIGN @f@a@d_main 1282 VIEW struct.bd 1283 GRAPHIC 12649,0 634 0 1284 DESIGN @f@a@d_main 1285 VIEW struct.bd 1286 GRAPHIC 12655,0 635 0 1287 DESIGN @f@a@d_main 1288 VIEW struct.bd 1289 GRAPHIC 4401,0 636 0 1290 DESIGN @f@a@d_main 1291 VIEW struct.bd 1292 GRAPHIC 4419,0 637 0 1293 DESIGN @f@a@d_main 1294 VIEW struct.bd 1295 GRAPHIC 10298,0 638 0 1296 DESIGN @f@a@d_main 1297 VIEW struct.bd 1298 GRAPHIC 10304,0 639 0 1299 DESIGN @f@a@d_main 1300 VIEW struct.bd 1301 GRAPHIC 10316,0 640 0 1302 DESIGN @f@a@d_main 1303 VIEW struct.bd 1304 GRAPHIC 10310,0 641 0 1305 DESIGN @f@a@d_main 1306 VIEW struct.bd 1307 GRAPHIC 4743,0 642 0 1308 DESIGN @f@a@d_main 1309 VIEW struct.bd 1310 GRAPHIC 4407,0 643 0 1311 DESIGN @f@a@d_main 1312 VIEW struct.bd 1313 GRAPHIC 11405,0 644 0 1314 DESIGN @f@a@d_main 1315 VIEW struct.bd 1316 GRAPHIC 4903,0 646 0 1317 DESIGN @f@a@d_main 1318 VIEW struct.bd 1319 GRAPHIC 4757,0 648 0 1320 DESIGN @f@a@d_main 1321 VIEW struct.bd 1322 GRAPHIC 4401,0 649 0 1323 DESIGN @f@a@d_main 1324 VIEW struct.bd 1325 GRAPHIC 4419,0 650 0 1326 DESIGN @f@a@d_main 1327 VIEW struct.bd 1328 GRAPHIC 4671,0 651 0 1329 DESIGN @f@a@d_main 1330 VIEW struct.bd 1331 GRAPHIC 4679,0 652 0 1332 DESIGN @f@a@d_main 1333 VIEW struct.bd 1334 GRAPHIC 4687,0 653 0 1335 DESIGN @f@a@d_main 1336 VIEW struct.bd 1337 GRAPHIC 4695,0 654 0 1338 DESIGN @f@a@d_main 1339 VIEW struct.bd 1340 GRAPHIC 4407,0 655 0 1341 DESIGN @f@a@d_main 1342 VIEW struct.bd 1343 GRAPHIC 4743,0 656 0 953 GRAPHIC 14417,0 502 0 954 DESIGN @f@a@d_main 955 VIEW struct.bd 956 GRAPHIC 5678,0 503 0 957 DESIGN @f@a@d_main 958 VIEW struct.bd 959 GRAPHIC 9175,0 504 0 960 DESIGN @f@a@d_main 961 VIEW struct.bd 962 GRAPHIC 13117,0 505 0 963 DESIGN @f@a@d_main 964 VIEW struct.bd 965 GRAPHIC 5072,0 506 0 966 DESIGN @f@a@d_main 967 VIEW struct.bd 968 GRAPHIC 8277,0 507 0 969 DESIGN @f@a@d_main 970 VIEW struct.bd 971 GRAPHIC 1399,0 508 0 972 DESIGN @f@a@d_main 973 VIEW struct.bd 974 GRAPHIC 4903,0 509 0 975 DESIGN @f@a@d_main 976 VIEW struct.bd 977 GRAPHIC 11209,0 510 0 978 DESIGN @f@a@d_main 979 VIEW struct.bd 980 GRAPHIC 2311,0 511 0 981 DESIGN @f@a@d_main 982 VIEW struct.bd 983 GRAPHIC 5793,0 512 0 984 DESIGN @f@a@d_main 985 VIEW struct.bd 986 GRAPHIC 1768,0 513 0 987 DESIGN @f@a@d_main 988 VIEW struct.bd 989 GRAPHIC 12625,0 514 0 990 DESIGN @f@a@d_main 991 VIEW struct.bd 992 GRAPHIC 1606,0 515 0 993 DESIGN @f@a@d_main 994 VIEW struct.bd 995 NO_GRAPHIC 518 996 DESIGN @f@a@d_main 997 VIEW struct.bd 998 GRAPHIC 6529,0 520 0 999 DESIGN @f@a@d_main 1000 VIEW struct.bd 1001 GRAPHIC 9957,0 523 0 1002 DESIGN @f@a@d_main 1003 VIEW struct.bd 1004 GRAPHIC 8721,0 526 0 1005 DESIGN @f@a@d_main 1006 VIEW struct.bd 1007 GRAPHIC 14991,0 529 0 1008 DESIGN @f@a@d_main 1009 VIEW struct.bd 1010 GRAPHIC 12295,0 532 0 1011 DESIGN @f@a@d_main 1012 VIEW struct.bd 1013 GRAPHIC 15058,0 535 0 1014 DESIGN @f@a@d_main 1015 VIEW struct.bd 1016 GRAPHIC 15036,0 538 0 1017 DESIGN @f@a@d_main 1018 VIEW struct.bd 1019 GRAPHIC 10380,0 542 0 1020 DESIGN @f@a@d_main 1021 VIEW struct.bd 1022 GRAPHIC 13266,0 545 0 1023 DESIGN @f@a@d_main 1024 VIEW struct.bd 1025 NO_GRAPHIC 548 1026 DESIGN @f@a@d_main 1027 VIEW struct.bd 1028 GRAPHIC 14417,0 550 0 1029 DESIGN @f@a@d_main 1030 VIEW struct.bd 1031 GRAPHIC 14427,0 552 0 1032 DESIGN @f@a@d_main 1033 VIEW struct.bd 1034 GRAPHIC 14048,0 553 0 1035 DESIGN @f@a@d_main 1036 VIEW struct.bd 1037 GRAPHIC 14622,0 554 0 1038 DESIGN @f@a@d_main 1039 VIEW struct.bd 1040 GRAPHIC 14479,0 555 0 1041 DESIGN @f@a@d_main 1042 VIEW struct.bd 1043 GRAPHIC 14493,0 556 0 1044 DESIGN @f@a@d_main 1045 VIEW struct.bd 1046 GRAPHIC 5678,0 558 0 1047 DESIGN @f@a@d_main 1048 VIEW struct.bd 1049 GRAPHIC 5646,0 560 0 1050 DESIGN @f@a@d_main 1051 VIEW struct.bd 1052 GRAPHIC 4272,0 561 0 1053 DESIGN @f@a@d_main 1054 VIEW struct.bd 1055 GRAPHIC 2786,0 562 0 1056 DESIGN @f@a@d_main 1057 VIEW struct.bd 1058 GRAPHIC 5626,0 563 0 1059 DESIGN @f@a@d_main 1060 VIEW struct.bd 1061 GRAPHIC 5634,0 564 0 1062 DESIGN @f@a@d_main 1063 VIEW struct.bd 1064 GRAPHIC 9175,0 566 0 1065 DESIGN @f@a@d_main 1066 VIEW struct.bd 1067 GRAPHIC 4042,0 568 0 1068 DESIGN @f@a@d_main 1069 VIEW struct.bd 1070 GRAPHIC 10036,0 569 0 1071 DESIGN @f@a@d_main 1072 VIEW struct.bd 1073 GRAPHIC 9253,0 570 0 1074 DESIGN @f@a@d_main 1075 VIEW struct.bd 1076 GRAPHIC 9261,0 571 0 1077 DESIGN @f@a@d_main 1078 VIEW struct.bd 1079 GRAPHIC 6072,0 572 0 1080 DESIGN @f@a@d_main 1081 VIEW struct.bd 1082 GRAPHIC 3984,0 573 0 1083 DESIGN @f@a@d_main 1084 VIEW struct.bd 1085 GRAPHIC 3888,0 574 0 1086 DESIGN @f@a@d_main 1087 VIEW struct.bd 1088 GRAPHIC 13117,0 577 0 1089 DESIGN @f@a@d_main 1090 VIEW struct.bd 1091 GRAPHIC 13124,0 578 1 1092 DESIGN @f@a@d_main 1093 VIEW struct.bd 1094 GRAPHIC 13143,0 582 0 1095 DESIGN @f@a@d_main 1096 VIEW struct.bd 1097 GRAPHIC 13159,0 583 0 1098 DESIGN @f@a@d_main 1099 VIEW struct.bd 1100 GRAPHIC 13165,0 584 0 1101 DESIGN @f@a@d_main 1102 VIEW struct.bd 1103 GRAPHIC 13210,0 585 0 1104 DESIGN @f@a@d_main 1105 VIEW struct.bd 1106 GRAPHIC 5072,0 587 0 1107 DESIGN @f@a@d_main 1108 VIEW struct.bd 1109 GRAPHIC 5582,0 589 0 1110 DESIGN @f@a@d_main 1111 VIEW struct.bd 1112 GRAPHIC 5090,0 590 0 1113 DESIGN @f@a@d_main 1114 VIEW struct.bd 1115 GRAPHIC 5130,0 591 0 1116 DESIGN @f@a@d_main 1117 VIEW struct.bd 1118 GRAPHIC 5184,0 592 0 1119 DESIGN @f@a@d_main 1120 VIEW struct.bd 1121 GRAPHIC 5122,0 593 0 1122 DESIGN @f@a@d_main 1123 VIEW struct.bd 1124 GRAPHIC 5106,0 594 0 1125 DESIGN @f@a@d_main 1126 VIEW struct.bd 1127 GRAPHIC 5098,0 595 0 1128 DESIGN @f@a@d_main 1129 VIEW struct.bd 1130 GRAPHIC 5190,0 596 0 1131 DESIGN @f@a@d_main 1132 VIEW struct.bd 1133 GRAPHIC 10194,0 597 0 1134 DESIGN @f@a@d_main 1135 VIEW struct.bd 1136 GRAPHIC 10202,0 598 0 1137 DESIGN @f@a@d_main 1138 VIEW struct.bd 1139 GRAPHIC 6002,0 599 0 1140 DESIGN @f@a@d_main 1141 VIEW struct.bd 1142 GRAPHIC 5146,0 600 0 1143 DESIGN @f@a@d_main 1144 VIEW struct.bd 1145 GRAPHIC 5138,0 601 0 1146 DESIGN @f@a@d_main 1147 VIEW struct.bd 1148 GRAPHIC 5114,0 602 0 1149 DESIGN @f@a@d_main 1150 VIEW struct.bd 1151 GRAPHIC 8277,0 604 0 1152 DESIGN @f@a@d_main 1153 VIEW struct.bd 1154 GRAPHIC 5602,0 606 0 1155 DESIGN @f@a@d_main 1156 VIEW struct.bd 1157 GRAPHIC 334,0 607 0 1158 DESIGN @f@a@d_main 1159 VIEW struct.bd 1160 GRAPHIC 328,0 608 0 1161 DESIGN @f@a@d_main 1162 VIEW struct.bd 1163 GRAPHIC 322,0 609 0 1164 DESIGN @f@a@d_main 1165 VIEW struct.bd 1166 GRAPHIC 4240,0 610 0 1167 DESIGN @f@a@d_main 1168 VIEW struct.bd 1169 GRAPHIC 364,0 611 0 1170 DESIGN @f@a@d_main 1171 VIEW struct.bd 1172 GRAPHIC 370,0 612 0 1173 DESIGN @f@a@d_main 1174 VIEW struct.bd 1175 GRAPHIC 1399,0 614 0 1176 DESIGN @f@a@d_main 1177 VIEW struct.bd 1178 GRAPHIC 1406,0 615 1 1179 DESIGN @f@a@d_main 1180 VIEW struct.bd 1181 GRAPHIC 5602,0 619 0 1182 DESIGN @f@a@d_main 1183 VIEW struct.bd 1184 GRAPHIC 334,0 620 0 1185 DESIGN @f@a@d_main 1186 VIEW struct.bd 1187 GRAPHIC 328,0 621 0 1188 DESIGN @f@a@d_main 1189 VIEW struct.bd 1190 GRAPHIC 322,0 622 0 1191 DESIGN @f@a@d_main 1192 VIEW struct.bd 1193 GRAPHIC 2299,0 623 0 1194 DESIGN @f@a@d_main 1195 VIEW struct.bd 1196 GRAPHIC 2576,0 624 0 1197 DESIGN @f@a@d_main 1198 VIEW struct.bd 1199 GRAPHIC 2582,0 625 0 1200 DESIGN @f@a@d_main 1201 VIEW struct.bd 1202 GRAPHIC 10467,0 626 0 1203 DESIGN @f@a@d_main 1204 VIEW struct.bd 1205 GRAPHIC 2588,0 627 0 1206 DESIGN @f@a@d_main 1207 VIEW struct.bd 1208 GRAPHIC 5184,0 628 0 1209 DESIGN @f@a@d_main 1210 VIEW struct.bd 1211 GRAPHIC 5745,0 629 0 1212 DESIGN @f@a@d_main 1213 VIEW struct.bd 1214 GRAPHIC 2594,0 630 0 1215 DESIGN @f@a@d_main 1216 VIEW struct.bd 1217 GRAPHIC 5190,0 631 0 1218 DESIGN @f@a@d_main 1219 VIEW struct.bd 1220 GRAPHIC 5404,0 632 0 1221 DESIGN @f@a@d_main 1222 VIEW struct.bd 1223 GRAPHIC 6018,0 633 0 1224 DESIGN @f@a@d_main 1225 VIEW struct.bd 1226 GRAPHIC 6002,0 634 0 1227 DESIGN @f@a@d_main 1228 VIEW struct.bd 1229 GRAPHIC 6008,0 635 0 1230 DESIGN @f@a@d_main 1231 VIEW struct.bd 1232 GRAPHIC 5138,0 636 0 1233 DESIGN @f@a@d_main 1234 VIEW struct.bd 1235 GRAPHIC 2600,0 637 0 1236 DESIGN @f@a@d_main 1237 VIEW struct.bd 1238 GRAPHIC 5480,0 638 0 1239 DESIGN @f@a@d_main 1240 VIEW struct.bd 1241 GRAPHIC 5474,0 639 0 1242 DESIGN @f@a@d_main 1243 VIEW struct.bd 1244 GRAPHIC 6064,0 640 0 1245 DESIGN @f@a@d_main 1246 VIEW struct.bd 1247 GRAPHIC 2642,0 641 0 1248 DESIGN @f@a@d_main 1249 VIEW struct.bd 1250 GRAPHIC 1411,0 642 0 1251 DESIGN @f@a@d_main 1252 VIEW struct.bd 1253 GRAPHIC 1682,0 643 0 1254 DESIGN @f@a@d_main 1255 VIEW struct.bd 1256 GRAPHIC 1983,0 644 0 1257 DESIGN @f@a@d_main 1258 VIEW struct.bd 1259 GRAPHIC 15494,0 645 0 1260 DESIGN @f@a@d_main 1261 VIEW struct.bd 1262 GRAPHIC 5950,0 646 0 1263 DESIGN @f@a@d_main 1264 VIEW struct.bd 1265 GRAPHIC 5962,0 647 0 1266 DESIGN @f@a@d_main 1267 VIEW struct.bd 1268 GRAPHIC 5626,0 648 0 1269 DESIGN @f@a@d_main 1270 VIEW struct.bd 1271 GRAPHIC 2778,0 649 0 1272 DESIGN @f@a@d_main 1273 VIEW struct.bd 1274 GRAPHIC 9006,0 650 0 1275 DESIGN @f@a@d_main 1276 VIEW struct.bd 1277 GRAPHIC 5634,0 651 0 1278 DESIGN @f@a@d_main 1279 VIEW struct.bd 1280 GRAPHIC 4537,0 652 0 1281 DESIGN @f@a@d_main 1282 VIEW struct.bd 1283 GRAPHIC 12649,0 653 0 1284 DESIGN @f@a@d_main 1285 VIEW struct.bd 1286 GRAPHIC 12655,0 654 0 1287 DESIGN @f@a@d_main 1288 VIEW struct.bd 1289 GRAPHIC 4401,0 655 0 1290 DESIGN @f@a@d_main 1291 VIEW struct.bd 1292 GRAPHIC 4419,0 656 0 1344 1293 DESIGN @f@a@d_main 1345 1294 VIEW struct.bd … … 1347 1296 DESIGN @f@a@d_main 1348 1297 VIEW struct.bd 1349 GRAPHIC 10310,0 658 0 1350 DESIGN @f@a@d_main 1351 VIEW struct.bd 1352 GRAPHIC 10304,0 659 0 1353 DESIGN @f@a@d_main 1354 VIEW struct.bd 1355 GRAPHIC 10316,0 660 0 1356 DESIGN @f@a@d_main 1357 VIEW struct.bd 1358 GRAPHIC 10322,0 661 0 1359 DESIGN @f@a@d_main 1360 VIEW struct.bd 1361 GRAPHIC 4948,0 662 0 1362 DESIGN @f@a@d_main 1363 VIEW struct.bd 1364 GRAPHIC 10010,0 663 0 1365 DESIGN @f@a@d_main 1366 VIEW struct.bd 1367 GRAPHIC 11209,0 665 0 1368 DESIGN @f@a@d_main 1369 VIEW struct.bd 1370 GRAPHIC 11216,0 666 1 1371 DESIGN @f@a@d_main 1372 VIEW struct.bd 1373 GRAPHIC 10699,0 672 0 1374 DESIGN @f@a@d_main 1375 VIEW struct.bd 1376 GRAPHIC 10723,0 673 0 1377 DESIGN @f@a@d_main 1378 VIEW struct.bd 1379 GRAPHIC 10737,0 674 0 1380 DESIGN @f@a@d_main 1381 VIEW struct.bd 1382 GRAPHIC 10751,0 675 0 1383 DESIGN @f@a@d_main 1384 VIEW struct.bd 1385 GRAPHIC 12707,0 676 0 1386 DESIGN @f@a@d_main 1387 VIEW struct.bd 1388 GRAPHIC 10707,0 677 0 1389 DESIGN @f@a@d_main 1390 VIEW struct.bd 1391 GRAPHIC 10685,0 678 0 1392 DESIGN @f@a@d_main 1393 VIEW struct.bd 1394 GRAPHIC 10691,0 679 0 1395 DESIGN @f@a@d_main 1396 VIEW struct.bd 1397 GRAPHIC 2311,0 681 0 1398 DESIGN @f@a@d_main 1399 VIEW struct.bd 1400 GRAPHIC 2318,0 682 1 1401 DESIGN @f@a@d_main 1402 VIEW struct.bd 1403 GRAPHIC 6082,0 687 0 1404 DESIGN @f@a@d_main 1405 VIEW struct.bd 1406 GRAPHIC 2588,0 688 0 1407 DESIGN @f@a@d_main 1408 VIEW struct.bd 1409 GRAPHIC 2582,0 689 0 1410 DESIGN @f@a@d_main 1411 VIEW struct.bd 1412 GRAPHIC 10467,0 690 0 1413 DESIGN @f@a@d_main 1414 VIEW struct.bd 1415 GRAPHIC 5168,0 691 0 1416 DESIGN @f@a@d_main 1417 VIEW struct.bd 1418 GRAPHIC 2576,0 692 0 1419 DESIGN @f@a@d_main 1420 VIEW struct.bd 1421 GRAPHIC 2594,0 693 0 1422 DESIGN @f@a@d_main 1423 VIEW struct.bd 1424 GRAPHIC 6018,0 694 0 1425 DESIGN @f@a@d_main 1426 VIEW struct.bd 1427 GRAPHIC 2600,0 695 0 1428 DESIGN @f@a@d_main 1429 VIEW struct.bd 1430 GRAPHIC 2642,0 696 0 1431 DESIGN @f@a@d_main 1432 VIEW struct.bd 1433 GRAPHIC 2488,0 697 0 1434 DESIGN @f@a@d_main 1435 VIEW struct.bd 1436 GRAPHIC 2482,0 698 0 1437 DESIGN @f@a@d_main 1438 VIEW struct.bd 1439 GRAPHIC 2494,0 699 0 1440 DESIGN @f@a@d_main 1441 VIEW struct.bd 1442 GRAPHIC 2476,0 700 0 1443 DESIGN @f@a@d_main 1444 VIEW struct.bd 1445 GRAPHIC 2506,0 701 0 1446 DESIGN @f@a@d_main 1447 VIEW struct.bd 1448 GRAPHIC 2500,0 702 0 1449 DESIGN @f@a@d_main 1450 VIEW struct.bd 1451 GRAPHIC 2470,0 703 0 1452 DESIGN @f@a@d_main 1453 VIEW struct.bd 1454 GRAPHIC 8416,0 704 0 1455 DESIGN @f@a@d_main 1456 VIEW struct.bd 1457 GRAPHIC 2299,0 705 0 1458 DESIGN @f@a@d_main 1459 VIEW struct.bd 1460 GRAPHIC 5793,0 707 0 1461 DESIGN @f@a@d_main 1462 VIEW struct.bd 1463 GRAPHIC 5805,0 709 0 1464 DESIGN @f@a@d_main 1465 VIEW struct.bd 1466 GRAPHIC 5745,0 710 0 1467 DESIGN @f@a@d_main 1468 VIEW struct.bd 1469 GRAPHIC 5146,0 711 0 1470 DESIGN @f@a@d_main 1471 VIEW struct.bd 1472 GRAPHIC 5404,0 712 0 1473 DESIGN @f@a@d_main 1474 VIEW struct.bd 1475 GRAPHIC 6008,0 713 0 1476 DESIGN @f@a@d_main 1477 VIEW struct.bd 1478 GRAPHIC 5829,0 714 0 1479 DESIGN @f@a@d_main 1480 VIEW struct.bd 1481 GRAPHIC 6160,0 715 0 1482 DESIGN @f@a@d_main 1483 VIEW struct.bd 1484 GRAPHIC 8732,0 716 0 1485 DESIGN @f@a@d_main 1486 VIEW struct.bd 1487 GRAPHIC 5480,0 717 0 1488 DESIGN @f@a@d_main 1489 VIEW struct.bd 1490 GRAPHIC 5837,0 718 0 1491 DESIGN @f@a@d_main 1492 VIEW struct.bd 1493 GRAPHIC 5474,0 719 0 1494 DESIGN @f@a@d_main 1495 VIEW struct.bd 1496 GRAPHIC 5821,0 720 0 1497 DESIGN @f@a@d_main 1498 VIEW struct.bd 1499 GRAPHIC 1768,0 722 0 1500 DESIGN @f@a@d_main 1501 VIEW struct.bd 1502 GRAPHIC 1983,0 724 0 1503 DESIGN @f@a@d_main 1504 VIEW struct.bd 1505 GRAPHIC 10439,0 725 0 1506 DESIGN @f@a@d_main 1507 VIEW struct.bd 1508 GRAPHIC 6276,0 726 0 1509 DESIGN @f@a@d_main 1510 VIEW struct.bd 1511 GRAPHIC 12625,0 728 0 1512 DESIGN @f@a@d_main 1513 VIEW struct.bd 1514 GRAPHIC 12687,0 730 0 1515 DESIGN @f@a@d_main 1516 VIEW struct.bd 1517 GRAPHIC 12643,0 731 0 1518 DESIGN @f@a@d_main 1519 VIEW struct.bd 1520 GRAPHIC 12635,0 732 0 1521 DESIGN @f@a@d_main 1522 VIEW struct.bd 1523 GRAPHIC 6540,0 733 0 1524 DESIGN @f@a@d_main 1525 VIEW struct.bd 1526 GRAPHIC 12649,0 734 0 1527 DESIGN @f@a@d_main 1528 VIEW struct.bd 1529 GRAPHIC 12655,0 735 0 1530 DESIGN @f@a@d_main 1531 VIEW struct.bd 1532 GRAPHIC 1606,0 737 0 1533 DESIGN @f@a@d_main 1534 VIEW struct.bd 1535 GRAPHIC 1613,0 738 1 1536 DESIGN @f@a@d_main 1537 VIEW struct.bd 1538 GRAPHIC 3888,0 742 0 1539 DESIGN @f@a@d_main 1540 VIEW struct.bd 1541 GRAPHIC 376,0 743 0 1542 DESIGN @f@a@d_main 1543 VIEW struct.bd 1544 GRAPHIC 384,0 744 0 1545 DESIGN @f@a@d_main 1546 VIEW struct.bd 1547 GRAPHIC 392,0 745 0 1548 DESIGN @f@a@d_main 1549 VIEW struct.bd 1550 GRAPHIC 400,0 746 0 1551 DESIGN @f@a@d_main 1552 VIEW struct.bd 1553 GRAPHIC 408,0 747 0 1554 DESIGN @f@a@d_main 1555 VIEW struct.bd 1556 GRAPHIC 5222,0 748 0 1557 DESIGN @f@a@d_main 1558 VIEW struct.bd 1559 GRAPHIC 424,0 749 0 1560 DESIGN @f@a@d_main 1561 VIEW struct.bd 1562 GRAPHIC 432,0 750 0 1563 DESIGN @f@a@d_main 1564 VIEW struct.bd 1565 GRAPHIC 2482,0 751 0 1566 DESIGN @f@a@d_main 1567 VIEW struct.bd 1568 GRAPHIC 2488,0 752 0 1569 DESIGN @f@a@d_main 1570 VIEW struct.bd 1571 GRAPHIC 370,0 753 0 1572 DESIGN @f@a@d_main 1573 VIEW struct.bd 1574 GRAPHIC 364,0 754 0 1575 DESIGN @f@a@d_main 1576 VIEW struct.bd 1577 GRAPHIC 2476,0 755 0 1578 DESIGN @f@a@d_main 1579 VIEW struct.bd 1580 GRAPHIC 8416,0 756 0 1581 DESIGN @f@a@d_main 1582 VIEW struct.bd 1583 GRAPHIC 2470,0 757 0 1584 DESIGN @f@a@d_main 1585 VIEW struct.bd 1586 GRAPHIC 2506,0 758 0 1587 DESIGN @f@a@d_main 1588 VIEW struct.bd 1589 GRAPHIC 2500,0 759 0 1590 DESIGN @f@a@d_main 1591 VIEW struct.bd 1592 GRAPHIC 2494,0 760 0 1593 DESIGN @f@a@d_main 1594 VIEW struct.bd 1595 GRAPHIC 10266,0 761 0 1596 DESIGN @f@a@d_main 1597 VIEW struct.bd 1598 GRAPHIC 13159,0 762 0 1599 DESIGN @f@a@d_main 1600 VIEW struct.bd 1601 GRAPHIC 13165,0 763 0 1602 DESIGN @f@a@d_main 1603 VIEW struct.bd 1604 GRAPHIC 5950,0 764 0 1605 DESIGN @f@a@d_main 1606 VIEW struct.bd 1607 GRAPHIC 5962,0 765 0 1608 DESIGN @f@a@d_main 1609 VIEW struct.bd 1610 GRAPHIC 5090,0 766 0 1611 DESIGN @f@a@d_main 1612 VIEW struct.bd 1613 GRAPHIC 5114,0 767 0 1614 DESIGN @f@a@d_main 1615 VIEW struct.bd 1616 GRAPHIC 5122,0 768 0 1617 DESIGN @f@a@d_main 1618 VIEW struct.bd 1619 GRAPHIC 5130,0 769 0 1620 DESIGN @f@a@d_main 1621 VIEW struct.bd 1622 GRAPHIC 10194,0 770 0 1623 DESIGN @f@a@d_main 1624 VIEW struct.bd 1625 GRAPHIC 10202,0 771 0 1626 DESIGN @f@a@d_main 1627 VIEW struct.bd 1628 GRAPHIC 5106,0 772 0 1629 DESIGN @f@a@d_main 1630 VIEW struct.bd 1631 GRAPHIC 13695,0 773 0 1632 DESIGN @f@a@d_main 1633 VIEW struct.bd 1634 GRAPHIC 13921,0 774 0 1635 DESIGN @f@a@d_main 1636 VIEW struct.bd 1637 GRAPHIC 13929,0 775 0 1638 DESIGN @f@a@d_main 1639 VIEW struct.bd 1640 GRAPHIC 15071,0 776 0 1641 DESIGN @f@a@d_main 1642 VIEW struct.bd 1643 GRAPHIC 6452,0 777 0 1644 DESIGN @f@a@d_main 1645 VIEW struct.bd 1646 GRAPHIC 8752,0 778 0 1647 DESIGN @f@a@d_main 1648 VIEW struct.bd 1649 GRAPHIC 9233,0 779 0 1650 DESIGN @f@a@d_main 1651 VIEW struct.bd 1652 GRAPHIC 9241,0 780 0 1653 DESIGN @f@a@d_main 1654 VIEW struct.bd 1655 GRAPHIC 9943,0 781 0 1656 DESIGN @f@a@d_main 1657 VIEW struct.bd 1658 GRAPHIC 9951,0 782 0 1659 DESIGN @f@a@d_main 1660 VIEW struct.bd 1661 GRAPHIC 11858,0 783 0 1662 DESIGN @f@a@d_main 1663 VIEW struct.bd 1664 GRAPHIC 10637,0 784 0 1665 DESIGN @f@a@d_main 1666 VIEW struct.bd 1667 GRAPHIC 10629,0 785 0 1668 DESIGN @f@a@d_main 1669 VIEW struct.bd 1670 GRAPHIC 6276,0 789 0 1671 DESIGN @f@a@d_main 1672 VIEW struct.bd 1673 GRAPHIC 3888,0 790 0 1674 DESIGN @f@a@d_main 1675 VIEW struct.bd 1676 GRAPHIC 15138,0 791 0 1677 DESIGN @f@a@d_main 1678 VIEW struct.bd 1679 GRAPHIC 15130,0 792 0 1680 DESIGN @f@a@d_main 1681 VIEW struct.bd 1682 NO_GRAPHIC 794 1298 GRAPHIC 10304,0 658 0 1299 DESIGN @f@a@d_main 1300 VIEW struct.bd 1301 GRAPHIC 10316,0 659 0 1302 DESIGN @f@a@d_main 1303 VIEW struct.bd 1304 GRAPHIC 10310,0 660 0 1305 DESIGN @f@a@d_main 1306 VIEW struct.bd 1307 GRAPHIC 4743,0 661 0 1308 DESIGN @f@a@d_main 1309 VIEW struct.bd 1310 GRAPHIC 4407,0 662 0 1311 DESIGN @f@a@d_main 1312 VIEW struct.bd 1313 GRAPHIC 11405,0 663 0 1314 DESIGN @f@a@d_main 1315 VIEW struct.bd 1316 GRAPHIC 4903,0 665 0 1317 DESIGN @f@a@d_main 1318 VIEW struct.bd 1319 GRAPHIC 4757,0 667 0 1320 DESIGN @f@a@d_main 1321 VIEW struct.bd 1322 GRAPHIC 4401,0 668 0 1323 DESIGN @f@a@d_main 1324 VIEW struct.bd 1325 GRAPHIC 4419,0 669 0 1326 DESIGN @f@a@d_main 1327 VIEW struct.bd 1328 GRAPHIC 4671,0 670 0 1329 DESIGN @f@a@d_main 1330 VIEW struct.bd 1331 GRAPHIC 4679,0 671 0 1332 DESIGN @f@a@d_main 1333 VIEW struct.bd 1334 GRAPHIC 4687,0 672 0 1335 DESIGN @f@a@d_main 1336 VIEW struct.bd 1337 GRAPHIC 4695,0 673 0 1338 DESIGN @f@a@d_main 1339 VIEW struct.bd 1340 GRAPHIC 4407,0 674 0 1341 DESIGN @f@a@d_main 1342 VIEW struct.bd 1343 GRAPHIC 4743,0 675 0 1344 DESIGN @f@a@d_main 1345 VIEW struct.bd 1346 GRAPHIC 10298,0 676 0 1347 DESIGN @f@a@d_main 1348 VIEW struct.bd 1349 GRAPHIC 10310,0 677 0 1350 DESIGN @f@a@d_main 1351 VIEW struct.bd 1352 GRAPHIC 10304,0 678 0 1353 DESIGN @f@a@d_main 1354 VIEW struct.bd 1355 GRAPHIC 10316,0 679 0 1356 DESIGN @f@a@d_main 1357 VIEW struct.bd 1358 GRAPHIC 10322,0 680 0 1359 DESIGN @f@a@d_main 1360 VIEW struct.bd 1361 GRAPHIC 4948,0 681 0 1362 DESIGN @f@a@d_main 1363 VIEW struct.bd 1364 GRAPHIC 10010,0 682 0 1365 DESIGN @f@a@d_main 1366 VIEW struct.bd 1367 GRAPHIC 11209,0 684 0 1368 DESIGN @f@a@d_main 1369 VIEW struct.bd 1370 GRAPHIC 11216,0 685 1 1371 DESIGN @f@a@d_main 1372 VIEW struct.bd 1373 GRAPHIC 10699,0 691 0 1374 DESIGN @f@a@d_main 1375 VIEW struct.bd 1376 GRAPHIC 10723,0 692 0 1377 DESIGN @f@a@d_main 1378 VIEW struct.bd 1379 GRAPHIC 10737,0 693 0 1380 DESIGN @f@a@d_main 1381 VIEW struct.bd 1382 GRAPHIC 10751,0 694 0 1383 DESIGN @f@a@d_main 1384 VIEW struct.bd 1385 GRAPHIC 12707,0 695 0 1386 DESIGN @f@a@d_main 1387 VIEW struct.bd 1388 GRAPHIC 10707,0 696 0 1389 DESIGN @f@a@d_main 1390 VIEW struct.bd 1391 GRAPHIC 10685,0 697 0 1392 DESIGN @f@a@d_main 1393 VIEW struct.bd 1394 GRAPHIC 10691,0 698 0 1395 DESIGN @f@a@d_main 1396 VIEW struct.bd 1397 GRAPHIC 2311,0 700 0 1398 DESIGN @f@a@d_main 1399 VIEW struct.bd 1400 GRAPHIC 2318,0 701 1 1401 DESIGN @f@a@d_main 1402 VIEW struct.bd 1403 GRAPHIC 15379,0 706 0 1404 DESIGN @f@a@d_main 1405 VIEW struct.bd 1406 GRAPHIC 2588,0 707 0 1407 DESIGN @f@a@d_main 1408 VIEW struct.bd 1409 GRAPHIC 2582,0 708 0 1410 DESIGN @f@a@d_main 1411 VIEW struct.bd 1412 GRAPHIC 10467,0 709 0 1413 DESIGN @f@a@d_main 1414 VIEW struct.bd 1415 GRAPHIC 5168,0 710 0 1416 DESIGN @f@a@d_main 1417 VIEW struct.bd 1418 GRAPHIC 2576,0 711 0 1419 DESIGN @f@a@d_main 1420 VIEW struct.bd 1421 GRAPHIC 2594,0 712 0 1422 DESIGN @f@a@d_main 1423 VIEW struct.bd 1424 GRAPHIC 6018,0 713 0 1425 DESIGN @f@a@d_main 1426 VIEW struct.bd 1427 GRAPHIC 2600,0 714 0 1428 DESIGN @f@a@d_main 1429 VIEW struct.bd 1430 GRAPHIC 2642,0 715 0 1431 DESIGN @f@a@d_main 1432 VIEW struct.bd 1433 GRAPHIC 2488,0 716 0 1434 DESIGN @f@a@d_main 1435 VIEW struct.bd 1436 GRAPHIC 2482,0 717 0 1437 DESIGN @f@a@d_main 1438 VIEW struct.bd 1439 GRAPHIC 2494,0 718 0 1440 DESIGN @f@a@d_main 1441 VIEW struct.bd 1442 GRAPHIC 2476,0 719 0 1443 DESIGN @f@a@d_main 1444 VIEW struct.bd 1445 GRAPHIC 2506,0 720 0 1446 DESIGN @f@a@d_main 1447 VIEW struct.bd 1448 GRAPHIC 2500,0 721 0 1449 DESIGN @f@a@d_main 1450 VIEW struct.bd 1451 GRAPHIC 2470,0 722 0 1452 DESIGN @f@a@d_main 1453 VIEW struct.bd 1454 GRAPHIC 8416,0 723 0 1455 DESIGN @f@a@d_main 1456 VIEW struct.bd 1457 GRAPHIC 2299,0 724 0 1458 DESIGN @f@a@d_main 1459 VIEW struct.bd 1460 GRAPHIC 5793,0 726 0 1461 DESIGN @f@a@d_main 1462 VIEW struct.bd 1463 GRAPHIC 5805,0 728 0 1464 DESIGN @f@a@d_main 1465 VIEW struct.bd 1466 GRAPHIC 5745,0 729 0 1467 DESIGN @f@a@d_main 1468 VIEW struct.bd 1469 GRAPHIC 5146,0 730 0 1470 DESIGN @f@a@d_main 1471 VIEW struct.bd 1472 GRAPHIC 5404,0 731 0 1473 DESIGN @f@a@d_main 1474 VIEW struct.bd 1475 GRAPHIC 6008,0 732 0 1476 DESIGN @f@a@d_main 1477 VIEW struct.bd 1478 GRAPHIC 5829,0 733 0 1479 DESIGN @f@a@d_main 1480 VIEW struct.bd 1481 GRAPHIC 6160,0 734 0 1482 DESIGN @f@a@d_main 1483 VIEW struct.bd 1484 GRAPHIC 8732,0 735 0 1485 DESIGN @f@a@d_main 1486 VIEW struct.bd 1487 GRAPHIC 5480,0 736 0 1488 DESIGN @f@a@d_main 1489 VIEW struct.bd 1490 GRAPHIC 5837,0 737 0 1491 DESIGN @f@a@d_main 1492 VIEW struct.bd 1493 GRAPHIC 5474,0 738 0 1494 DESIGN @f@a@d_main 1495 VIEW struct.bd 1496 GRAPHIC 5821,0 739 0 1497 DESIGN @f@a@d_main 1498 VIEW struct.bd 1499 GRAPHIC 1768,0 741 0 1500 DESIGN @f@a@d_main 1501 VIEW struct.bd 1502 GRAPHIC 1983,0 743 0 1503 DESIGN @f@a@d_main 1504 VIEW struct.bd 1505 GRAPHIC 15498,0 744 0 1506 DESIGN @f@a@d_main 1507 VIEW struct.bd 1508 GRAPHIC 6276,0 745 0 1509 DESIGN @f@a@d_main 1510 VIEW struct.bd 1511 GRAPHIC 12625,0 747 0 1512 DESIGN @f@a@d_main 1513 VIEW struct.bd 1514 GRAPHIC 12687,0 749 0 1515 DESIGN @f@a@d_main 1516 VIEW struct.bd 1517 GRAPHIC 12643,0 750 0 1518 DESIGN @f@a@d_main 1519 VIEW struct.bd 1520 GRAPHIC 15494,0 751 0 1521 DESIGN @f@a@d_main 1522 VIEW struct.bd 1523 GRAPHIC 6540,0 752 0 1524 DESIGN @f@a@d_main 1525 VIEW struct.bd 1526 GRAPHIC 12649,0 753 0 1527 DESIGN @f@a@d_main 1528 VIEW struct.bd 1529 GRAPHIC 12655,0 754 0 1530 DESIGN @f@a@d_main 1531 VIEW struct.bd 1532 GRAPHIC 1606,0 756 0 1533 DESIGN @f@a@d_main 1534 VIEW struct.bd 1535 GRAPHIC 1613,0 757 1 1536 DESIGN @f@a@d_main 1537 VIEW struct.bd 1538 GRAPHIC 3888,0 761 0 1539 DESIGN @f@a@d_main 1540 VIEW struct.bd 1541 GRAPHIC 376,0 762 0 1542 DESIGN @f@a@d_main 1543 VIEW struct.bd 1544 GRAPHIC 384,0 763 0 1545 DESIGN @f@a@d_main 1546 VIEW struct.bd 1547 GRAPHIC 392,0 764 0 1548 DESIGN @f@a@d_main 1549 VIEW struct.bd 1550 GRAPHIC 400,0 765 0 1551 DESIGN @f@a@d_main 1552 VIEW struct.bd 1553 GRAPHIC 408,0 766 0 1554 DESIGN @f@a@d_main 1555 VIEW struct.bd 1556 GRAPHIC 5222,0 767 0 1557 DESIGN @f@a@d_main 1558 VIEW struct.bd 1559 GRAPHIC 424,0 768 0 1560 DESIGN @f@a@d_main 1561 VIEW struct.bd 1562 GRAPHIC 432,0 769 0 1563 DESIGN @f@a@d_main 1564 VIEW struct.bd 1565 GRAPHIC 2482,0 770 0 1566 DESIGN @f@a@d_main 1567 VIEW struct.bd 1568 GRAPHIC 2488,0 771 0 1569 DESIGN @f@a@d_main 1570 VIEW struct.bd 1571 GRAPHIC 370,0 772 0 1572 DESIGN @f@a@d_main 1573 VIEW struct.bd 1574 GRAPHIC 364,0 773 0 1575 DESIGN @f@a@d_main 1576 VIEW struct.bd 1577 GRAPHIC 2476,0 774 0 1578 DESIGN @f@a@d_main 1579 VIEW struct.bd 1580 GRAPHIC 8416,0 775 0 1581 DESIGN @f@a@d_main 1582 VIEW struct.bd 1583 GRAPHIC 2470,0 776 0 1584 DESIGN @f@a@d_main 1585 VIEW struct.bd 1586 GRAPHIC 2506,0 777 0 1587 DESIGN @f@a@d_main 1588 VIEW struct.bd 1589 GRAPHIC 2500,0 778 0 1590 DESIGN @f@a@d_main 1591 VIEW struct.bd 1592 GRAPHIC 2494,0 779 0 1593 DESIGN @f@a@d_main 1594 VIEW struct.bd 1595 GRAPHIC 10266,0 780 0 1596 DESIGN @f@a@d_main 1597 VIEW struct.bd 1598 GRAPHIC 13159,0 781 0 1599 DESIGN @f@a@d_main 1600 VIEW struct.bd 1601 GRAPHIC 13165,0 782 0 1602 DESIGN @f@a@d_main 1603 VIEW struct.bd 1604 GRAPHIC 5950,0 783 0 1605 DESIGN @f@a@d_main 1606 VIEW struct.bd 1607 GRAPHIC 5962,0 784 0 1608 DESIGN @f@a@d_main 1609 VIEW struct.bd 1610 GRAPHIC 5090,0 785 0 1611 DESIGN @f@a@d_main 1612 VIEW struct.bd 1613 GRAPHIC 5114,0 786 0 1614 DESIGN @f@a@d_main 1615 VIEW struct.bd 1616 GRAPHIC 5122,0 787 0 1617 DESIGN @f@a@d_main 1618 VIEW struct.bd 1619 GRAPHIC 5130,0 788 0 1620 DESIGN @f@a@d_main 1621 VIEW struct.bd 1622 GRAPHIC 10194,0 789 0 1623 DESIGN @f@a@d_main 1624 VIEW struct.bd 1625 GRAPHIC 10202,0 790 0 1626 DESIGN @f@a@d_main 1627 VIEW struct.bd 1628 GRAPHIC 5106,0 791 0 1629 DESIGN @f@a@d_main 1630 VIEW struct.bd 1631 GRAPHIC 13695,0 792 0 1632 DESIGN @f@a@d_main 1633 VIEW struct.bd 1634 GRAPHIC 13921,0 793 0 1635 DESIGN @f@a@d_main 1636 VIEW struct.bd 1637 GRAPHIC 13929,0 794 0 1638 DESIGN @f@a@d_main 1639 VIEW struct.bd 1640 GRAPHIC 15071,0 795 0 1641 DESIGN @f@a@d_main 1642 VIEW struct.bd 1643 GRAPHIC 6452,0 796 0 1644 DESIGN @f@a@d_main 1645 VIEW struct.bd 1646 GRAPHIC 8752,0 797 0 1647 DESIGN @f@a@d_main 1648 VIEW struct.bd 1649 GRAPHIC 9233,0 798 0 1650 DESIGN @f@a@d_main 1651 VIEW struct.bd 1652 GRAPHIC 9241,0 799 0 1653 DESIGN @f@a@d_main 1654 VIEW struct.bd 1655 GRAPHIC 9943,0 800 0 1656 DESIGN @f@a@d_main 1657 VIEW struct.bd 1658 GRAPHIC 9951,0 801 0 1659 DESIGN @f@a@d_main 1660 VIEW struct.bd 1661 GRAPHIC 11858,0 802 0 1662 DESIGN @f@a@d_main 1663 VIEW struct.bd 1664 GRAPHIC 10637,0 803 0 1665 DESIGN @f@a@d_main 1666 VIEW struct.bd 1667 GRAPHIC 10629,0 804 0 1668 DESIGN @f@a@d_main 1669 VIEW struct.bd 1670 GRAPHIC 6276,0 808 0 1671 DESIGN @f@a@d_main 1672 VIEW struct.bd 1673 GRAPHIC 3888,0 809 0 1674 DESIGN @f@a@d_main 1675 VIEW struct.bd 1676 GRAPHIC 15138,0 810 0 1677 DESIGN @f@a@d_main 1678 VIEW struct.bd 1679 GRAPHIC 15130,0 811 0 1680 DESIGN @f@a@d_main 1681 VIEW struct.bd 1682 NO_GRAPHIC 813 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd
r10138 r10155 26 26 library "IEEE" 27 27 unitName "std_logic_signed" 28 ) 29 (DmPackageRef 30 library "UNISIM" 31 unitName "VComponents" 28 32 ) 29 33 ] … … 278 282 uid 15058,0 279 283 ) 284 (Instance 285 name "U_0" 286 duLibraryName "FACT_FAD_lib" 287 duName "dna_gen" 288 elements [ 289 ] 290 mwi 0 291 uid 15728,0 292 ) 280 293 ] 281 294 libraryRefs [ … … 333 346 (vvPair 334 347 variable "date" 335 value " 08.02.2011"348 value "15.02.2011" 336 349 ) 337 350 (vvPair … … 345 358 (vvPair 346 359 variable "dd" 347 value " 08"360 value "15" 348 361 ) 349 362 (vvPair … … 485 498 (vvPair 486 499 variable "time" 487 value " 11:06:22"500 value "09:27:14" 488 501 ) 489 502 (vvPair … … 1363 1376 preAdd 0 1364 1377 posAdd 0 1365 o 2 41378 o 25 1366 1379 suid 9,0 1367 1380 ) … … 1369 1382 ) 1370 1383 *29 (CptPort 1371 uid 1388,01372 ps "OnEdgeStrategy"1373 shape (Triangle1374 uid 1389,01375 ro 901376 va (VaSet1377 vasetType 11378 fg "0,65535,0"1379 )1380 xt "-21750,69625,-21000,70375"1381 )1382 tg (CPTG1383 uid 1390,01384 ps "CptPortTextPlaceStrategy"1385 stg "VerticalLayoutStrategy"1386 f (Text1387 uid 1391,01388 va (VaSet1389 )1390 xt "-20000,69500,-13200,70500"1391 st "trigger_id : (47:0)"1392 blo "-20000,70300"1393 )1394 )1395 thePort (LogicalPort1396 decl (Decl1397 n "trigger_id"1398 t "std_logic_vector"1399 b "(47 downto 0)"1400 preAdd 01401 posAdd 01402 o 261403 suid 10,01404 )1405 )1406 )1407 *30 (CptPort1408 1384 uid 1392,0 1409 1385 ps "OnEdgeStrategy" … … 1436 1412 preAdd 0 1437 1413 posAdd 0 1438 o 2 71414 o 28 1439 1415 suid 11,0 1440 1416 ) 1441 1417 ) 1442 1418 ) 1443 *3 1(CptPort1419 *30 (CptPort 1444 1420 uid 1676,0 1445 1421 ps "OnEdgeStrategy" … … 1471 1447 t "std_logic_vector" 1472 1448 b "(1 downto 0)" 1473 o 2 51449 o 26 1474 1450 suid 12,0 1475 1451 ) 1476 1452 ) 1477 1453 ) 1478 *3 2(CptPort1454 *31 (CptPort 1479 1455 uid 2562,0 1480 1456 ps "OnEdgeStrategy" … … 1511 1487 ) 1512 1488 ) 1513 *3 3(CptPort1489 *32 (CptPort 1514 1490 uid 2566,0 1515 1491 ps "OnEdgeStrategy" … … 1549 1525 ) 1550 1526 ) 1551 *3 4(CptPort1527 *33 (CptPort 1552 1528 uid 2570,0 1553 1529 ps "OnEdgeStrategy" … … 1584 1560 ) 1585 1561 ) 1586 *3 5(CptPort1562 *34 (CptPort 1587 1563 uid 2614,0 1588 1564 ps "OnEdgeStrategy" … … 1619 1595 ) 1620 1596 ) 1621 *3 6(CptPort1597 *35 (CptPort 1622 1598 uid 2624,0 1623 1599 ps "OnEdgeStrategy" … … 1655 1631 ) 1656 1632 ) 1657 *3 7(CptPort1633 *36 (CptPort 1658 1634 uid 2760,0 1659 1635 ps "OnEdgeStrategy" … … 1685 1661 n "adc_oeb" 1686 1662 t "std_logic" 1687 o 3 11663 o 32 1688 1664 suid 23,0 1689 1665 i "'1'" … … 1691 1667 ) 1692 1668 ) 1693 *3 8(CptPort1669 *37 (CptPort 1694 1670 uid 2764,0 1695 1671 ps "OnEdgeStrategy" … … 1721 1697 t "std_logic_vector" 1722 1698 b "(3 downto 0)" 1723 o 3 31699 o 34 1724 1700 suid 24,0 1725 1701 ) 1726 1702 ) 1727 1703 ) 1728 *3 9(CptPort1704 *38 (CptPort 1729 1705 uid 3918,0 1730 1706 ps "OnEdgeStrategy" … … 1758 1734 b "(3 downto 0)" 1759 1735 posAdd 0 1760 o 3 41736 o 35 1761 1737 suid 25,0 1762 1738 i "(others => '0')" … … 1764 1740 ) 1765 1741 ) 1766 * 40(CptPort1742 *39 (CptPort 1767 1743 uid 3922,0 1768 1744 ps "OnEdgeStrategy" … … 1797 1773 preAdd 0 1798 1774 posAdd 0 1799 o 3 71775 o 38 1800 1776 suid 26,0 1801 1777 i "'0'" … … 1803 1779 ) 1804 1780 ) 1805 *4 1(CptPort1781 *40 (CptPort 1806 1782 uid 3930,0 1807 1783 ps "OnEdgeStrategy" … … 1835 1811 prec "-- --" 1836 1812 preAdd 0 1837 o 3 81813 o 39 1838 1814 suid 33,0 1839 1815 i "'0'" … … 1841 1817 ) 1842 1818 ) 1843 *4 2(CptPort1819 *41 (CptPort 1844 1820 uid 3934,0 1845 1821 ps "OnEdgeStrategy" … … 1870 1846 n "drs_read_s_cell_ready" 1871 1847 t "std_logic" 1872 o 4 31848 o 44 1873 1849 suid 34,0 1874 1850 ) 1875 1851 ) 1876 1852 ) 1877 *4 3(CptPort1853 *42 (CptPort 1878 1854 uid 3938,0 1879 1855 ps "OnEdgeStrategy" … … 1904 1880 n "drs_s_cell_array" 1905 1881 t "drs_s_cell_array_type" 1906 o 4 41882 o 45 1907 1883 suid 35,0 1908 1884 ) 1909 1885 ) 1910 1886 ) 1911 *4 4(CptPort1887 *43 (CptPort 1912 1888 uid 4246,0 1913 1889 ps "OnEdgeStrategy" … … 1938 1914 n "adc_data_array" 1939 1915 t "adc_data_array_type" 1940 o 3 01916 o 31 1941 1917 suid 37,0 1942 1918 ) 1943 1919 ) 1944 1920 ) 1945 *4 5(CptPort1921 *44 (CptPort 1946 1922 uid 5174,0 1947 1923 ps "OnEdgeStrategy" … … 1978 1954 ) 1979 1955 ) 1980 *4 6(CptPort1956 *45 (CptPort 1981 1957 uid 5178,0 1982 1958 ps "OnEdgeStrategy" … … 2018 1994 ) 2019 1995 ) 2020 *4 7(CptPort1996 *46 (CptPort 2021 1997 uid 5392,0 2022 1998 ps "OnEdgeStrategy" … … 2053 2029 ) 2054 2030 ) 2055 *4 8(CptPort2031 *47 (CptPort 2056 2032 uid 5396,0 2057 2033 ps "OnEdgeStrategy" … … 2088 2064 ) 2089 2065 ) 2090 *4 9(CptPort2066 *48 (CptPort 2091 2067 uid 5464,0 2092 2068 ps "OnEdgeStrategy" … … 2123 2099 ) 2124 2100 ) 2125 * 50(CptPort2101 *49 (CptPort 2126 2102 uid 5468,0 2127 2103 ps "OnEdgeStrategy" … … 2158 2134 ) 2159 2135 ) 2160 *5 1(CptPort2136 *50 (CptPort 2161 2137 uid 5735,0 2162 2138 ps "OnEdgeStrategy" … … 2198 2174 ) 2199 2175 ) 2200 *5 2(CptPort2176 *51 (CptPort 2201 2177 uid 5739,0 2202 2178 ps "OnEdgeStrategy" … … 2237 2213 ) 2238 2214 ) 2239 *5 3(CptPort2215 *52 (CptPort 2240 2216 uid 5916,0 2241 2217 ps "OnEdgeStrategy" … … 2268 2244 n "config_started" 2269 2245 t "std_logic" 2270 o 292246 o 30 2271 2247 suid 48,0 2272 2248 i "'0'" … … 2274 2250 ) 2275 2251 ) 2276 *5 4(CptPort2252 *53 (CptPort 2277 2253 uid 5920,0 2278 2254 ps "OnEdgeStrategy" … … 2306 2282 prec "-- s_trigger : in std_logic;" 2307 2283 preAdd 0 2308 o 2 82284 o 29 2309 2285 suid 49,0 2310 2286 ) 2311 2287 ) 2312 2288 ) 2313 *5 5(CptPort2289 *54 (CptPort 2314 2290 uid 5974,0 2315 2291 ps "OnEdgeStrategy" … … 2346 2322 ) 2347 2323 ) 2348 *5 6(CptPort2324 *55 (CptPort 2349 2325 uid 5978,0 2350 2326 ps "OnEdgeStrategy" … … 2381 2357 ) 2382 2358 ) 2383 *5 7(CptPort2359 *56 (CptPort 2384 2360 uid 5982,0 2385 2361 ps "OnEdgeStrategy" … … 2416 2392 ) 2417 2393 ) 2418 *5 8(CptPort2394 *57 (CptPort 2419 2395 uid 6060,0 2420 2396 ps "OnEdgeStrategy" … … 2451 2427 ) 2452 2428 ) 2453 *5 9(CptPort2429 *58 (CptPort 2454 2430 uid 9000,0 2455 2431 ps "OnEdgeStrategy" … … 2481 2457 n "adc_clk_en" 2482 2458 t "std_logic" 2483 o 3 22459 o 33 2484 2460 suid 54,0 2485 2461 i "'0'" … … 2487 2463 ) 2488 2464 ) 2489 * 60(CptPort2465 *59 (CptPort 2490 2466 uid 10244,0 2491 2467 ps "OnEdgeStrategy" … … 2518 2494 t "std_logic_vector" 2519 2495 b "(7 downto 0)" 2520 o 4 12496 o 42 2521 2497 suid 56,0 2522 2498 i "(others => '0')" … … 2524 2500 ) 2525 2501 ) 2526 *6 1(CptPort2502 *60 (CptPort 2527 2503 uid 10248,0 2528 2504 ps "OnEdgeStrategy" … … 2554 2530 n "drs_srin_write_8b" 2555 2531 t "std_logic" 2556 o 392532 o 40 2557 2533 suid 57,0 2558 2534 i "'0'" … … 2560 2536 ) 2561 2537 ) 2562 *6 2(CptPort2538 *61 (CptPort 2563 2539 uid 10252,0 2564 2540 ps "OnEdgeStrategy" … … 2589 2565 n "drs_srin_write_ack" 2590 2566 t "std_logic" 2591 o 4 02567 o 41 2592 2568 suid 58,0 2593 2569 ) 2594 2570 ) 2595 2571 ) 2596 *6 3(CptPort2572 *62 (CptPort 2597 2573 uid 10256,0 2598 2574 ps "OnEdgeStrategy" … … 2623 2599 n "drs_srin_write_ready" 2624 2600 t "std_logic" 2625 o 4 22601 o 43 2626 2602 suid 59,0 2627 2603 ) 2628 2604 ) 2629 2605 ) 2630 *6 4(CptPort2606 *63 (CptPort 2631 2607 uid 10260,0 2632 2608 ps "OnEdgeStrategy" … … 2666 2642 ) 2667 2643 ) 2668 *6 5(CptPort2644 *64 (CptPort 2669 2645 uid 11385,0 2670 2646 ps "OnEdgeStrategy" … … 2697 2673 n "drs_readout_started" 2698 2674 t "std_logic" 2699 o 4 52675 o 46 2700 2676 suid 61,0 2701 2677 i "'0'" … … 2703 2679 ) 2704 2680 ) 2705 *6 6(CptPort2681 *65 (CptPort 2706 2682 uid 12597,0 2707 2683 ps "OnEdgeStrategy" … … 2737 2713 preAdd 0 2738 2714 posAdd 0 2739 o 3 52715 o 36 2740 2716 suid 62,0 2741 2717 i "'0'" … … 2743 2719 ) 2744 2720 ) 2745 *6 7(CptPort2721 *66 (CptPort 2746 2722 uid 12601,0 2747 2723 ps "OnEdgeStrategy" … … 2772 2748 n "drs_readout_ready_ack" 2773 2749 t "std_logic" 2774 o 3 62750 o 37 2775 2751 suid 63,0 2752 ) 2753 ) 2754 ) 2755 *67 (CptPort 2756 uid 15740,0 2757 ps "OnEdgeStrategy" 2758 shape (Triangle 2759 uid 15741,0 2760 ro 90 2761 va (VaSet 2762 vasetType 1 2763 fg "0,65535,0" 2764 ) 2765 xt "-21750,69625,-21000,70375" 2766 ) 2767 tg (CPTG 2768 uid 15742,0 2769 ps "CptPortTextPlaceStrategy" 2770 stg "VerticalLayoutStrategy" 2771 f (Text 2772 uid 15743,0 2773 va (VaSet 2774 ) 2775 xt "-20000,69500,-10200,70500" 2776 st "fad_event_counter : (31:0)" 2777 blo "-20000,70300" 2778 ) 2779 ) 2780 thePort (LogicalPort 2781 decl (Decl 2782 n "fad_event_counter" 2783 t "std_logic_vector" 2784 b "(31 downto 0)" 2785 o 27 2786 suid 65,0 2787 ) 2788 ) 2789 ) 2790 *68 (CptPort 2791 uid 15744,0 2792 ps "OnEdgeStrategy" 2793 shape (Triangle 2794 uid 15745,0 2795 ro 90 2796 va (VaSet 2797 vasetType 1 2798 fg "0,65535,0" 2799 ) 2800 xt "-21750,95625,-21000,96375" 2801 ) 2802 tg (CPTG 2803 uid 15746,0 2804 ps "CptPortTextPlaceStrategy" 2805 stg "VerticalLayoutStrategy" 2806 f (Text 2807 uid 15747,0 2808 va (VaSet 2809 ) 2810 xt "-20000,95500,-14500,96500" 2811 st "pll_lock : (3:0)" 2812 blo "-20000,96300" 2813 ) 2814 ) 2815 thePort (LogicalPort 2816 decl (Decl 2817 n "pll_lock" 2818 t "std_logic_vector" 2819 b "( 3 downto 0)" 2820 o 24 2821 suid 64,0 2776 2822 ) 2777 2823 ) … … 2794 2840 stg "VerticalLayoutStrategy" 2795 2841 textVec [ 2796 *6 8(Text2842 *69 (Text 2797 2843 uid 1402,0 2798 2844 va (VaSet … … 2804 2850 tm "BdLibraryNameMgr" 2805 2851 ) 2806 * 69(Text2852 *70 (Text 2807 2853 uid 1403,0 2808 2854 va (VaSet … … 2814 2860 tm "CptNameMgr" 2815 2861 ) 2816 *7 0(Text2862 *71 (Text 2817 2863 uid 1404,0 2818 2864 va (VaSet … … 2867 2913 archFileType "UNKNOWN" 2868 2914 ) 2869 *7 1(Net2915 *72 (Net 2870 2916 uid 1409,0 2871 2917 decl (Decl … … 2886 2932 ) 2887 2933 ) 2888 *7 2(Net2934 *73 (Net 2889 2935 uid 1423,0 2890 2936 decl (Decl … … 2906 2952 ) 2907 2953 ) 2908 *7 3(PortIoIn2954 *74 (PortIoIn 2909 2955 uid 1443,0 2910 2956 shape (CompositeShape … … 2951 2997 ) 2952 2998 ) 2953 *7 4(SaComponent2999 *75 (SaComponent 2954 3000 uid 1606,0 2955 3001 optionalChildren [ 2956 *7 5(CptPort3002 *76 (CptPort 2957 3003 uid 1542,0 2958 3004 ps "OnEdgeStrategy" … … 2990 3036 ) 2991 3037 ) 2992 *7 6(CptPort3038 *77 (CptPort 2993 3039 uid 1546,0 2994 3040 ps "OnEdgeStrategy" … … 3029 3075 ) 3030 3076 ) 3031 *7 7(CptPort3077 *78 (CptPort 3032 3078 uid 1550,0 3033 3079 ps "OnEdgeStrategy" … … 3068 3114 ) 3069 3115 ) 3070 *7 8(CptPort3116 *79 (CptPort 3071 3117 uid 1554,0 3072 3118 ps "OnEdgeStrategy" … … 3107 3153 ) 3108 3154 ) 3109 * 79(CptPort3155 *80 (CptPort 3110 3156 uid 1558,0 3111 3157 ps "OnEdgeStrategy" … … 3146 3192 ) 3147 3193 ) 3148 *8 0(CptPort3194 *81 (CptPort 3149 3195 uid 1562,0 3150 3196 ps "OnEdgeStrategy" … … 3185 3231 ) 3186 3232 ) 3187 *8 1(CptPort3233 *82 (CptPort 3188 3234 uid 1570,0 3189 3235 ps "OnEdgeStrategy" … … 3224 3270 ) 3225 3271 ) 3226 *8 2(CptPort3272 *83 (CptPort 3227 3273 uid 1574,0 3228 3274 ps "OnEdgeStrategy" … … 3261 3307 ) 3262 3308 ) 3263 *8 3(CptPort3309 *84 (CptPort 3264 3310 uid 1578,0 3265 3311 ps "OnEdgeStrategy" … … 3298 3344 ) 3299 3345 ) 3300 *8 4(CptPort3346 *85 (CptPort 3301 3347 uid 1582,0 3302 3348 ps "OnEdgeStrategy" … … 3335 3381 ) 3336 3382 ) 3337 *8 5(CptPort3383 *86 (CptPort 3338 3384 uid 1586,0 3339 3385 ps "OnEdgeStrategy" … … 3372 3418 ) 3373 3419 ) 3374 *8 6(CptPort3420 *87 (CptPort 3375 3421 uid 1590,0 3376 3422 ps "OnEdgeStrategy" … … 3410 3456 ) 3411 3457 ) 3412 *8 7(CptPort3458 *88 (CptPort 3413 3459 uid 1594,0 3414 3460 ps "OnEdgeStrategy" … … 3446 3492 ) 3447 3493 ) 3448 *8 8(CptPort3494 *89 (CptPort 3449 3495 uid 1598,0 3450 3496 ps "OnEdgeStrategy" … … 3484 3530 ) 3485 3531 ) 3486 * 89(CptPort3532 *90 (CptPort 3487 3533 uid 2218,0 3488 3534 ps "OnEdgeStrategy" … … 3520 3566 ) 3521 3567 ) 3522 *9 0(CptPort3568 *91 (CptPort 3523 3569 uid 2222,0 3524 3570 ps "OnEdgeStrategy" … … 3554 3600 ) 3555 3601 ) 3556 *9 1(CptPort3602 *92 (CptPort 3557 3603 uid 2226,0 3558 3604 ps "OnEdgeStrategy" … … 3588 3634 ) 3589 3635 ) 3590 *9 2(CptPort3636 *93 (CptPort 3591 3637 uid 5216,0 3592 3638 ps "OnEdgeStrategy" … … 3627 3673 ) 3628 3674 ) 3629 *9 3(CptPort3675 *94 (CptPort 3630 3676 uid 5275,0 3631 3677 ps "OnEdgeStrategy" … … 3665 3711 ) 3666 3712 ) 3667 *9 4(CptPort3713 *95 (CptPort 3668 3714 uid 5924,0 3669 3715 ps "OnEdgeStrategy" … … 3701 3747 ) 3702 3748 ) 3703 *9 5(CptPort3749 *96 (CptPort 3704 3750 uid 5928,0 3705 3751 ps "OnEdgeStrategy" … … 3737 3783 ) 3738 3784 ) 3739 *9 6(CptPort3785 *97 (CptPort 3740 3786 uid 5932,0 3741 3787 ps "OnEdgeStrategy" … … 3774 3820 ) 3775 3821 ) 3776 *9 7(CptPort3822 *98 (CptPort 3777 3823 uid 5936,0 3778 3824 ps "OnEdgeStrategy" … … 3808 3854 ) 3809 3855 ) 3810 *9 8(CptPort3856 *99 (CptPort 3811 3857 uid 5940,0 3812 3858 ps "OnEdgeStrategy" … … 3844 3890 ) 3845 3891 ) 3846 * 99(CptPort3892 *100 (CptPort 3847 3893 uid 5944,0 3848 3894 ps "OnEdgeStrategy" … … 3882 3928 ) 3883 3929 ) 3884 *10 0(CptPort3930 *101 (CptPort 3885 3931 uid 5970,0 3886 3932 ps "OnEdgeStrategy" … … 3919 3965 ) 3920 3966 ) 3921 *10 1(CptPort3967 *102 (CptPort 3922 3968 uid 6356,0 3923 3969 ps "OnEdgeStrategy" … … 3958 4004 ) 3959 4005 ) 3960 *10 2(CptPort4006 *103 (CptPort 3961 4007 uid 6446,0 3962 4008 ps "OnEdgeStrategy" … … 3998 4044 ) 3999 4045 ) 4000 *10 3(CptPort4046 *104 (CptPort 4001 4047 uid 8406,0 4002 4048 ps "OnEdgeStrategy" … … 4034 4080 ) 4035 4081 ) 4036 *10 4(CptPort4082 *105 (CptPort 4037 4083 uid 8748,0 4038 4084 ps "OnEdgeStrategy" … … 4073 4119 ) 4074 4120 ) 4075 *10 5(CptPort4121 *106 (CptPort 4076 4122 uid 9223,0 4077 4123 ps "OnEdgeStrategy" … … 4112 4158 ) 4113 4159 ) 4114 *10 6(CptPort4160 *107 (CptPort 4115 4161 uid 9227,0 4116 4162 ps "OnEdgeStrategy" … … 4152 4198 ) 4153 4199 ) 4154 *10 7(CptPort4200 *108 (CptPort 4155 4201 uid 9933,0 4156 4202 ps "OnEdgeStrategy" … … 4191 4237 ) 4192 4238 ) 4193 *10 8(CptPort4239 *109 (CptPort 4194 4240 uid 9937,0 4195 4241 ps "OnEdgeStrategy" … … 4230 4276 ) 4231 4277 ) 4232 *1 09(CptPort4278 *110 (CptPort 4233 4279 uid 10212,0 4234 4280 ps "OnEdgeStrategy" … … 4267 4313 ) 4268 4314 ) 4269 *11 0(CptPort4315 *111 (CptPort 4270 4316 uid 10216,0 4271 4317 ps "OnEdgeStrategy" … … 4304 4350 ) 4305 4351 ) 4306 *11 1(CptPort4352 *112 (CptPort 4307 4353 uid 10619,0 4308 4354 ps "OnEdgeStrategy" … … 4340 4386 ) 4341 4387 ) 4342 *11 2(CptPort4388 *113 (CptPort 4343 4389 uid 10623,0 4344 4390 ps "OnEdgeStrategy" … … 4377 4423 ) 4378 4424 ) 4379 *11 3(CptPort4425 *114 (CptPort 4380 4426 uid 11838,0 4381 4427 ps "OnEdgeStrategy" … … 4416 4462 ) 4417 4463 ) 4418 *11 4(CptPort4464 *115 (CptPort 4419 4465 uid 13149,0 4420 4466 ps "OnEdgeStrategy" … … 4452 4498 ) 4453 4499 ) 4454 *11 5(CptPort4500 *116 (CptPort 4455 4501 uid 13153,0 4456 4502 ps "OnEdgeStrategy" … … 4491 4537 ) 4492 4538 ) 4493 *11 6(CptPort4539 *117 (CptPort 4494 4540 uid 13806,0 4495 4541 ps "OnEdgeStrategy" … … 4526 4572 ) 4527 4573 ) 4528 *11 7(CptPort4574 *118 (CptPort 4529 4575 uid 13911,0 4530 4576 ps "OnEdgeStrategy" … … 4561 4607 ) 4562 4608 ) 4563 *11 8(CptPort4609 *119 (CptPort 4564 4610 uid 13915,0 4565 4611 ps "OnEdgeStrategy" … … 4613 4659 stg "VerticalLayoutStrategy" 4614 4660 textVec [ 4615 *1 19(Text4661 *120 (Text 4616 4662 uid 1609,0 4617 4663 va (VaSet … … 4623 4669 tm "BdLibraryNameMgr" 4624 4670 ) 4625 *12 0(Text4671 *121 (Text 4626 4672 uid 1610,0 4627 4673 va (VaSet … … 4633 4679 tm "CptNameMgr" 4634 4680 ) 4635 *12 1(Text4681 *122 (Text 4636 4682 uid 1611,0 4637 4683 va (VaSet … … 4686 4732 archFileType "UNKNOWN" 4687 4733 ) 4688 *12 2(Net4734 *123 (Net 4689 4735 uid 1680,0 4690 4736 decl (Decl … … 4705 4751 ) 4706 4752 ) 4707 *12 3(SaComponent4753 *124 (SaComponent 4708 4754 uid 1768,0 4709 4755 optionalChildren [ 4710 *12 4(CptPort4756 *125 (CptPort 4711 4757 uid 1760,0 4712 4758 ps "OnEdgeStrategy" … … 4729 4775 ) 4730 4776 xt "-48800,68500,-42000,69500" 4731 st "trigger_id : ( 47:0)"4777 st "trigger_id : (31:0)" 4732 4778 ju 2 4733 4779 blo "-42000,69300" … … 4740 4786 n "trigger_id" 4741 4787 t "std_logic_vector" 4742 b "( 47downto 0)"4788 b "(31 downto 0)" 4743 4789 preAdd 0 4744 4790 posAdd 0 … … 4748 4794 ) 4749 4795 ) 4750 *12 5(CptPort4796 *126 (CptPort 4751 4797 uid 1764,0 4752 4798 ps "OnEdgeStrategy" … … 4785 4831 ) 4786 4832 ) 4787 *12 6(CptPort4833 *127 (CptPort 4788 4834 uid 6207,0 4789 4835 ps "OnEdgeStrategy" … … 4837 4883 stg "VerticalLayoutStrategy" 4838 4884 textVec [ 4839 *12 7(Text4885 *128 (Text 4840 4886 uid 1771,0 4841 4887 va (VaSet … … 4848 4894 tm "BdLibraryNameMgr" 4849 4895 ) 4850 *12 8(Text4896 *129 (Text 4851 4897 uid 1772,0 4852 4898 va (VaSet … … 4859 4905 tm "CptNameMgr" 4860 4906 ) 4861 *1 29(Text4907 *130 (Text 4862 4908 uid 1773,0 4863 4909 va (VaSet … … 4907 4953 ) 4908 4954 archFileType "UNKNOWN" 4909 )4910 *130 (Net4911 uid 1981,04912 lang 24913 decl (Decl4914 n "trigger_id"4915 t "std_logic_vector"4916 b "(47 downto 0)"4917 preAdd 04918 posAdd 04919 o 1194920 suid 34,04921 )4922 declText (MLText4923 uid 1982,04924 va (VaSet4925 font "Courier New,8,0"4926 )4927 xt "-172000,98800,-139500,99600"4928 st "SIGNAL trigger_id : std_logic_vector(47 downto 0)4929 "4930 )4931 4955 ) 4932 4956 *131 (Net … … 17011 17035 ) 17012 17036 ) 17013 *599 (Wire 17037 *599 (SaComponent 17038 uid 15728,0 17039 optionalChildren [ 17040 *600 (CptPort 17041 uid 15712,0 17042 ps "OnEdgeStrategy" 17043 shape (Triangle 17044 uid 15713,0 17045 ro 90 17046 va (VaSet 17047 vasetType 1 17048 fg "0,65535,0" 17049 ) 17050 xt "-83750,113625,-83000,114375" 17051 ) 17052 tg (CPTG 17053 uid 15714,0 17054 ps "CptPortTextPlaceStrategy" 17055 stg "VerticalLayoutStrategy" 17056 f (Text 17057 uid 15715,0 17058 va (VaSet 17059 ) 17060 xt "-82000,113500,-80700,114500" 17061 st "clk" 17062 blo "-82000,114300" 17063 ) 17064 ) 17065 thePort (LogicalPort 17066 decl (Decl 17067 n "clk" 17068 t "STD_LOGIC" 17069 preAdd 0 17070 posAdd 0 17071 o 1 17072 suid 1,0 17073 ) 17074 ) 17075 ) 17076 *601 (CptPort 17077 uid 15716,0 17078 ps "OnEdgeStrategy" 17079 shape (Triangle 17080 uid 15717,0 17081 ro 90 17082 va (VaSet 17083 vasetType 1 17084 fg "0,65535,0" 17085 ) 17086 xt "-83750,115625,-83000,116375" 17087 ) 17088 tg (CPTG 17089 uid 15718,0 17090 ps "CptPortTextPlaceStrategy" 17091 stg "VerticalLayoutStrategy" 17092 f (Text 17093 uid 15719,0 17094 va (VaSet 17095 ) 17096 xt "-82000,115500,-80100,116500" 17097 st "start" 17098 blo "-82000,116300" 17099 ) 17100 ) 17101 thePort (LogicalPort 17102 decl (Decl 17103 n "start" 17104 t "STD_LOGIC" 17105 preAdd 0 17106 posAdd 0 17107 o 2 17108 suid 2,0 17109 ) 17110 ) 17111 ) 17112 *602 (CptPort 17113 uid 15720,0 17114 ps "OnEdgeStrategy" 17115 shape (Triangle 17116 uid 15721,0 17117 ro 90 17118 va (VaSet 17119 vasetType 1 17120 fg "0,65535,0" 17121 ) 17122 xt "-73000,113625,-72250,114375" 17123 ) 17124 tg (CPTG 17125 uid 15722,0 17126 ps "CptPortTextPlaceStrategy" 17127 stg "RightVerticalLayoutStrategy" 17128 f (Text 17129 uid 15723,0 17130 va (VaSet 17131 ) 17132 xt "-78600,113500,-74000,114500" 17133 st "dna : (63:0)" 17134 ju 2 17135 blo "-74000,114300" 17136 ) 17137 t (Text 17138 uid 15738,0 17139 va (VaSet 17140 ) 17141 xt "-79700,114500,-74000,115500" 17142 st "(others => '0')" 17143 ju 2 17144 blo "-74000,115300" 17145 ) 17146 ) 17147 thePort (LogicalPort 17148 m 1 17149 decl (Decl 17150 n "dna" 17151 t "STD_LOGIC_VECTOR" 17152 b "(63 downto 0)" 17153 preAdd 0 17154 posAdd 0 17155 o 3 17156 suid 3,0 17157 i "(others => '0')" 17158 ) 17159 ) 17160 ) 17161 *603 (CptPort 17162 uid 15724,0 17163 ps "OnEdgeStrategy" 17164 shape (Triangle 17165 uid 15725,0 17166 ro 90 17167 va (VaSet 17168 vasetType 1 17169 fg "0,65535,0" 17170 ) 17171 xt "-73000,115625,-72250,116375" 17172 ) 17173 tg (CPTG 17174 uid 15726,0 17175 ps "CptPortTextPlaceStrategy" 17176 stg "RightVerticalLayoutStrategy" 17177 f (Text 17178 uid 15727,0 17179 va (VaSet 17180 ) 17181 xt "-76200,115500,-74000,116500" 17182 st "ready" 17183 ju 2 17184 blo "-74000,116300" 17185 ) 17186 t (Text 17187 uid 15739,0 17188 va (VaSet 17189 ) 17190 xt "-75200,116500,-74000,117500" 17191 st "'0'" 17192 ju 2 17193 blo "-74000,117300" 17194 ) 17195 ) 17196 thePort (LogicalPort 17197 m 1 17198 decl (Decl 17199 n "ready" 17200 t "STD_LOGIC" 17201 preAdd 0 17202 posAdd 0 17203 o 4 17204 suid 4,0 17205 i "'0'" 17206 ) 17207 ) 17208 ) 17209 ] 17210 shape (Rectangle 17211 uid 15729,0 17212 va (VaSet 17213 vasetType 1 17214 fg "0,65535,0" 17215 lineColor "0,32896,0" 17216 lineWidth 2 17217 ) 17218 xt "-83000,112000,-73000,118000" 17219 ) 17220 oxt "39000,2000,49000,12000" 17221 ttg (MlTextGroup 17222 uid 15730,0 17223 ps "CenterOffsetStrategy" 17224 stg "VerticalLayoutStrategy" 17225 textVec [ 17226 *604 (Text 17227 uid 15731,0 17228 va (VaSet 17229 font "Arial,8,1" 17230 ) 17231 xt "-80800,118000,-74600,119000" 17232 st "FACT_FAD_lib" 17233 blo "-80800,118800" 17234 tm "BdLibraryNameMgr" 17235 ) 17236 *605 (Text 17237 uid 15732,0 17238 va (VaSet 17239 font "Arial,8,1" 17240 ) 17241 xt "-80800,119000,-77200,120000" 17242 st "dna_gen" 17243 blo "-80800,119800" 17244 tm "CptNameMgr" 17245 ) 17246 *606 (Text 17247 uid 15733,0 17248 va (VaSet 17249 font "Arial,8,1" 17250 ) 17251 xt "-80800,120000,-79000,121000" 17252 st "U_0" 17253 blo "-80800,120800" 17254 tm "InstanceNameMgr" 17255 ) 17256 ] 17257 ) 17258 ga (GenericAssociation 17259 uid 15734,0 17260 ps "EdgeToEdgeStrategy" 17261 matrix (Matrix 17262 uid 15735,0 17263 text (MLText 17264 uid 15736,0 17265 va (VaSet 17266 font "Courier New,8,0" 17267 ) 17268 xt "-83000,111000,-83000,111000" 17269 ) 17270 header "" 17271 ) 17272 elements [ 17273 ] 17274 ) 17275 viewicon (ZoomableIcon 17276 uid 15737,0 17277 sl 0 17278 va (VaSet 17279 vasetType 1 17280 fg "49152,49152,49152" 17281 ) 17282 xt "-82750,116250,-81250,117750" 17283 iconName "VhdlFileViewIcon.png" 17284 iconMaskName "VhdlFileViewIcon.msk" 17285 ftype 10 17286 ) 17287 ordering 1 17288 viewiconposition 0 17289 portVis (PortSigDisplay 17290 sIVOD 1 17291 ) 17292 archFileType "UNKNOWN" 17293 ) 17294 *607 (Net 17295 uid 15748,0 17296 lang 2 17297 decl (Decl 17298 n "trigger_id" 17299 t "std_logic_vector" 17300 b "(31 downto 0)" 17301 preAdd 0 17302 posAdd 0 17303 o 123 17304 suid 302,0 17305 ) 17306 declText (MLText 17307 uid 15749,0 17308 va (VaSet 17309 font "Courier New,8,0" 17310 ) 17311 xt "-172000,98800,-139500,99600" 17312 st "SIGNAL trigger_id : std_logic_vector(31 downto 0) 17313 " 17314 ) 17315 ) 17316 *608 (Wire 17014 17317 uid 322,0 17015 17318 shape (OrthoPolyLine … … 17050 17353 on &2 17051 17354 ) 17052 *60 0(Wire17355 *609 (Wire 17053 17356 uid 328,0 17054 17357 shape (OrthoPolyLine … … 17089 17392 on &3 17090 17393 ) 17091 *6 01(Wire17394 *610 (Wire 17092 17395 uid 334,0 17093 17396 shape (OrthoPolyLine … … 17128 17431 on &4 17129 17432 ) 17130 *6 02(Wire17433 *611 (Wire 17131 17434 uid 364,0 17132 17435 shape (OrthoPolyLine … … 17144 17447 ] 17145 17448 ) 17146 start &8 617449 start &87 17147 17450 end &336 17148 17451 sat 32 … … 17168 17471 on &5 17169 17472 ) 17170 *6 03(Wire17473 *612 (Wire 17171 17474 uid 370,0 17172 17475 shape (OrthoPolyLine … … 17184 17487 ] 17185 17488 ) 17186 start &8 517489 start &86 17187 17490 end &337 17188 17491 sat 32 … … 17208 17511 on &6 17209 17512 ) 17210 *6 04(Wire17513 *613 (Wire 17211 17514 uid 376,0 17212 17515 shape (OrthoPolyLine … … 17221 17524 ] 17222 17525 ) 17223 start &7 617526 start &77 17224 17527 end &14 17225 17528 sat 32 … … 17246 17549 on &7 17247 17550 ) 17248 *6 05(Wire17551 *614 (Wire 17249 17552 uid 384,0 17250 17553 shape (OrthoPolyLine … … 17260 17563 ] 17261 17564 ) 17262 start &7 717565 start &78 17263 17566 end &15 17264 17567 sat 32 … … 17286 17589 on &8 17287 17590 ) 17288 *6 06(Wire17591 *615 (Wire 17289 17592 uid 392,0 17290 17593 shape (OrthoPolyLine … … 17300 17603 ] 17301 17604 ) 17302 start &7 817605 start &79 17303 17606 end &16 17304 17607 sat 32 … … 17326 17629 on &9 17327 17630 ) 17328 *6 07(Wire17631 *616 (Wire 17329 17632 uid 400,0 17330 17633 shape (OrthoPolyLine … … 17339 17642 ] 17340 17643 ) 17341 start & 7917644 start &80 17342 17645 end &17 17343 17646 sat 32 … … 17364 17667 on &10 17365 17668 ) 17366 *6 08(Wire17669 *617 (Wire 17367 17670 uid 408,0 17368 17671 shape (OrthoPolyLine … … 17377 17680 ] 17378 17681 ) 17379 start &8 017682 start &81 17380 17683 end &18 17381 17684 sat 32 … … 17402 17705 on &11 17403 17706 ) 17404 *6 09(Wire17707 *618 (Wire 17405 17708 uid 424,0 17406 17709 shape (OrthoPolyLine … … 17415 17718 ] 17416 17719 ) 17417 start &8 117720 start &82 17418 17721 end &20 17419 17722 sat 32 … … 17440 17743 on &12 17441 17744 ) 17442 *61 0(Wire17745 *619 (Wire 17443 17746 uid 432,0 17444 17747 shape (OrthoPolyLine … … 17454 17757 ) 17455 17758 start &21 17456 end &8 217759 end &83 17457 17760 sat 32 17458 17761 eat 32 … … 17478 17781 on &13 17479 17782 ) 17480 *6 11(Wire17783 *620 (Wire 17481 17784 uid 1411,0 17482 17785 shape (OrthoPolyLine … … 17515 17818 ) 17516 17819 ) 17517 on &7 117518 ) 17519 *6 12(Wire17820 on &72 17821 ) 17822 *621 (Wire 17520 17823 uid 1425,0 17521 17824 shape (OrthoPolyLine … … 17530 17833 ] 17531 17834 ) 17532 start &7 317835 start &74 17533 17836 end &409 17534 17837 es 0 … … 17554 17857 ) 17555 17858 ) 17556 on &7 217557 ) 17558 *6 13(Wire17859 on &73 17860 ) 17861 *622 (Wire 17559 17862 uid 1682,0 17560 17863 shape (OrthoPolyLine … … 17571 17874 ) 17572 17875 start &173 17573 end &3 117876 end &30 17574 17877 sat 32 17575 17878 eat 32 … … 17593 17896 ) 17594 17897 ) 17595 on &122 17596 ) 17597 *614 (Wire 17598 uid 1983,0 17599 shape (OrthoPolyLine 17600 uid 1984,0 17601 va (VaSet 17602 vasetType 3 17603 lineWidth 2 17604 ) 17605 xt "-40250,69000,-21750,70000" 17606 pts [ 17607 "-40250,69000" 17608 "-36000,69000" 17609 "-36000,70000" 17610 "-21750,70000" 17611 ] 17612 ) 17613 start &124 17614 end &29 17615 sat 32 17616 eat 32 17617 sty 1 17618 st 0 17619 sf 1 17620 tg (WTG 17621 uid 1985,0 17622 ps "ConnStartEndStrategy" 17623 stg "STSignalDisplayStrategy" 17624 f (Text 17625 uid 1986,0 17626 va (VaSet 17627 ) 17628 xt "-29000,70000,-22200,71000" 17629 st "trigger_id : (47:0)" 17630 blo "-29000,70800" 17631 tm "WireNameMgr" 17632 ) 17633 ) 17634 on &130 17635 ) 17636 *615 (Wire 17898 on &123 17899 ) 17900 *623 (Wire 17637 17901 uid 2299,0 17638 17902 shape (OrthoPolyLine … … 17672 17936 on &131 17673 17937 ) 17674 *6 16(Wire17938 *624 (Wire 17675 17939 uid 2470,0 17676 17940 shape (OrthoPolyLine … … 17686 17950 ) 17687 17951 start &140 17688 end &8 817952 end &89 17689 17953 sat 32 17690 17954 eat 32 … … 17708 17972 on &155 17709 17973 ) 17710 *6 17(Wire17974 *625 (Wire 17711 17975 uid 2476,0 17712 17976 shape (OrthoPolyLine … … 17722 17986 ) 17723 17987 start &143 17724 end &8 717988 end &88 17725 17989 sat 32 17726 17990 eat 32 … … 17744 18008 on &156 17745 18009 ) 17746 *6 18(Wire18010 *626 (Wire 17747 18011 uid 2482,0 17748 18012 shape (OrthoPolyLine … … 17759 18023 ) 17760 18024 start &146 17761 end &8 318025 end &84 17762 18026 sat 32 17763 18027 eat 32 … … 17782 18046 on &157 17783 18047 ) 17784 *6 19(Wire18048 *627 (Wire 17785 18049 uid 2488,0 17786 18050 shape (OrthoPolyLine … … 17797 18061 ) 17798 18062 start &142 17799 end &8 418063 end &85 17800 18064 sat 32 17801 18065 eat 32 … … 17820 18084 on &158 17821 18085 ) 17822 *62 0(Wire18086 *628 (Wire 17823 18087 uid 2494,0 17824 18088 shape (OrthoPolyLine … … 17835 18099 ) 17836 18100 start &141 17837 end & 8918101 end &90 17838 18102 sat 32 17839 18103 eat 32 … … 17858 18122 on &159 17859 18123 ) 17860 *62 1(Wire18124 *629 (Wire 17861 18125 uid 2500,0 17862 18126 shape (OrthoPolyLine … … 17872 18136 ) 17873 18137 start &144 17874 end &9 018138 end &91 17875 18139 sat 32 17876 18140 eat 32 … … 17894 18158 on &160 17895 18159 ) 17896 *6 22(Wire18160 *630 (Wire 17897 18161 uid 2506,0 17898 18162 shape (OrthoPolyLine … … 17908 18172 ) 17909 18173 start &145 17910 end &9 118174 end &92 17911 18175 sat 32 17912 18176 eat 32 … … 17930 18194 on &161 17931 18195 ) 17932 *6 23(Wire18196 *631 (Wire 17933 18197 uid 2576,0 17934 18198 shape (OrthoPolyLine … … 17943 18207 ] 17944 18208 ) 17945 start &3 218209 start &31 17946 18210 end &137 17947 18211 sat 32 … … 17966 18230 on &162 17967 18231 ) 17968 *6 24(Wire18232 *632 (Wire 17969 18233 uid 2582,0 17970 18234 shape (OrthoPolyLine … … 17979 18243 ] 17980 18244 ) 17981 start &3 318245 start &32 17982 18246 end &138 17983 18247 sat 32 … … 18002 18266 on &163 18003 18267 ) 18004 *6 25(Wire18268 *633 (Wire 18005 18269 uid 2588,0 18006 18270 shape (OrthoPolyLine … … 18015 18279 ] 18016 18280 ) 18017 start &5 118281 start &50 18018 18282 end &136 18019 18283 ss 0 … … 18039 18303 on &164 18040 18304 ) 18041 *6 26(Wire18305 *634 (Wire 18042 18306 uid 2594,0 18043 18307 shape (OrthoPolyLine … … 18052 18316 ] 18053 18317 ) 18054 start &4 718318 start &46 18055 18319 end &135 18056 18320 sat 32 … … 18075 18339 on &165 18076 18340 ) 18077 *6 27(Wire18341 *635 (Wire 18078 18342 uid 2600,0 18079 18343 shape (OrthoPolyLine … … 18088 18352 ] 18089 18353 ) 18090 start &3 418354 start &33 18091 18355 end &139 18092 18356 sat 32 … … 18111 18375 on &166 18112 18376 ) 18113 *6 28(Wire18377 *636 (Wire 18114 18378 uid 2642,0 18115 18379 shape (OrthoPolyLine … … 18125 18389 ] 18126 18390 ) 18127 start &3 618391 start &35 18128 18392 end &148 18129 18393 sat 32 … … 18149 18413 on &167 18150 18414 ) 18151 *6 29(Wire18415 *637 (Wire 18152 18416 uid 2778,0 18153 18417 shape (OrthoPolyLine … … 18162 18426 ] 18163 18427 ) 18164 start &3 718428 start &36 18165 18429 end &169 18166 18430 sat 32 … … 18187 18451 on &168 18188 18452 ) 18189 *63 0(Wire18453 *638 (Wire 18190 18454 uid 2786,0 18191 18455 shape (OrthoPolyLine … … 18227 18491 on &191 18228 18492 ) 18229 *63 1(Wire18493 *639 (Wire 18230 18494 uid 3888,0 18231 18495 optionalChildren [ 18232 *6 32(BdJunction18496 *640 (BdJunction 18233 18497 uid 4230,0 18234 18498 ps "OnConnectorStrategy" … … 18242 18506 ) 18243 18507 ) 18244 *6 33(BdJunction18508 *641 (BdJunction 18245 18509 uid 4244,0 18246 18510 ps "OnConnectorStrategy" … … 18270 18534 ) 18271 18535 start &365 18272 end &7 518536 end &76 18273 18537 sat 32 18274 18538 eat 32 … … 18293 18557 on &187 18294 18558 ) 18295 *6 34(Wire18559 *642 (Wire 18296 18560 uid 3984,0 18297 18561 shape (OrthoPolyLine … … 18334 18598 on &185 18335 18599 ) 18336 *6 35(Wire18600 *643 (Wire 18337 18601 uid 4042,0 18338 18602 shape (OrthoPolyLine … … 18372 18636 on &190 18373 18637 ) 18374 *6 36(Wire18638 *644 (Wire 18375 18639 uid 4226,0 18376 18640 shape (OrthoPolyLine … … 18388 18652 ) 18389 18653 start &189 18390 end &6 3218654 end &640 18391 18655 sat 32 18392 18656 eat 32 … … 18412 18676 on &187 18413 18677 ) 18414 *6 37(Wire18678 *645 (Wire 18415 18679 uid 4240,0 18416 18680 shape (OrthoPolyLine … … 18428 18692 ) 18429 18693 start &335 18430 end &6 3318694 end &641 18431 18695 sat 32 18432 18696 eat 32 … … 18451 18715 on &187 18452 18716 ) 18453 *6 38(Wire18717 *646 (Wire 18454 18718 uid 4272,0 18455 18719 shape (OrthoPolyLine … … 18489 18753 on &192 18490 18754 ) 18491 *6 39(Wire18755 *647 (Wire 18492 18756 uid 4401,0 18493 18757 shape (OrthoPolyLine … … 18504 18768 ] 18505 18769 ) 18506 start & 4018770 start &39 18507 18771 end &212 18508 18772 sat 32 … … 18527 18791 on &194 18528 18792 ) 18529 *64 0(Wire18793 *648 (Wire 18530 18794 uid 4407,0 18531 18795 shape (OrthoPolyLine … … 18542 18806 ] 18543 18807 ) 18544 start &4 318808 start &42 18545 18809 end &218 18546 18810 sat 32 … … 18565 18829 on &195 18566 18830 ) 18567 *64 1(Wire18831 *649 (Wire 18568 18832 uid 4419,0 18569 18833 shape (OrthoPolyLine … … 18580 18844 ] 18581 18845 ) 18582 start &4 118846 start &40 18583 18847 end &213 18584 18848 sat 32 … … 18603 18867 on &196 18604 18868 ) 18605 *6 42(Wire18869 *650 (Wire 18606 18870 uid 4537,0 18607 18871 shape (OrthoPolyLine … … 18617 18881 ] 18618 18882 ) 18619 start &3 918883 start &38 18620 18884 end &199 18621 18885 sat 32 … … 18643 18907 on &197 18644 18908 ) 18645 *6 43(Wire18909 *651 (Wire 18646 18910 uid 4545,0 18647 18911 shape (OrthoPolyLine … … 18680 18944 on &198 18681 18945 ) 18682 *6 44(Wire18946 *652 (Wire 18683 18947 uid 4671,0 18684 18948 shape (OrthoPolyLine … … 18718 18982 on &201 18719 18983 ) 18720 *6 45(Wire18984 *653 (Wire 18721 18985 uid 4679,0 18722 18986 shape (OrthoPolyLine … … 18756 19020 on &202 18757 19021 ) 18758 *6 46(Wire19022 *654 (Wire 18759 19023 uid 4687,0 18760 19024 shape (OrthoPolyLine … … 18794 19058 on &203 18795 19059 ) 18796 *6 47(Wire19060 *655 (Wire 18797 19061 uid 4695,0 18798 19062 shape (OrthoPolyLine … … 18832 19096 on &204 18833 19097 ) 18834 *6 48(Wire19098 *656 (Wire 18835 19099 uid 4743,0 18836 19100 shape (OrthoPolyLine … … 18848 19112 ) 18849 19113 start &219 18850 end &4 219114 end &41 18851 19115 sat 32 18852 19116 eat 32 … … 18870 19134 on &209 18871 19135 ) 18872 *6 49(Wire19136 *657 (Wire 18873 19137 uid 4757,0 18874 19138 optionalChildren [ 18875 *65 0(BdJunction19139 *658 (BdJunction 18876 19140 uid 6076,0 18877 19141 ps "OnConnectorStrategy" … … 18881 19145 vasetType 1 18882 19146 ) 18883 xt "-2 5400,40600,-24600,41400"19147 xt "-26400,40600,-25600,41400" 18884 19148 radius 400 18885 19149 ) … … 18892 19156 lineColor "0,32896,0" 18893 19157 ) 18894 xt "-6 2000,41000,-25000,48000"19158 xt "-64000,41000,-26000,48000" 18895 19159 pts [ 18896 19160 "-58750,48000" 18897 "-6 2000,48000"18898 "-6 2000,41000"18899 "-2 5000,41000"19161 "-64000,48000" 19162 "-64000,41000" 19163 "-26000,41000" 18900 19164 ] 18901 19165 ) 18902 19166 start &211 18903 end *65 1(BdJunction19167 end *659 (BdJunction 18904 19168 uid 6080,0 18905 19169 ps "OnConnectorStrategy" … … 18909 19173 vasetType 1 18910 19174 ) 18911 xt "-2 5400,40600,-24600,41400"19175 xt "-26400,40600,-25600,41400" 18912 19176 radius 400 18913 19177 ) … … 18935 19199 on &188 18936 19200 ) 18937 *6 52(Wire19201 *660 (Wire 18938 19202 uid 4948,0 18939 19203 shape (OrthoPolyLine … … 18973 19237 on &230 18974 19238 ) 18975 *6 53(Wire19239 *661 (Wire 18976 19240 uid 4962,0 18977 19241 shape (OrthoPolyLine … … 19011 19275 on &232 19012 19276 ) 19013 *6 54(Wire19277 *662 (Wire 19014 19278 uid 5090,0 19015 19279 shape (OrthoPolyLine … … 19027 19291 ] 19028 19292 ) 19029 start &9 419293 start &95 19030 19294 end &236 19031 19295 sat 32 … … 19050 19314 on &252 19051 19315 ) 19052 *6 55(Wire19316 *663 (Wire 19053 19317 uid 5098,0 19054 19318 shape (OrthoPolyLine … … 19084 19348 on &253 19085 19349 ) 19086 *6 56(Wire19350 *664 (Wire 19087 19351 uid 5106,0 19088 19352 shape (OrthoPolyLine … … 19100 19364 ) 19101 19365 start &238 19102 end &9 519366 end &96 19103 19367 sat 32 19104 19368 eat 32 … … 19121 19385 on &254 19122 19386 ) 19123 *6 57(Wire19387 *665 (Wire 19124 19388 uid 5114,0 19125 19389 shape (OrthoPolyLine … … 19138 19402 ) 19139 19403 start &239 19140 end &9 619404 end &97 19141 19405 sat 32 19142 19406 eat 32 … … 19160 19424 on &255 19161 19425 ) 19162 *6 58(Wire19426 *666 (Wire 19163 19427 uid 5122,0 19164 19428 shape (OrthoPolyLine … … 19175 19439 ] 19176 19440 ) 19177 start &9 819441 start &99 19178 19442 end &241 19179 19443 sat 32 … … 19197 19461 on &256 19198 19462 ) 19199 *6 59(Wire19463 *667 (Wire 19200 19464 uid 5130,0 19201 19465 shape (OrthoPolyLine … … 19212 19476 ] 19213 19477 ) 19214 start &10 019478 start &101 19215 19479 end &243 19216 19480 sat 32 … … 19234 19498 on &257 19235 19499 ) 19236 *66 0(Wire19500 *668 (Wire 19237 19501 uid 5138,0 19238 19502 optionalChildren [ 19239 *66 1(BdJunction19503 *669 (BdJunction 19240 19504 uid 5400,0 19241 19505 ps "OnConnectorStrategy" … … 19264 19528 ) 19265 19529 start &240 19266 end &3 519530 end &34 19267 19531 ss 0 19268 19532 es 0 … … 19287 19551 on &171 19288 19552 ) 19289 *6 62(Wire19553 *670 (Wire 19290 19554 uid 5146,0 19291 19555 shape (OrthoPolyLine … … 19323 19587 on &258 19324 19588 ) 19325 *6 63(Wire19589 *671 (Wire 19326 19590 uid 5168,0 19327 19591 shape (OrthoPolyLine … … 19338 19602 ] 19339 19603 ) 19340 start &66 119604 start &669 19341 19605 end &147 19342 19606 sat 32 … … 19361 19625 on &171 19362 19626 ) 19363 *6 64(Wire19627 *672 (Wire 19364 19628 uid 5184,0 19365 19629 shape (OrthoPolyLine … … 19377 19641 ) 19378 19642 start &244 19379 end &4 619643 end &45 19380 19644 sat 32 19381 19645 eat 32 … … 19398 19662 on &259 19399 19663 ) 19400 *6 65(Wire19664 *673 (Wire 19401 19665 uid 5190,0 19402 19666 shape (OrthoPolyLine … … 19414 19678 ) 19415 19679 start &245 19416 end &4 519680 end &44 19417 19681 sat 32 19418 19682 eat 32 … … 19435 19699 on &260 19436 19700 ) 19437 *6 66(Wire19701 *674 (Wire 19438 19702 uid 5222,0 19439 19703 shape (OrthoPolyLine … … 19449 19713 ] 19450 19714 ) 19451 start &9 219715 start &93 19452 19716 end &19 19453 19717 sat 32 … … 19475 19739 on &261 19476 19740 ) 19477 *6 67(Wire19741 *675 (Wire 19478 19742 uid 5404,0 19479 19743 shape (OrthoPolyLine … … 19491 19755 ) 19492 19756 start &280 19493 end &4 819757 end &47 19494 19758 sat 32 19495 19759 eat 32 … … 19512 19776 on &264 19513 19777 ) 19514 *6 68(Wire19778 *676 (Wire 19515 19779 uid 5474,0 19516 19780 shape (OrthoPolyLine … … 19528 19792 ) 19529 19793 start &283 19530 end & 5019794 end &49 19531 19795 sat 32 19532 19796 eat 32 … … 19549 19813 on &262 19550 19814 ) 19551 *6 69(Wire19815 *677 (Wire 19552 19816 uid 5480,0 19553 19817 shape (OrthoPolyLine … … 19565 19829 ) 19566 19830 start &282 19567 end &4 919831 end &48 19568 19832 sat 32 19569 19833 eat 32 … … 19586 19850 on &263 19587 19851 ) 19588 *67 0(Wire19852 *678 (Wire 19589 19853 uid 5582,0 19590 19854 shape (OrthoPolyLine … … 19621 19885 on &187 19622 19886 ) 19623 *67 1(Wire19887 *679 (Wire 19624 19888 uid 5602,0 19625 19889 optionalChildren [ 19626 &65 119890 &659 19627 19891 ] 19628 19892 shape (OrthoPolyLine … … 19632 19896 lineColor "0,32896,0" 19633 19897 ) 19634 xt "-2 5000,41000,36250,51000"19898 xt "-26000,41000,36250,51000" 19635 19899 pts [ 19636 19900 "-21750,51000" 19637 "-2 5000,51000"19638 "-2 5000,41000"19901 "-26000,51000" 19902 "-26000,41000" 19639 19903 "28000,41000" 19640 19904 "28000,47000" … … 19666 19930 on &188 19667 19931 ) 19668 *6 72(Wire19932 *680 (Wire 19669 19933 uid 5626,0 19670 19934 shape (OrthoPolyLine … … 19679 19943 ] 19680 19944 ) 19681 start &4 419945 start &43 19682 19946 end &269 19683 19947 sat 32 … … 19702 19966 on &266 19703 19967 ) 19704 *6 73(Wire19968 *681 (Wire 19705 19969 uid 5634,0 19706 19970 shape (OrthoPolyLine … … 19716 19980 ] 19717 19981 ) 19718 start &3 819982 start &37 19719 19983 end &270 19720 19984 sat 32 … … 19740 20004 on &265 19741 20005 ) 19742 *6 74(Wire20006 *682 (Wire 19743 20007 uid 5646,0 19744 20008 shape (OrthoPolyLine … … 19776 20040 on &185 19777 20041 ) 19778 *6 75(Wire20042 *683 (Wire 19779 20043 uid 5745,0 19780 20044 shape (OrthoPolyLine … … 19791 20055 ] 19792 20056 ) 19793 start &5 220057 start &51 19794 20058 end &281 19795 20059 sat 32 … … 19814 20078 on &276 19815 20079 ) 19816 *6 76(Wire20080 *684 (Wire 19817 20081 uid 5805,0 19818 20082 shape (OrthoPolyLine … … 19848 20112 on &187 19849 20113 ) 19850 *6 77(Wire20114 *685 (Wire 19851 20115 uid 5813,0 19852 20116 shape (OrthoPolyLine … … 19886 20150 on &293 19887 20151 ) 19888 *6 78(Wire20152 *686 (Wire 19889 20153 uid 5821,0 19890 20154 shape (OrthoPolyLine … … 19924 20188 on &294 19925 20189 ) 19926 *6 79(Wire20190 *687 (Wire 19927 20191 uid 5829,0 19928 20192 shape (OrthoPolyLine … … 19962 20226 on &295 19963 20227 ) 19964 *68 0(Wire20228 *688 (Wire 19965 20229 uid 5837,0 19966 20230 shape (OrthoPolyLine … … 20002 20266 on &296 20003 20267 ) 20004 *68 1(Wire20268 *689 (Wire 20005 20269 uid 5950,0 20006 20270 shape (OrthoPolyLine … … 20017 20281 ] 20018 20282 ) 20019 start & 9920020 end &5 420283 start &100 20284 end &53 20021 20285 sat 32 20022 20286 eat 32 … … 20040 20304 on &301 20041 20305 ) 20042 *6 82(Wire20306 *690 (Wire 20043 20307 uid 5962,0 20044 20308 shape (OrthoPolyLine … … 20055 20319 ] 20056 20320 ) 20057 start &9 720058 end &5 320321 start &98 20322 end &52 20059 20323 sat 32 20060 20324 eat 32 … … 20078 20342 on &302 20079 20343 ) 20080 *6 83(Wire20344 *691 (Wire 20081 20345 uid 6002,0 20082 20346 shape (OrthoPolyLine … … 20094 20358 ) 20095 20359 start &246 20096 end &5 520360 end &54 20097 20361 sat 32 20098 20362 eat 32 … … 20116 20380 on &304 20117 20381 ) 20118 *6 84(Wire20382 *692 (Wire 20119 20383 uid 6008,0 20120 20384 shape (OrthoPolyLine … … 20132 20396 ) 20133 20397 start &287 20134 end &5 720398 end &56 20135 20399 sat 32 20136 20400 eat 32 … … 20154 20418 on &303 20155 20419 ) 20156 *6 85(Wire20420 *693 (Wire 20157 20421 uid 6018,0 20158 20422 shape (OrthoPolyLine … … 20167 20431 ] 20168 20432 ) 20169 start &5 620433 start &55 20170 20434 end &149 20171 20435 sat 32 … … 20190 20454 on &305 20191 20455 ) 20192 *6 86(Wire20456 *694 (Wire 20193 20457 uid 6064,0 20194 20458 shape (OrthoPolyLine … … 20203 20467 ] 20204 20468 ) 20205 end &5 820469 end &57 20206 20470 sat 16 20207 20471 eat 32 … … 20225 20489 on &258 20226 20490 ) 20227 *6 87(Wire20491 *695 (Wire 20228 20492 uid 6072,0 20229 20493 shape (OrthoPolyLine … … 20233 20497 lineColor "0,32896,0" 20234 20498 ) 20235 xt "-41250,23000,-2 5000,41000"20499 xt "-41250,23000,-26000,41000" 20236 20500 pts [ 20237 20501 "-41250,23000" 20238 "-2 5000,23000"20239 "-2 5000,41000"20502 "-26000,23000" 20503 "-26000,41000" 20240 20504 ] 20241 20505 ) 20242 20506 start &366 20243 end &65 020507 end &658 20244 20508 sat 32 20245 20509 eat 32 … … 20264 20528 on &188 20265 20529 ) 20266 *6 88(Wire20530 *696 (Wire 20267 20531 uid 6160,0 20268 20532 shape (OrthoPolyLine … … 20302 20566 on &306 20303 20567 ) 20304 *6 89(Wire20568 *697 (Wire 20305 20569 uid 6276,0 20306 20570 shape (OrthoPolyLine … … 20315 20579 ] 20316 20580 ) 20317 end &12 620581 end &127 20318 20582 sat 16 20319 20583 eat 32 … … 20336 20600 on &185 20337 20601 ) 20338 *69 0(Wire20602 *698 (Wire 20339 20603 uid 6362,0 20340 20604 shape (OrthoPolyLine … … 20375 20639 on &308 20376 20640 ) 20377 *69 1(Wire20641 *699 (Wire 20378 20642 uid 6452,0 20379 20643 shape (OrthoPolyLine … … 20388 20652 ] 20389 20653 ) 20390 start &10 220654 start &103 20391 20655 sat 32 20392 20656 eat 16 … … 20411 20675 on &310 20412 20676 ) 20413 * 692(Wire20677 *700 (Wire 20414 20678 uid 6540,0 20415 20679 shape (OrthoPolyLine … … 20448 20712 on &329 20449 20713 ) 20450 * 693(Wire20714 *701 (Wire 20451 20715 uid 6548,0 20452 20716 shape (OrthoPolyLine … … 20485 20749 on &310 20486 20750 ) 20487 * 694(Wire20751 *702 (Wire 20488 20752 uid 8416,0 20489 20753 shape (OrthoPolyLine … … 20499 20763 ) 20500 20764 start &150 20501 end &10 320765 end &104 20502 20766 sat 32 20503 20767 eat 32 … … 20521 20785 on &341 20522 20786 ) 20523 * 695(Wire20787 *703 (Wire 20524 20788 uid 8732,0 20525 20789 shape (OrthoPolyLine … … 20559 20823 on &360 20560 20824 ) 20561 * 696(Wire20825 *704 (Wire 20562 20826 uid 8738,0 20563 20827 shape (OrthoPolyLine … … 20595 20859 on &361 20596 20860 ) 20597 * 697(Wire20861 *705 (Wire 20598 20862 uid 8752,0 20599 20863 shape (OrthoPolyLine … … 20608 20872 ] 20609 20873 ) 20610 start &10 420874 start &105 20611 20875 sat 32 20612 20876 eat 16 … … 20630 20894 on &361 20631 20895 ) 20632 * 698(Wire20896 *706 (Wire 20633 20897 uid 9006,0 20634 20898 shape (OrthoPolyLine … … 20643 20907 ] 20644 20908 ) 20645 start &5 920909 start &58 20646 20910 end &363 20647 20911 sat 32 … … 20668 20932 on &362 20669 20933 ) 20670 * 699(Wire20934 *707 (Wire 20671 20935 uid 9233,0 20672 20936 shape (OrthoPolyLine … … 20681 20945 ] 20682 20946 ) 20683 start &10 520947 start &106 20684 20948 sat 32 20685 20949 eat 16 … … 20703 20967 on &376 20704 20968 ) 20705 *70 0(Wire20969 *708 (Wire 20706 20970 uid 9241,0 20707 20971 shape (OrthoPolyLine … … 20716 20980 ] 20717 20981 ) 20718 start &10 620982 start &107 20719 20983 sat 32 20720 20984 eat 16 … … 20738 21002 on &377 20739 21003 ) 20740 *70 1(Wire21004 *709 (Wire 20741 21005 uid 9253,0 20742 21006 shape (OrthoPolyLine … … 20772 21036 on &376 20773 21037 ) 20774 *7 02(Wire21038 *710 (Wire 20775 21039 uid 9261,0 20776 21040 shape (OrthoPolyLine … … 20806 21070 on &377 20807 21071 ) 20808 *7 03(Wire21072 *711 (Wire 20809 21073 uid 9943,0 20810 21074 shape (OrthoPolyLine … … 20819 21083 ] 20820 21084 ) 20821 start &10 721085 start &108 20822 21086 sat 32 20823 21087 eat 16 … … 20841 21105 on &378 20842 21106 ) 20843 *7 04(Wire21107 *712 (Wire 20844 21108 uid 9951,0 20845 21109 shape (OrthoPolyLine … … 20854 21118 ] 20855 21119 ) 20856 start &10 821120 start &109 20857 21121 sat 32 20858 21122 eat 16 … … 20876 21140 on &379 20877 21141 ) 20878 *7 05(Wire21142 *713 (Wire 20879 21143 uid 10010,0 20880 21144 shape (OrthoPolyLine … … 20914 21178 on &398 20915 21179 ) 20916 *7 06(Wire21180 *714 (Wire 20917 21181 uid 10018,0 20918 21182 shape (OrthoPolyLine … … 20950 21214 on &379 20951 21215 ) 20952 *7 07(Wire21216 *715 (Wire 20953 21217 uid 10036,0 20954 21218 shape (OrthoPolyLine … … 20984 21248 on &378 20985 21249 ) 20986 *7 08(Wire21250 *716 (Wire 20987 21251 uid 10194,0 20988 21252 shape (OrthoPolyLine … … 21000 21264 ) 21001 21265 start &247 21002 end &1 0921266 end &110 21003 21267 ss 0 21004 21268 es 0 … … 21024 21288 on &399 21025 21289 ) 21026 *7 09(Wire21290 *717 (Wire 21027 21291 uid 10202,0 21028 21292 shape (OrthoPolyLine … … 21040 21304 ) 21041 21305 start &248 21042 end &11 021306 end &111 21043 21307 sat 32 21044 21308 eat 32 … … 21062 21326 on &400 21063 21327 ) 21064 *71 0(Wire21328 *718 (Wire 21065 21329 uid 10266,0 21066 21330 shape (OrthoPolyLine … … 21075 21339 ] 21076 21340 ) 21077 start &9 321341 start &94 21078 21342 sat 32 21079 21343 eat 16 … … 21097 21361 on &498 21098 21362 ) 21099 *71 1(Wire21363 *719 (Wire 21100 21364 uid 10298,0 21101 21365 shape (OrthoPolyLine … … 21111 21375 ) 21112 21376 start &226 21113 end &6 121377 end &60 21114 21378 sat 32 21115 21379 eat 32 … … 21133 21397 on &402 21134 21398 ) 21135 *7 12(Wire21399 *720 (Wire 21136 21400 uid 10304,0 21137 21401 shape (OrthoPolyLine … … 21147 21411 ) 21148 21412 start &224 21149 end &6 221413 end &61 21150 21414 sat 32 21151 21415 eat 32 … … 21169 21433 on &403 21170 21434 ) 21171 *7 13(Wire21435 *721 (Wire 21172 21436 uid 10310,0 21173 21437 shape (OrthoPolyLine … … 21183 21447 ) 21184 21448 start &225 21185 end &6 321449 end &62 21186 21450 sat 32 21187 21451 eat 32 … … 21205 21469 on &404 21206 21470 ) 21207 *7 14(Wire21471 *722 (Wire 21208 21472 uid 10316,0 21209 21473 shape (OrthoPolyLine … … 21219 21483 ] 21220 21484 ) 21221 start & 6021485 start &59 21222 21486 end &222 21223 21487 sat 32 … … 21243 21507 on &405 21244 21508 ) 21245 *7 15(Wire21509 *723 (Wire 21246 21510 uid 10322,0 21247 21511 shape (OrthoPolyLine … … 21281 21545 on &406 21282 21546 ) 21283 *7 16(Wire21547 *724 (Wire 21284 21548 uid 10431,0 21285 21549 shape (OrthoPolyLine … … 21318 21582 on &401 21319 21583 ) 21320 *7 17(Wire21584 *725 (Wire 21321 21585 uid 10467,0 21322 21586 shape (OrthoPolyLine … … 21332 21596 ) 21333 21597 start &151 21334 end &6 421598 end &63 21335 21599 es 0 21336 21600 sat 32 … … 21355 21619 on &431 21356 21620 ) 21357 *7 18(Wire21621 *726 (Wire 21358 21622 uid 10629,0 21359 21623 shape (OrthoPolyLine … … 21368 21632 ] 21369 21633 ) 21370 start &11 121634 start &112 21371 21635 sat 32 21372 21636 eat 16 … … 21390 21654 on &432 21391 21655 ) 21392 *7 19(Wire21656 *727 (Wire 21393 21657 uid 10637,0 21394 21658 shape (OrthoPolyLine … … 21403 21667 ] 21404 21668 ) 21405 start &11 221669 start &113 21406 21670 sat 32 21407 21671 eat 16 … … 21425 21689 on &433 21426 21690 ) 21427 *72 0(Wire21691 *728 (Wire 21428 21692 uid 10685,0 21429 21693 shape (OrthoPolyLine … … 21460 21724 on &433 21461 21725 ) 21462 *72 1(Wire21726 *729 (Wire 21463 21727 uid 10691,0 21464 21728 shape (OrthoPolyLine … … 21495 21759 on &432 21496 21760 ) 21497 *7 22(Wire21761 *730 (Wire 21498 21762 uid 10699,0 21499 21763 shape (OrthoPolyLine … … 21531 21795 on &187 21532 21796 ) 21533 *7 23(Wire21797 *731 (Wire 21534 21798 uid 10707,0 21535 21799 shape (OrthoPolyLine … … 21566 21830 on &452 21567 21831 ) 21568 *7 24(Wire21832 *732 (Wire 21569 21833 uid 10723,0 21570 21834 shape (OrthoPolyLine … … 21604 21868 on &434 21605 21869 ) 21606 *7 25(Wire21870 *733 (Wire 21607 21871 uid 10737,0 21608 21872 shape (OrthoPolyLine … … 21642 21906 on &436 21643 21907 ) 21644 *7 26(Wire21908 *734 (Wire 21645 21909 uid 10751,0 21646 21910 shape (OrthoPolyLine … … 21680 21944 on &438 21681 21945 ) 21682 *7 27(Wire21946 *735 (Wire 21683 21947 uid 11405,0 21684 21948 shape (OrthoPolyLine … … 21694 21958 ] 21695 21959 ) 21696 start &6 521960 start &64 21697 21961 sat 32 21698 21962 eat 16 … … 21716 21980 on &452 21717 21981 ) 21718 *7 28(Wire21982 *736 (Wire 21719 21983 uid 11858,0 21720 21984 shape (OrthoPolyLine … … 21729 21993 ] 21730 21994 ) 21731 start &11 321995 start &114 21732 21996 sat 32 21733 21997 eat 16 … … 21751 22015 on &453 21752 22016 ) 21753 *7 29(Wire22017 *737 (Wire 21754 22018 uid 11952,0 21755 22019 shape (OrthoPolyLine … … 21787 22051 on &453 21788 22052 ) 21789 *73 0(Wire22053 *738 (Wire 21790 22054 uid 12306,0 21791 22055 shape (OrthoPolyLine … … 21825 22089 on &472 21826 22090 ) 21827 *73 1(Wire22091 *739 (Wire 21828 22092 uid 12643,0 21829 22093 shape (OrthoPolyLine … … 21865 22129 on &483 21866 22130 ) 21867 *7 32(Wire22131 *740 (Wire 21868 22132 uid 12649,0 21869 22133 shape (OrthoPolyLine … … 21878 22142 ] 21879 22143 ) 21880 start &6 622144 start &65 21881 22145 end &477 21882 22146 sat 32 … … 21901 22165 on &484 21902 22166 ) 21903 *7 33(Wire22167 *741 (Wire 21904 22168 uid 12655,0 21905 22169 shape (OrthoPolyLine … … 21915 22179 ] 21916 22180 ) 21917 start &6 722181 start &66 21918 22182 end &478 21919 22183 sat 32 … … 21938 22202 on &485 21939 22203 ) 21940 *7 34(Wire22204 *742 (Wire 21941 22205 uid 12687,0 21942 22206 shape (OrthoPolyLine … … 21976 22240 on &188 21977 22241 ) 21978 *7 35(Wire22242 *743 (Wire 21979 22243 uid 12707,0 21980 22244 shape (OrthoPolyLine … … 22014 22278 on &486 22015 22279 ) 22016 *7 36(Wire22280 *744 (Wire 22017 22281 uid 13143,0 22018 22282 shape (OrthoPolyLine … … 22049 22313 on &188 22050 22314 ) 22051 *7 37(Wire22315 *745 (Wire 22052 22316 uid 13159,0 22053 22317 shape (OrthoPolyLine … … 22064 22328 ] 22065 22329 ) 22066 start &11 422330 start &115 22067 22331 end &490 22068 22332 sat 32 … … 22087 22351 on &496 22088 22352 ) 22089 *7 38(Wire22353 *746 (Wire 22090 22354 uid 13165,0 22091 22355 shape (OrthoPolyLine … … 22103 22367 ] 22104 22368 ) 22105 start &11 522369 start &116 22106 22370 end &491 22107 22371 sat 32 … … 22127 22391 on &497 22128 22392 ) 22129 *7 39(Wire22393 *747 (Wire 22130 22394 uid 13210,0 22131 22395 shape (OrthoPolyLine … … 22163 22427 on &499 22164 22428 ) 22165 *74 0(Wire22429 *748 (Wire 22166 22430 uid 13216,0 22167 22431 shape (OrthoPolyLine … … 22199 22463 on &498 22200 22464 ) 22201 *74 1(Wire22465 *749 (Wire 22202 22466 uid 13224,0 22203 22467 shape (OrthoPolyLine … … 22235 22499 on &401 22236 22500 ) 22237 *7 42(Wire22501 *750 (Wire 22238 22502 uid 13695,0 22239 22503 shape (OrthoPolyLine … … 22250 22514 ) 22251 22515 start &523 22252 end &11 622516 end &117 22253 22517 sat 32 22254 22518 eat 32 … … 22274 22538 on &524 22275 22539 ) 22276 *7 43(Wire22540 *751 (Wire 22277 22541 uid 13921,0 22278 22542 shape (OrthoPolyLine … … 22288 22552 ] 22289 22553 ) 22290 end &11 722554 end &118 22291 22555 sat 16 22292 22556 eat 32 … … 22309 22573 ) 22310 22574 ) 22311 on &7 122312 ) 22313 *7 44(Wire22575 on &72 22576 ) 22577 *752 (Wire 22314 22578 uid 13929,0 22315 22579 shape (OrthoPolyLine … … 22325 22589 ] 22326 22590 ) 22327 end &11 822591 end &119 22328 22592 sat 16 22329 22593 eat 32 … … 22346 22610 ) 22347 22611 ) 22348 on &12 222349 ) 22350 *7 45(Wire22612 on &123 22613 ) 22614 *753 (Wire 22351 22615 uid 14048,0 22352 22616 shape (OrthoPolyLine … … 22385 22649 on &526 22386 22650 ) 22387 *7 46(Wire22651 *754 (Wire 22388 22652 uid 14171,0 22389 22653 shape (OrthoPolyLine … … 22423 22687 on &528 22424 22688 ) 22425 *7 47(Wire22689 *755 (Wire 22426 22690 uid 14427,0 22427 22691 shape (OrthoPolyLine … … 22458 22722 on &187 22459 22723 ) 22460 *7 48(Wire22724 *756 (Wire 22461 22725 uid 14479,0 22462 22726 shape (OrthoPolyLine … … 22496 22760 on &538 22497 22761 ) 22498 *7 49(Wire22762 *757 (Wire 22499 22763 uid 14493,0 22500 22764 shape (OrthoPolyLine … … 22534 22798 on &540 22535 22799 ) 22536 *75 0(Wire22800 *758 (Wire 22537 22801 uid 14622,0 22538 22802 shape (OrthoPolyLine … … 22574 22838 on &542 22575 22839 ) 22576 *75 1(Wire22840 *759 (Wire 22577 22841 uid 15071,0 22578 22842 shape (OrthoPolyLine … … 22587 22851 ] 22588 22852 ) 22589 start &10 122853 start &102 22590 22854 end &548 22591 22855 sat 32 … … 22610 22874 on &595 22611 22875 ) 22612 *7 52(Wire22876 *760 (Wire 22613 22877 uid 15081,0 22614 22878 shape (OrthoPolyLine … … 22648 22912 on &596 22649 22913 ) 22650 *7 53(Wire22914 *761 (Wire 22651 22915 uid 15122,0 22652 22916 shape (OrthoPolyLine … … 22686 22950 on &597 22687 22951 ) 22688 *7 54(Wire22952 *762 (Wire 22689 22953 uid 15130,0 22690 22954 shape (OrthoPolyLine … … 22724 22988 on &540 22725 22989 ) 22726 *7 55(Wire22990 *763 (Wire 22727 22991 uid 15138,0 22728 22992 shape (OrthoPolyLine … … 22762 23026 on &538 22763 23027 ) 22764 *7 56(Wire23028 *764 (Wire 22765 23029 uid 15379,0 22766 23030 shape (OrthoPolyLine … … 22797 23061 on &188 22798 23062 ) 22799 *7 57(Wire23063 *765 (Wire 22800 23064 uid 15494,0 22801 23065 optionalChildren [ 22802 *7 58(BdJunction23066 *766 (BdJunction 22803 23067 uid 15502,0 22804 23068 ps "OnConnectorStrategy" … … 22825 23089 ) 22826 23090 start &475 22827 end & 3023091 end &29 22828 23092 sat 32 22829 23093 eat 32 … … 22847 23111 on &598 22848 23112 ) 22849 *7 59(Wire23113 *767 (Wire 22850 23114 uid 15498,0 22851 23115 shape (OrthoPolyLine … … 22861 23125 ] 22862 23126 ) 22863 start &12 522864 end &7 5823127 start &126 23128 end &766 22865 23129 sat 32 22866 23130 eat 32 … … 22885 23149 on &598 22886 23150 ) 23151 *768 (Wire 23152 uid 15750,0 23153 shape (OrthoPolyLine 23154 uid 15751,0 23155 va (VaSet 23156 vasetType 3 23157 lineWidth 2 23158 ) 23159 xt "-40250,69000,-21750,70000" 23160 pts [ 23161 "-40250,69000" 23162 "-28000,69000" 23163 "-28000,70000" 23164 "-21750,70000" 23165 ] 23166 ) 23167 start &125 23168 end &67 23169 sat 32 23170 eat 32 23171 sty 1 23172 st 0 23173 sf 1 23174 tg (WTG 23175 uid 15752,0 23176 ps "ConnStartEndStrategy" 23177 stg "STSignalDisplayStrategy" 23178 f (Text 23179 uid 15753,0 23180 va (VaSet 23181 ) 23182 xt "-38250,68000,-31450,69000" 23183 st "trigger_id : (31:0)" 23184 blo "-38250,68800" 23185 tm "WireNameMgr" 23186 ) 23187 ) 23188 on &607 23189 ) 22887 23190 ] 22888 23191 bg "65535,65535,65535" … … 22897 23200 color "26368,26368,26368" 22898 23201 ) 22899 packageList *76 0(PackageList23202 packageList *769 (PackageList 22900 23203 uid 41,0 22901 23204 stg "VerticalLayoutStrategy" 22902 23205 textVec [ 22903 *7 61(Text23206 *770 (Text 22904 23207 uid 42,0 22905 23208 va (VaSet … … 22910 23213 blo "-163000,-15200" 22911 23214 ) 22912 *7 62(MLText23215 *771 (MLText 22913 23216 uid 43,0 22914 23217 va (VaSet 22915 23218 ) 22916 xt "-163000,-15000,-148600,- 3000"23219 xt "-163000,-15000,-148600,-2000" 22917 23220 st "library ieee; 22918 23221 use ieee.std_logic_1164.all; … … 22926 23229 --use UNISIM.VComponents.all; 22927 23230 USE IEEE.NUMERIC_STD.all; 22928 USE IEEE.std_logic_signed.all;" 23231 USE IEEE.std_logic_signed.all; 23232 USE UNISIM.VComponents.all;" 22929 23233 tm "PackageList" 22930 23234 ) … … 22935 23239 stg "VerticalLayoutStrategy" 22936 23240 textVec [ 22937 *7 63(Text23241 *772 (Text 22938 23242 uid 45,0 22939 23243 va (VaSet … … 22945 23249 blo "20000,800" 22946 23250 ) 22947 *7 64(Text23251 *773 (Text 22948 23252 uid 46,0 22949 23253 va (VaSet … … 22955 23259 blo "20000,1800" 22956 23260 ) 22957 *7 65(MLText23261 *774 (MLText 22958 23262 uid 47,0 22959 23263 va (VaSet … … 22965 23269 tm "BdCompilerDirectivesTextMgr" 22966 23270 ) 22967 *7 66(Text23271 *775 (Text 22968 23272 uid 48,0 22969 23273 va (VaSet … … 22975 23279 blo "20000,4800" 22976 23280 ) 22977 *7 67(MLText23281 *776 (MLText 22978 23282 uid 49,0 22979 23283 va (VaSet … … 22983 23287 tm "BdCompilerDirectivesTextMgr" 22984 23288 ) 22985 *7 68(Text23289 *777 (Text 22986 23290 uid 50,0 22987 23291 va (VaSet … … 22993 23297 blo "20000,5800" 22994 23298 ) 22995 *7 69(MLText23299 *778 (MLText 22996 23300 uid 51,0 22997 23301 va (VaSet … … 23005 23309 ) 23006 23310 windowSize "0,0,1281,1024" 23007 viewArea "- 65700,47500,1143,102625"23311 viewArea "-70475,46416,-3930,101296" 23008 23312 cachedDiagramExtent "-174000,-25425,428157,346294" 23009 23313 pageSetupInfo (PageSetupInfo … … 23031 23335 hasePageBreakOrigin 1 23032 23336 pageBreakOrigin "-73000,0" 23033 lastUid 15 505,023337 lastUid 15755,0 23034 23338 defaultCommentText (CommentText 23035 23339 shape (Rectangle … … 23093 23397 stg "VerticalLayoutStrategy" 23094 23398 textVec [ 23095 *77 0(Text23399 *779 (Text 23096 23400 va (VaSet 23097 23401 font "Arial,8,1" … … 23102 23406 tm "BdLibraryNameMgr" 23103 23407 ) 23104 *7 71(Text23408 *780 (Text 23105 23409 va (VaSet 23106 23410 font "Arial,8,1" … … 23111 23415 tm "BlkNameMgr" 23112 23416 ) 23113 *7 72(Text23417 *781 (Text 23114 23418 va (VaSet 23115 23419 font "Arial,8,1" … … 23157 23461 ) 23158 23462 xt "0,0,8000,10000" 23159 )23160 ttg (MlTextGroup23161 ps "CenterOffsetStrategy"23162 stg "VerticalLayoutStrategy"23163 textVec [23164 *773 (Text23165 va (VaSet23166 font "Arial,8,1"23167 )23168 xt "550,3500,3450,4500"23169 st "Library"23170 blo "550,4300"23171 )23172 *774 (Text23173 va (VaSet23174 font "Arial,8,1"23175 )23176 xt "550,4500,7450,5500"23177 st "MWComponent"23178 blo "550,5300"23179 )23180 *775 (Text23181 va (VaSet23182 font "Arial,8,1"23183 )23184 xt "550,5500,2350,6500"23185 st "U_0"23186 blo "550,6300"23187 tm "InstanceNameMgr"23188 )23189 ]23190 )23191 ga (GenericAssociation23192 ps "EdgeToEdgeStrategy"23193 matrix (Matrix23194 text (MLText23195 va (VaSet23196 font "Courier New,8,0"23197 )23198 xt "-6450,1500,-6450,1500"23199 )23200 header ""23201 )23202 elements [23203 ]23204 )23205 portVis (PortSigDisplay23206 )23207 prms (Property23208 pclass "params"23209 pname "params"23210 ptn "String"23211 )23212 visOptions (mwParamsVisibilityOptions23213 )23214 )23215 defaultSaComponent (SaComponent23216 shape (Rectangle23217