Changeset 10155


Ignore:
Timestamp:
02/15/11 12:07:05 (14 years ago)
Author:
neise
Message:
highly unstable version !!!
Location:
firmware/FAD
Files:
5 added
25 edited

Legend:

Unmodified
Added
Removed

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD.hdp

    r10129 r10155  
    55FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/work
    66secureip = D:/unisim/secureip
    7 simprim = D:/unisim/simprim
    8 unimacro = D:/unisim/unimacro
    9 unisim = D:/unisim/unisim
    10 XilinxCoreLib = D:/unisim/xilinxcorelib
     7simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
     8unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
     9unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
     10XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
    1111[QuestaSim]
    1212secureip = D:/unisim/secureip
    13 simprim = D:/unisim/simprim
    14 unimacro = D:/unisim/unimacro
    15 unisim = D:/unisim/unisim
    16 XilinxCoreLib = D:/unisim/xilinxcorelib
     13simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
     14unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
     15unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
     16XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
    1717[XilinxISE]
    1818FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/ise
    19 FACT_FAD_TB_lib = $HDS_PROJECT_DIR\FACT_FAD_TB_lib\ise
     19FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise
    2020[hdl]
    2121FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hdl

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd

    r10129 r10155  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 15:27:49 04.02.2011
     5--          at - 13:26:27 14.02.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    3232-- Created:
    3333--          by - dneise.UNKNOWN (E5B-LABOR6)
    34 --          at - 15:27:49 04.02.2011
     34--          at - 13:26:27 14.02.2011
    3535--
    3636-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    4242LIBRARY UNISIM;
    4343--USE UNISIM.Vcomponents.all;
     44LIBRARY FACT_FAD_lib;
     45USE FACT_FAD_lib.fad_definitions.all;
    4446
    4547LIBRARY FACT_FAD_lib;
    … …  
    5658   SIGNAL PSEN_IN     : std_logic;
    5759   SIGNAL PSINCDEC_IN : std_logic;
     60   SIGNAL rst         : std_logic := '0';    --asynch in of DCM
    5861
    5962   -- Implicit buffer signal declarations
    … …  
    9194   PORT (
    9295      CLK         : IN     std_logic ;
    93       rst         : IN     std_logic ;                                    --asynch in of DCM
     96      rst         : OUT    std_logic                     := '0'; --asynch in of DCM
    9497      -- interface to: clock_generator_variable_PS_struct.vhd
    9598      PSCLK       : OUT    std_logic ;
    9699      PSEN        : OUT    std_logic                     := '0';
    97       PSINCDEC    : OUT    std_logic                     := '1';           -- default is 'incrementing'
    98       PSDONE      : IN     std_logic ;                                     -- will pulse once, if phase shifting was done.
    99       LOCKED      : IN     std_logic ;
     100      PSINCDEC    : OUT    std_logic                     := '1'; -- default is 'incrementing'
     101      PSDONE      : IN     std_logic ;                           -- will pulse once, if phase shifting was done.
     102      LOCKED      : IN     std_logic ;                           -- when is this going high?
    100103      -- interface to: w5300_modul.vhd
    101104      shift_phase : IN     std_logic ;
    102       direction   : IN     std_logic ;                                     -- corresponds TO 'PSINCDEC'
     105      direction   : IN     std_logic ;                           -- corresponds TO 'PSINCDEC'
     106      reset_DCM   : IN     std_logic ;                           -- asynch in: orders us, TO reset the DCM
    103107      -- status:
    104108      shifting    : OUT    std_logic                     := '0';
    105109      ready       : OUT    std_logic                     := '0';
    106       offset      : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    107       DCM_locked  : OUT    std_logic
     110      offset      : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0')
    108111   );
    109112   END COMPONENT;
    … …  
    139142         PSEN_IN     => PSEN_IN,
    140143         PSINCDEC_IN => PSINCDEC_IN,
    141          RST_IN      => RST_IN,
     144         RST_IN      => rst,
    142145         CLK0_OUT    => CLK_25_PS,
    143146         LOCKED_OUT  => LOCKED_OUT,
    … …  
    147150      PORT MAP (
    148151         CLK         => CLK0_OUT,
    149          rst         => RST_IN,
     152         rst         => rst,
    150153         PSCLK       => PSCLK_IN,
    151154         PSEN        => PSEN_IN,
    … …  
    155158         shift_phase => do_shift,
    156159         direction   => direction,
     160         reset_DCM   => RST_IN,
    157161         shifting    => OPEN,
    158162         ready       => OPEN,
    159          offset      => offset,
    160          DCM_locked  => OPEN
     163         offset      => offset
    161164      );
    162165

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd

    r10129 r10155  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 11:39:13 04.02.2011
     5--          at - 13:10:37 12.02.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    4242-- Created:
    4343--          by - dneise.UNKNOWN (E5B-LABOR6)
    44 --          at - 11:39:13 04.02.2011
     44--          at - 13:10:37 12.02.2011
    4545--
    4646-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd

    r10138 r10155  
    4545      sensor_ready : in std_logic;
    4646      dac_array : in dac_array_type;
     47     
     48      -- EVT HEADER - part 1
    4749      package_length : in std_logic_vector (15 downto 0);
     50      pll_lock                                                  : in std_logic_vector ( 3 downto 0);
     51      --
     52           
     53      -- EVT HEADER - part 2  --> FTM trigger informaton, comes in late ...
     54      -- during EVT header wrinting, this field is left out ... and only written into event header,
     55      -- when the DRS chip were read out already.
     56      FTM_RS485_ready : in std_logic;
     57      FTM_trigger_info : in std_logic_vector (55 downto 0); --7 byte
     58      --
     59     
     60                        -- EVT HEADER - part 3
     61      fad_event_counter     : in std_logic_vector (31 downto 0);
     62      refclk_counter    : in std_logic_vector (11 downto 0);
     63      refclk_too_high: in std_logic;
     64      refclk_too_low : in std_logic;
     65      --
     66     
     67      -- EVT HEADER - part 4
    4868      board_id       : in std_logic_vector (3 downto 0);
    4969      crate_id       : in std_logic_vector (1 downto 0);
    50       trigger_id     : in std_logic_vector (47 downto 0);
     70      DCM_PS_status     : in std_logic_vector (7 downto 0);
     71      TRG_GEN_no                                        : in std_logic_vector (15 downto 0);
     72      TRG_GEN_div                                       : in std_logic_vector (15 downto 0);
     73      --
     74     
     75      -- EVT HEADER - part 5
     76      dna                               : in std_logic_vector (63 downto 0);
     77      --
     78     
     79      -- EVT HEADER - part 6
     80      timer_value : in std_logic_vector (31 downto 0); -- time in units of 100us
     81      --
     82     
    5183      trigger        : in std_logic;
    5284--      s_trigger      : in std_logic;
    … …  
    79111architecture Behavioral of data_generator is
    80112
    81 type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
    82                              WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
    83                              WRITE_END_FLAG, WRITE_DATA_STOP, WRITE_DATA_STOP1,
    84                              WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING);
     113type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7,
     114                                WRITE_DATA_IDLE,
     115                                WRITE_HEADER, WRITE_FTM_INFO, WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER, WRITE_BOARD_ID,
     116                                WRITE_DNA, WRITE_TIMER, WRITE_TEMPERATURES,
     117                                WRITE_DAC1, WRITE_DAC2,
     118                                WAIT_FOR_STOP_CELL,
     119                                START_DRS_READING,
     120                                WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_FILLING,
     121                                WAIT_FOR_ADC, WRITE_ADC_DATA,
     122                                WRITE_EXTERNAL_TRIGGER,
     123                                WRITE_END_FLAG,
     124                                WRITE_DATA_END, WRITE_DATA_END_WAIT,
     125                                WRITE_DATA_STOP, WRITE_DATA_STOP1);
    85126
    86127signal state_generate : state_generate_type := INIT;
    … …  
    199240                                when WRITE_HEADER =>
    200241                                  write_ea <= "1";
    201           data_out <= X"0000" & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01";
    202                                         addr_cntr <= addr_cntr + 3;
    203                                         state_generate <= WRITE_BOARD_ID;
    204         when WRITE_BOARD_ID =>     -- crate ID & board ID
    205           data_out <= (63 downto 10 => '0') & crate_id & "1000" & board_id;
    206           addr_cntr <= addr_cntr + 1;
    207           state_generate <= WRITE_TEMPERATURES;
     242          data_out <= X"000" & pll_lock & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01";
     243                                        addr_cntr <= addr_cntr + 1; 
     244                                        state_generate <= WRITE_FTM_INFO;
     245                                       
     246                                when WRITE_FTM_INFO =>
     247                                        -- here we do not write the FTM info ... just jump over it.
     248                                        addr_cntr <= addr_cntr + 1; 
     249                                        state_generate <= WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER;
     250                                       
     251                                when WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER =>
     252                                data_out <= X"0000" &
     253                                                                                        refclk_too_high & refclk_too_low & "00" & refclk_counter &
     254                                                fad_event_counter(15 downto 0) &
     255                                                fad_event_counter(31 downto 16) ;
     256                                addr_cntr <= addr_cntr + 1;
     257                                state_generate <= WRITE_BOARD_ID;
     258                                -- crate ID & board ID
     259                                -- and a lot more...
     260                                        -- info about the phase shifter
     261                                        -- status of the trigger generator
     262        when WRITE_BOARD_ID =>     
     263          data_out <= TRG_GEN_div & TRG_GEN_no & X"00" & DCM_PS_status & "000000" & crate_id & "1000" & board_id;
     264          addr_cntr <= addr_cntr + 1;
     265          state_generate <= WRITE_DNA;
     266         
     267        when WRITE_DNA =>
     268                                data_out <= X"00" & dna(55 downto 0);
     269          addr_cntr <= addr_cntr + 1;
     270          state_generate <= WRITE_TIMER;
     271         
     272        when WRITE_TIMER =>
     273                data_out <= X"0000" & X"0000" & timer_value; -- 2times 16bit reserved for additional status info
     274                        addr_cntr <= addr_cntr + 1;
     275                        state_generate <= WRITE_TEMPERATURES;
     276
    208277        when WRITE_TEMPERATURES =>     -- temperatures
    209278          if (sensor_ready = '1') then
    … …  
    248317
    249318        when WRITE_CHANNEL_ID =>    -- write DRS and Channel IDs
    250           data_out <= conv_std_logic_vector(0,10) & conv_std_logic_vector(3,2) & conv_std_logic_vector(channel_id,4)
    251                     & conv_std_logic_vector(0,10) & conv_std_logic_vector(2,2) & conv_std_logic_vector(channel_id,4)
    252                     & conv_std_logic_vector(0,10) & conv_std_logic_vector(1,2) & conv_std_logic_vector(channel_id,4)
    253                     & conv_std_logic_vector(0,10) & conv_std_logic_vector(0,2) & conv_std_logic_vector(channel_id,4);
     319          data_out <=  conv_std_logic_vector(3,12) & conv_std_logic_vector(channel_id,4)
     320                    &  conv_std_logic_vector(2,12) & conv_std_logic_vector(channel_id,4)
     321                    &  conv_std_logic_vector(1,12) & conv_std_logic_vector(channel_id,4)
     322                    &  conv_std_logic_vector(0,12) & conv_std_logic_vector(channel_id,4);
    254323          addr_cntr <= addr_cntr + 1;
    255324          state_generate <= WRITE_START_CELL;
    … …  
    267336                    & "00000" & conv_std_logic_vector (roi_array((0) * 9 + channel_id), 11);
    268337          addr_cntr <= addr_cntr + 1;
    269           state_generate <= WAIT_FOR_ADC;
     338          state_generate <= WRITE_FILLING;
     339         
     340                when WRITE_FILLING =>    -- write FILLING
     341                                                data_out <= conv_std_logic_vector(0,64); -- filling
     342                                                addr_cntr <= addr_cntr + 1;
     343                                                state_generate <= WAIT_FOR_ADC;
     344 
    270345        when WAIT_FOR_ADC =>
    271346          -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
    … …  
    281356                      & "000" & adc_otr(1) & adc_data_array(1)
    282357                      & "000" & adc_otr(0) & adc_data_array(0);
    283  --             data_out <= "00000" & conv_std_logic_vector (data_cntr, 11)
     358--             data_out <= "00000" & conv_std_logic_vector (data_cntr, 11)
    284359--                          & "00010" & conv_std_logic_vector (data_cntr, 11)
    285360--                          & "00100" & conv_std_logic_vector (data_cntr, 11)
    … …  
    303378          end if;
    304379         
    305          
    306380        when WRITE_EXTERNAL_TRIGGER =>    -- external trigger ID
    307381          addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH);
    308 --          data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16);
    309           data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16);
    310           state_generate <= WRITE_INTERNAL_TRIGGER;
    311         when WRITE_INTERNAL_TRIGGER =>    -- internal trigger ID
    312           addr_out <= start_addr + conv_std_logic_vector(2, RAM_ADDR_WIDTH);
    313           data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16);
     382          data_out <=           FTM_trigger_info(15 downto 0)
     383                                                                                                & FTM_trigger_info(31 downto 16)
     384                                                                                                & FTM_trigger_info(47 downto 32)
     385                                                                                                & X"00" & FTM_trigger_info(55 downto 48);
    314386          state_generate <= WRITE_END_FLAG;
     387       
    315388                                when WRITE_END_FLAG =>
    316389          data_out <= (63 downto 32 => '0') & X"04FE" & X"4242";

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd

    r10129 r10155  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 15:27:51 04.02.2011
     5--          at - 13:26:28 14.02.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    7676-- Created:
    7777--          by - dneise.UNKNOWN (E5B-LABOR6)
    78 --          at - 15:27:51 04.02.2011
     78--          at - 13:26:28 14.02.2011
    7979--
    8080-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd

    r10138 r10155  
    5656  constant PACKAGE_HEADER_LENGTH : integer := 22;
    5757  constant PACKAGE_END_LENGTH : integer := 2; -- CRC and END-Flag
     58  constant CHANNEL_HEADER_SIZE : integer := 3;
    5859 
    5960  constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd

    r10129 r10155  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 15:27:49 04.02.2011
     5--          at - 13:26:27 14.02.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    7272-- Created:
    7373--          by - dneise.UNKNOWN (E5B-LABOR6)
    74 --          at - 15:27:50 04.02.2011
     74--          at - 13:26:28 14.02.2011
    7575--
    7676-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    171171   SIGNAL trigger_enable         : std_logic;
    172172   SIGNAL trigger_id             : std_logic_vector(47 DOWNTO 0);
    173    SIGNAL trigger_out            : std_logic;
     173   SIGNAL trigger_out            : std_logic                                    := '0';
    174174   SIGNAL wiz_ack                : std_logic;
    175175   SIGNAL wiz_busy               : std_logic;
    … …  
    451451      c_trigger_enable  : OUT    std_logic                      := '0';
    452452      c_trigger_mult    : OUT    std_logic_vector (7 DOWNTO 0)  := (OTHERS => '1'); --subject TO changes
    453       --
     453      -- FAD configuration signals:
     454      ------------------------------------------------------------------------------
     455      -- start entire configuration chain
    454456      new_config        : OUT    std_logic                      := '0';
    455457      config_started    : IN     std_logic ;
     458      -- read/write configRAM
    456459      config_addr       : OUT    std_logic_vector (7 DOWNTO 0);
    457460      config_data       : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z');
    458461      config_wr_en      : OUT    std_logic                      := '0';
    459462      config_rd_en      : OUT    std_logic                      := '0';
    460       -- --
    461463      config_rw_ack     : IN     std_logic ;
    462       -- --
    463464      config_rw_ready   : IN     std_logic ;
    464       -- --
    465465      config_busy       : IN     std_logic ;
     466      ------------------------------------------------------------------------------
     467     
     468      -- MAC/IP calculation signals:
     469      ------------------------------------------------------------------------------
    466470      MAC_jumper        : IN     std_logic_vector (1 DOWNTO 0);
    467471      BoardID           : IN     std_logic_vector (3 DOWNTO 0);
    468472      CrateID           : IN     std_logic_vector (1 DOWNTO 0);
     473      ------------------------------------------------------------------------------
     474     
     475      -- user controllable enable signals
     476      ------------------------------------------------------------------------------
     477      trigger_enable    : OUT    std_logic                      := '0';             -- default triggers are NOT accepted
    469478      denable           : OUT    std_logic                      := '0';             -- default domino wave off
    470479      dwrite_enable     : OUT    std_logic                      := '0';             -- default DWRITE low.
    471480      sclk_enable       : OUT    std_logic                      := '1';             -- default DWRITE HIGH.
     481      srclk_enable      : OUT    std_logic                      := '1';             -- default SRCLK on.
     482      ------------------------------------------------------------------------------
     483     
     484      -- ADC CLK generator, is able to shift phase with respect to X_50M
     485      -- these signals control the behavior of the digital clock manager (DCM)
     486      ------------------------------------------------------------------------------
    472487      ps_direction      : OUT    std_logic                      := '1';             -- default phase shift upwards
    473488      ps_do_phase_shift : OUT    std_logic                      := '0';             --pulse this TO phase shift once
    474489      ps_reset          : OUT    std_logic                      := '0';             -- pulse this TO reset the variable phase shift
    475       srclk_enable      : OUT    std_logic                      := '1';             -- default SRCLK on.
    476       trigger_enable    : OUT    std_logic                      := '0';             -- default triggers are NOT accepted
     490      ------------------------------------------------------------------------------
     491     
     492      -- signals used to control FAD LED bahavior:
     493      -- one of the three LEDs is used for com-status info
     494      ------------------------------------------------------------------------------
    477495      socks_waiting     : OUT    std_logic ;
    478496      socks_connected   : OUT    std_logic
     497      ------------------------------------------------------------------------------
    479498   );
    480499   END COMPONENT;

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd

    r10072 r10155  
    5151      wiz_write_end : OUT std_logic := '0';
    5252      wiz_busy : IN std_logic;
    53           wiz_ack : IN std_logic;
     53            wiz_ack : IN std_logic;
    5454      ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0')
    5555   );
    … …  
    134134              roi_max_array (channel_id) <= temp_roi;
    135135            end if;
    136             channel_size (channel_id) <= channel_size (channel_id) + temp_roi + 3;
     136            channel_size (channel_id) <= channel_size (channel_id) + temp_roi + CHANNEL_HEADER_SIZE;
    137137            drs_id <= drs_id + 1;
    138138            state_mm <= MAX_ROI;

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd

    r10154 r10155  
    3535                shifting : OUT std_logic := '0';
    3636                ready : OUT std_logic := '0';
     37               
    3738                offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0')
    3839               
    … …  
    9394
    9495        -- MAIN FSM
    95         FSM: process(state, PSDONE, LOCKED, shift_phase, direction, local_direction)
     96        FSM: process(CLK)
    9697        begin
    9798       
    … …  
    144145                        end if;
    145146                       
    146                         if (reset_dcm_sr = "01") then
     147                        if (reset_dcm_sr = "01") then   
    147148                                state <= RESET_STATE;
    148149                        end if;

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd

    r10129 r10155  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 16:13:08 03.02.2011
     5--          at - 13:10:37 12.02.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    3838-- Created:
    3939--          by - dneise.UNKNOWN (E5B-LABOR6)
    40 --          at - 16:13:08 03.02.2011
     40--          at - 13:10:37 12.02.2011
    4141--
    4242-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/trigger_counter_beha.vhd

    r9912 r10155  
    1616entity trigger_counter is
    1717  port(
    18     trigger_id : out std_logic_vector(47 downto 0);
     18    trigger_id : out std_logic_vector(31 downto 0);
    1919    trigger : in std_logic;
    2020    clk : in std_logic
    … …  
    2929begin
    3030 
    31   trigger_id <= X"AA55" & conv_std_logic_vector(temp_id, 32);
     31  trigger_id <= conv_std_logic_vector(temp_id, 32);
    3232 
    3333  trigger_incr_proc: process(clk)

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/clock_generator_var_ps_struct.xrf

    r10129 r10155  
    4343DESIGN clock_generator_var_ps
    4444VIEW struct.bd
    45 NO_GRAPHIC 43
    46 DESIGN clock_generator_var_ps
    47 VIEW struct.bd
    48 GRAPHIC 0,0 46 2
    49 DESIGN clock_generator_var_ps
    50 VIEW struct.bd
    51 GRAPHIC 524,0 51 0
    52 DESIGN clock_generator_var_ps
    53 VIEW struct.bd
    54 GRAPHIC 600,0 52 0
    55 DESIGN clock_generator_var_ps
    56 VIEW struct.bd
    57 GRAPHIC 530,0 53 0
    58 DESIGN clock_generator_var_ps
    59 VIEW struct.bd
    60 GRAPHIC 586,0 54 0
    61 DESIGN clock_generator_var_ps
    62 VIEW struct.bd
    63 GRAPHIC 544,0 55 0
    64 DESIGN clock_generator_var_ps
    65 VIEW struct.bd
    66 GRAPHIC 558,0 56 0
    67 DESIGN clock_generator_var_ps
    68 VIEW struct.bd
    69 NO_GRAPHIC 57
    70 DESIGN clock_generator_var_ps
    71 VIEW struct.bd
    72 GRAPHIC 229,0 59 0
    73 DESIGN clock_generator_var_ps
    74 VIEW struct.bd
    75 NO_GRAPHIC 61
     45NO_GRAPHIC 45
     46DESIGN clock_generator_var_ps
     47VIEW struct.bd
     48GRAPHIC 0,0 48 2
     49DESIGN clock_generator_var_ps
     50VIEW struct.bd
     51GRAPHIC 524,0 53 0
     52DESIGN clock_generator_var_ps
     53VIEW struct.bd
     54GRAPHIC 600,0 54 0
     55DESIGN clock_generator_var_ps
     56VIEW struct.bd
     57GRAPHIC 530,0 55 0
     58DESIGN clock_generator_var_ps
     59VIEW struct.bd
     60GRAPHIC 586,0 56 0
     61DESIGN clock_generator_var_ps
     62VIEW struct.bd
     63GRAPHIC 544,0 57 0
     64DESIGN clock_generator_var_ps
     65VIEW struct.bd
     66GRAPHIC 558,0 58 0
     67DESIGN clock_generator_var_ps
     68VIEW struct.bd
     69GRAPHIC 1979,0 59 0
     70DESIGN clock_generator_var_ps
     71VIEW struct.bd
     72NO_GRAPHIC 60
     73DESIGN clock_generator_var_ps
     74VIEW struct.bd
     75GRAPHIC 229,0 62 0
     76DESIGN clock_generator_var_ps
     77VIEW struct.bd
     78NO_GRAPHIC 64
    7679LIBRARY FACT_FAD_lib
    7780DESIGN dcm_50_to_25
    7881VIEW @b@e@h@a@v@i@o@r@a@l
    79 GRAPHIC 403,0 63 0
    80 DESIGN clock_generator_var_ps
    81 VIEW struct.bd
    82 NO_GRAPHIC 69
    83 DESIGN clock_generator_var_ps
    84 VIEW struct.bd
    85 GRAPHIC 354,0 71 0
    86 DESIGN clock_generator_var_ps
    87 VIEW struct.bd
    88 NO_GRAPHIC 75
    89 DESIGN clock_generator_var_ps
    90 VIEW struct.bd
    91 GRAPHIC 514,0 77 0
    92 DESIGN clock_generator_var_ps
    93 VIEW struct.bd
    94 NO_GRAPHIC 87
    95 DESIGN clock_generator_var_ps
    96 VIEW struct.bd
    97 GRAPHIC 826,0 89 0
    98 DESIGN phase_shifter
    99 VIEW first_behave
    100 GRAPHIC 48,0 91 0
    101 DESIGN phase_shifter
    102 VIEW first_behave
    103 GRAPHIC 281,0 92 0
    104 DESIGN phase_shifter
    105 VIEW first_behave
    106 GRAPHIC 53,0 93 0
    107 DESIGN phase_shifter
    108 VIEW first_behave
    109 GRAPHIC 58,0 95 0
    110 DESIGN phase_shifter
    111 VIEW first_behave
    112 GRAPHIC 63,0 96 0
    113 DESIGN phase_shifter
    114 VIEW first_behave
    115 GRAPHIC 68,0 97 0
    116 DESIGN phase_shifter
    117 VIEW first_behave
    118 GRAPHIC 73,0 98 0
    119 DESIGN phase_shifter
    120 VIEW first_behave
    121 GRAPHIC 83,0 99 0
    122 DESIGN phase_shifter
    123 VIEW first_behave
    124 GRAPHIC 88,0 101 0
    125 DESIGN phase_shifter
    126 VIEW first_behave
    127 GRAPHIC 93,0 102 0
    128 DESIGN phase_shifter
    129 VIEW first_behave
    130 GRAPHIC 98,0 104 0
    131 DESIGN phase_shifter
    132 VIEW first_behave
    133 GRAPHIC 103,0 105 0
    134 DESIGN phase_shifter
    135 VIEW first_behave
    136 GRAPHIC 108,0 106 0
     82GRAPHIC 403,0 66 0
     83DESIGN clock_generator_var_ps
     84VIEW struct.bd
     85NO_GRAPHIC 72
     86DESIGN clock_generator_var_ps
     87VIEW struct.bd
     88GRAPHIC 354,0 74 0
     89DESIGN clock_generator_var_ps
     90VIEW struct.bd
     91NO_GRAPHIC 78
     92DESIGN clock_generator_var_ps
     93VIEW struct.bd
     94GRAPHIC 514,0 80 0
     95DESIGN clock_generator_var_ps
     96VIEW struct.bd
     97NO_GRAPHIC 90
     98DESIGN clock_generator_var_ps
     99VIEW struct.bd
     100GRAPHIC 826,0 92 0
     101DESIGN phase_shifter
     102VIEW first_behave
     103GRAPHIC 48,0 94 0
     104DESIGN phase_shifter
     105VIEW first_behave
     106GRAPHIC 281,0 95 0
     107DESIGN phase_shifter
     108VIEW first_behave
     109GRAPHIC 53,0 96 0
     110DESIGN phase_shifter
     111VIEW first_behave
     112GRAPHIC 58,0 98 0
     113DESIGN phase_shifter
     114VIEW first_behave
     115GRAPHIC 63,0 99 0
     116DESIGN phase_shifter
     117VIEW first_behave
     118GRAPHIC 68,0 100 0
     119DESIGN phase_shifter
     120VIEW first_behave
     121GRAPHIC 73,0 101 0
     122DESIGN phase_shifter
     123VIEW first_behave
     124GRAPHIC 83,0 102 0
     125DESIGN phase_shifter
     126VIEW first_behave
     127GRAPHIC 88,0 104 0
     128DESIGN phase_shifter
     129VIEW first_behave
     130GRAPHIC 362,0 105 0
     131DESIGN phase_shifter
     132VIEW first_behave
     133GRAPHIC 93,0 106 0
     134DESIGN phase_shifter
     135VIEW first_behave
     136GRAPHIC 98,0 108 0
     137DESIGN phase_shifter
     138VIEW first_behave
     139GRAPHIC 103,0 109 0
    137140LIBRARY FACT_FAD_lib
    138141DESIGN clock_generator_var_ps
    139142VIEW struct.bd
    140 NO_GRAPHIC 109
    141 DESIGN clock_generator_var_ps
    142 VIEW struct.bd
    143 GRAPHIC 403,0 112 0
    144 DESIGN clock_generator_var_ps
    145 VIEW struct.bd
    146 GRAPHIC 354,0 113 0
    147 DESIGN clock_generator_var_ps
    148 VIEW struct.bd
    149 GRAPHIC 514,0 114 0
    150 DESIGN clock_generator_var_ps
    151 VIEW struct.bd
    152 GRAPHIC 826,0 115 0
    153 DESIGN clock_generator_var_ps
    154 VIEW struct.bd
    155 NO_GRAPHIC 118
    156 DESIGN clock_generator_var_ps
    157 VIEW struct.bd
    158 NO_GRAPHIC 120
    159 DESIGN clock_generator_var_ps
    160 VIEW struct.bd
    161 GRAPHIC 403,0 122 0
    162 DESIGN clock_generator_var_ps
    163 VIEW struct.bd
    164 GRAPHIC 163,0 124 0
    165 DESIGN clock_generator_var_ps
    166 VIEW struct.bd
    167 GRAPHIC 209,0 125 0
    168 DESIGN clock_generator_var_ps
    169 VIEW struct.bd
    170 GRAPHIC 191,0 127 0
    171 DESIGN clock_generator_var_ps
    172 VIEW struct.bd
    173 GRAPHIC 354,0 129 0
    174 DESIGN clock_generator_var_ps
    175 VIEW struct.bd
    176 GRAPHIC 229,0 131 0
    177 DESIGN clock_generator_var_ps
    178 VIEW struct.bd
    179 GRAPHIC 526,0 132 0
    180 DESIGN clock_generator_var_ps
    181 VIEW struct.bd
    182 GRAPHIC 514,0 134 0
    183 DESIGN clock_generator_var_ps
    184 VIEW struct.bd
    185 GRAPHIC 526,0 136 0
    186 DESIGN clock_generator_var_ps
    187 VIEW struct.bd
    188 GRAPHIC 532,0 137 0
    189 DESIGN clock_generator_var_ps
    190 VIEW struct.bd
    191 GRAPHIC 546,0 138 0
    192 DESIGN clock_generator_var_ps
    193 VIEW struct.bd
    194 GRAPHIC 841,0 139 0
    195 DESIGN clock_generator_var_ps
    196 VIEW struct.bd
    197 GRAPHIC 1493,0 140 0
    198 DESIGN clock_generator_var_ps
    199 VIEW struct.bd
    200 GRAPHIC 1254,0 141 0
    201 DESIGN clock_generator_var_ps
    202 VIEW struct.bd
    203 GRAPHIC 602,0 142 0
    204 DESIGN clock_generator_var_ps
    205 VIEW struct.bd
    206 GRAPHIC 588,0 143 0
    207 DESIGN clock_generator_var_ps
    208 VIEW struct.bd
    209 GRAPHIC 826,0 145 0
    210 DESIGN clock_generator_var_ps
    211 VIEW struct.bd
    212 GRAPHIC 1458,0 147 0
    213 DESIGN clock_generator_var_ps
    214 VIEW struct.bd
    215 GRAPHIC 1625,0 148 0
    216 DESIGN clock_generator_var_ps
    217 VIEW struct.bd
    218 GRAPHIC 532,0 149 0
    219 DESIGN clock_generator_var_ps
    220 VIEW struct.bd
    221 GRAPHIC 546,0 150 0
    222 DESIGN clock_generator_var_ps
    223 VIEW struct.bd
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    225 DESIGN clock_generator_var_ps
    226 VIEW struct.bd
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    228 DESIGN clock_generator_var_ps
    229 VIEW struct.bd
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    231 DESIGN clock_generator_var_ps
    232 VIEW struct.bd
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    234 DESIGN clock_generator_var_ps
    235 VIEW struct.bd
    236 GRAPHIC 1286,0 155 0
    237 DESIGN clock_generator_var_ps
    238 VIEW struct.bd
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    240 DESIGN clock_generator_var_ps
    241 VIEW struct.bd
    242 GRAPHIC 229,0 163 0
    243 DESIGN clock_generator_var_ps
    244 VIEW struct.bd
    245 NO_GRAPHIC 165
     143NO_GRAPHIC 112
     144DESIGN clock_generator_var_ps
     145VIEW struct.bd
     146GRAPHIC 403,0 115 0
     147DESIGN clock_generator_var_ps
     148VIEW struct.bd
     149GRAPHIC 354,0 116 0
     150DESIGN clock_generator_var_ps
     151VIEW struct.bd
     152GRAPHIC 514,0 117 0
     153DESIGN clock_generator_var_ps
     154VIEW struct.bd
     155GRAPHIC 826,0 118 0
     156DESIGN clock_generator_var_ps
     157VIEW struct.bd
     158NO_GRAPHIC 121
     159DESIGN clock_generator_var_ps
     160VIEW struct.bd
     161NO_GRAPHIC 123
     162DESIGN clock_generator_var_ps
     163VIEW struct.bd
     164GRAPHIC 403,0 125 0
     165DESIGN clock_generator_var_ps
     166VIEW struct.bd
     167GRAPHIC 163,0 127 0
     168DESIGN clock_generator_var_ps
     169VIEW struct.bd
     170GRAPHIC 209,0 128 0
     171DESIGN clock_generator_var_ps
     172VIEW struct.bd
     173GRAPHIC 191,0 130 0
     174DESIGN clock_generator_var_ps
     175VIEW struct.bd
     176GRAPHIC 354,0 132 0
     177DESIGN clock_generator_var_ps
     178VIEW struct.bd
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     180DESIGN clock_generator_var_ps
     181VIEW struct.bd
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     183DESIGN clock_generator_var_ps
     184VIEW struct.bd
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     186DESIGN clock_generator_var_ps
     187VIEW struct.bd
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     189DESIGN clock_generator_var_ps
     190VIEW struct.bd
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     192DESIGN clock_generator_var_ps
     193VIEW struct.bd
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     195DESIGN clock_generator_var_ps
     196VIEW struct.bd
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     198DESIGN clock_generator_var_ps
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     201DESIGN clock_generator_var_ps
     202VIEW struct.bd
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     204DESIGN clock_generator_var_ps
     205VIEW struct.bd
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     207DESIGN clock_generator_var_ps
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     210DESIGN clock_generator_var_ps
     211VIEW struct.bd
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     213DESIGN clock_generator_var_ps
     214VIEW struct.bd
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     216DESIGN clock_generator_var_ps
     217VIEW struct.bd
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     219DESIGN clock_generator_var_ps
     220VIEW struct.bd
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     222DESIGN clock_generator_var_ps
     223VIEW struct.bd
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     225DESIGN clock_generator_var_ps
     226VIEW struct.bd
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     228DESIGN clock_generator_var_ps
     229VIEW struct.bd
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     231DESIGN clock_generator_var_ps
     232VIEW struct.bd
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     234DESIGN clock_generator_var_ps
     235VIEW struct.bd
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     237DESIGN clock_generator_var_ps
     238VIEW struct.bd
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     240DESIGN clock_generator_var_ps
     241VIEW struct.bd
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     243DESIGN clock_generator_var_ps
     244VIEW struct.bd
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     246DESIGN clock_generator_var_ps
     247VIEW struct.bd
     248GRAPHIC 229,0 166 0
     249DESIGN clock_generator_var_ps
     250VIEW struct.bd
     251NO_GRAPHIC 168

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf

    r10129 r10155  
    367367DESIGN @f@a@d_main
    368368VIEW struct.bd
    369 GRAPHIC 10449,0 172 0
     369GRAPHIC 15492,0 172 0
    370370DESIGN @f@a@d_main
    371371VIEW struct.bd
    … …  
    884884DESIGN w5300_modul
    885885VIEW @behavioral
    886 GRAPHIC 566,0 454 0
    887 DESIGN w5300_modul
    888 VIEW @behavioral
    889 GRAPHIC 551,0 455 0
    890 DESIGN w5300_modul
    891 VIEW @behavioral
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    893 DESIGN w5300_modul
    894 VIEW @behavioral
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    896 DESIGN w5300_modul
    897 VIEW @behavioral
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    903 VIEW @behavioral
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    906 VIEW @behavioral
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     888VIEW @behavioral
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     891VIEW @behavioral
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     894VIEW @behavioral
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     897VIEW @behavioral
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     900VIEW @behavioral
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     903VIEW @behavioral
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     906VIEW @behavioral
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    909909VIEW @behavioral
    … …  
    911911DESIGN w5300_modul
    912912VIEW @behavioral
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    915 VIEW @behavioral
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    918 VIEW @behavioral
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    921 VIEW @behavioral
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    924 VIEW @behavioral
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     915VIEW @behavioral
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     924VIEW @behavioral
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     930VIEW @behavioral
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     936VIEW @behavioral
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     939VIEW @behavioral
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     942VIEW @behavioral
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     944DESIGN w5300_modul
     945VIEW @behavioral
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    947947LIBRARY FACT_FAD_lib
    948948DESIGN @f@a@d_main
    949949VIEW struct.bd
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    951 DESIGN @f@a@d_main
    952 VIEW struct.bd
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    967 VIEW struct.bd
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    970 VIEW struct.bd
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    985 VIEW struct.bd
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    988 VIEW struct.bd
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    991 VIEW struct.bd
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    994 VIEW struct.bd
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    996951DESIGN @f@a@d_main
    997952VIEW struct.bd
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    1020 DESIGN @f@a@d_main
    1021 VIEW struct.bd
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    1024 VIEW struct.bd
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     1311DESIGN @f@a@d_main
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     1314DESIGN @f@a@d_main
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     1329DESIGN @f@a@d_main
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     1332DESIGN @f@a@d_main
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     1335DESIGN @f@a@d_main
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     1338DESIGN @f@a@d_main
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     1341DESIGN @f@a@d_main
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     1344DESIGN @f@a@d_main
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     1347DESIGN @f@a@d_main
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     1350DESIGN @f@a@d_main
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     1353DESIGN @f@a@d_main
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     1356DESIGN @f@a@d_main
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     1359DESIGN @f@a@d_main
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     1362DESIGN @f@a@d_main
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     1365DESIGN @f@a@d_main
     1366VIEW struct.bd
     1367GRAPHIC 11209,0 684 0
     1368DESIGN @f@a@d_main
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     1370GRAPHIC 11216,0 685 1
     1371DESIGN @f@a@d_main
     1372VIEW struct.bd
     1373GRAPHIC 10699,0 691 0
     1374DESIGN @f@a@d_main
     1375VIEW struct.bd
     1376GRAPHIC 10723,0 692 0
     1377DESIGN @f@a@d_main
     1378VIEW struct.bd
     1379GRAPHIC 10737,0 693 0
     1380DESIGN @f@a@d_main
     1381VIEW struct.bd
     1382GRAPHIC 10751,0 694 0
     1383DESIGN @f@a@d_main
     1384VIEW struct.bd
     1385GRAPHIC 12707,0 695 0
     1386DESIGN @f@a@d_main
     1387VIEW struct.bd
     1388GRAPHIC 10707,0 696 0
     1389DESIGN @f@a@d_main
     1390VIEW struct.bd
     1391GRAPHIC 10685,0 697 0
     1392DESIGN @f@a@d_main
     1393VIEW struct.bd
     1394GRAPHIC 10691,0 698 0
     1395DESIGN @f@a@d_main
     1396VIEW struct.bd
     1397GRAPHIC 2311,0 700 0
     1398DESIGN @f@a@d_main
     1399VIEW struct.bd
     1400GRAPHIC 2318,0 701 1
     1401DESIGN @f@a@d_main
     1402VIEW struct.bd
     1403GRAPHIC 15379,0 706 0
     1404DESIGN @f@a@d_main
     1405VIEW struct.bd
     1406GRAPHIC 2588,0 707 0
     1407DESIGN @f@a@d_main
     1408VIEW struct.bd
     1409GRAPHIC 2582,0 708 0
     1410DESIGN @f@a@d_main
     1411VIEW struct.bd
     1412GRAPHIC 10467,0 709 0
     1413DESIGN @f@a@d_main
     1414VIEW struct.bd
     1415GRAPHIC 5168,0 710 0
     1416DESIGN @f@a@d_main
     1417VIEW struct.bd
     1418GRAPHIC 2576,0 711 0
     1419DESIGN @f@a@d_main
     1420VIEW struct.bd
     1421GRAPHIC 2594,0 712 0
     1422DESIGN @f@a@d_main
     1423VIEW struct.bd
     1424GRAPHIC 6018,0 713 0
     1425DESIGN @f@a@d_main
     1426VIEW struct.bd
     1427GRAPHIC 2600,0 714 0
     1428DESIGN @f@a@d_main
     1429VIEW struct.bd
     1430GRAPHIC 2642,0 715 0
     1431DESIGN @f@a@d_main
     1432VIEW struct.bd
     1433GRAPHIC 2488,0 716 0
     1434DESIGN @f@a@d_main
     1435VIEW struct.bd
     1436GRAPHIC 2482,0 717 0
     1437DESIGN @f@a@d_main
     1438VIEW struct.bd
     1439GRAPHIC 2494,0 718 0
     1440DESIGN @f@a@d_main
     1441VIEW struct.bd
     1442GRAPHIC 2476,0 719 0
     1443DESIGN @f@a@d_main
     1444VIEW struct.bd
     1445GRAPHIC 2506,0 720 0
     1446DESIGN @f@a@d_main
     1447VIEW struct.bd
     1448GRAPHIC 2500,0 721 0
     1449DESIGN @f@a@d_main
     1450VIEW struct.bd
     1451GRAPHIC 2470,0 722 0
     1452DESIGN @f@a@d_main
     1453VIEW struct.bd
     1454GRAPHIC 8416,0 723 0
     1455DESIGN @f@a@d_main
     1456VIEW struct.bd
     1457GRAPHIC 2299,0 724 0
     1458DESIGN @f@a@d_main
     1459VIEW struct.bd
     1460GRAPHIC 5793,0 726 0
     1461DESIGN @f@a@d_main
     1462VIEW struct.bd
     1463GRAPHIC 5805,0 728 0
     1464DESIGN @f@a@d_main
     1465VIEW struct.bd
     1466GRAPHIC 5745,0 729 0
     1467DESIGN @f@a@d_main
     1468VIEW struct.bd
     1469GRAPHIC 5146,0 730 0
     1470DESIGN @f@a@d_main
     1471VIEW struct.bd
     1472GRAPHIC 5404,0 731 0
     1473DESIGN @f@a@d_main
     1474VIEW struct.bd
     1475GRAPHIC 6008,0 732 0
     1476DESIGN @f@a@d_main
     1477VIEW struct.bd
     1478GRAPHIC 5829,0 733 0
     1479DESIGN @f@a@d_main
     1480VIEW struct.bd
     1481GRAPHIC 6160,0 734 0
     1482DESIGN @f@a@d_main
     1483VIEW struct.bd
     1484GRAPHIC 8732,0 735 0
     1485DESIGN @f@a@d_main
     1486VIEW struct.bd
     1487GRAPHIC 5480,0 736 0
     1488DESIGN @f@a@d_main
     1489VIEW struct.bd
     1490GRAPHIC 5837,0 737 0
     1491DESIGN @f@a@d_main
     1492VIEW struct.bd
     1493GRAPHIC 5474,0 738 0
     1494DESIGN @f@a@d_main
     1495VIEW struct.bd
     1496GRAPHIC 5821,0 739 0
     1497DESIGN @f@a@d_main
     1498VIEW struct.bd
     1499GRAPHIC 1768,0 741 0
     1500DESIGN @f@a@d_main
     1501VIEW struct.bd
     1502GRAPHIC 1983,0 743 0
     1503DESIGN @f@a@d_main
     1504VIEW struct.bd
     1505GRAPHIC 15498,0 744 0
     1506DESIGN @f@a@d_main
     1507VIEW struct.bd
     1508GRAPHIC 6276,0 745 0
     1509DESIGN @f@a@d_main
     1510VIEW struct.bd
     1511GRAPHIC 12625,0 747 0
     1512DESIGN @f@a@d_main
     1513VIEW struct.bd
     1514GRAPHIC 12687,0 749 0
     1515DESIGN @f@a@d_main
     1516VIEW struct.bd
     1517GRAPHIC 12643,0 750 0
     1518DESIGN @f@a@d_main
     1519VIEW struct.bd
     1520GRAPHIC 15494,0 751 0
     1521DESIGN @f@a@d_main
     1522VIEW struct.bd
     1523GRAPHIC 6540,0 752 0
     1524DESIGN @f@a@d_main
     1525VIEW struct.bd
     1526GRAPHIC 12649,0 753 0
     1527DESIGN @f@a@d_main
     1528VIEW struct.bd
     1529GRAPHIC 12655,0 754 0
     1530DESIGN @f@a@d_main
     1531VIEW struct.bd
     1532GRAPHIC 1606,0 756 0
     1533DESIGN @f@a@d_main
     1534VIEW struct.bd
     1535GRAPHIC 1613,0 757 1
     1536DESIGN @f@a@d_main
     1537VIEW struct.bd
     1538GRAPHIC 3888,0 761 0
     1539DESIGN @f@a@d_main
     1540VIEW struct.bd
     1541GRAPHIC 376,0 762 0
     1542DESIGN @f@a@d_main
     1543VIEW struct.bd
     1544GRAPHIC 384,0 763 0
     1545DESIGN @f@a@d_main
     1546VIEW struct.bd
     1547GRAPHIC 392,0 764 0
     1548DESIGN @f@a@d_main
     1549VIEW struct.bd
     1550GRAPHIC 400,0 765 0
     1551DESIGN @f@a@d_main
     1552VIEW struct.bd
     1553GRAPHIC 408,0 766 0
     1554DESIGN @f@a@d_main
     1555VIEW struct.bd
     1556GRAPHIC 5222,0 767 0
     1557DESIGN @f@a@d_main
     1558VIEW struct.bd
     1559GRAPHIC 424,0 768 0
     1560DESIGN @f@a@d_main
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     1562GRAPHIC 432,0 769 0
     1563DESIGN @f@a@d_main
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     1566DESIGN @f@a@d_main
     1567VIEW struct.bd
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     1569DESIGN @f@a@d_main
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     1572DESIGN @f@a@d_main
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     1575DESIGN @f@a@d_main
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     1578DESIGN @f@a@d_main
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     1581DESIGN @f@a@d_main
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     1584DESIGN @f@a@d_main
     1585VIEW struct.bd
     1586GRAPHIC 2506,0 777 0
     1587DESIGN @f@a@d_main
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     1590DESIGN @f@a@d_main
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     1593DESIGN @f@a@d_main
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     1596DESIGN @f@a@d_main
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     1599DESIGN @f@a@d_main
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     1611DESIGN @f@a@d_main
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     1614DESIGN @f@a@d_main
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     1617DESIGN @f@a@d_main
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     1620DESIGN @f@a@d_main
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     1623DESIGN @f@a@d_main
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     1626DESIGN @f@a@d_main
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     1629DESIGN @f@a@d_main
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     1632DESIGN @f@a@d_main
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  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd

    r10138 r10155  
    2626library "IEEE"
    2727unitName "std_logic_signed"
     28)
     29(DmPackageRef
     30library "UNISIM"
     31unitName "VComponents"
    2832)
    2933]
    … …  
    278282uid 15058,0
    279283)
     284(Instance
     285name "U_0"
     286duLibraryName "FACT_FAD_lib"
     287duName "dna_gen"
     288elements [
     289]
     290mwi 0
     291uid 15728,0
     292)
    280293]
    281294libraryRefs [
    … …  
    333346(vvPair
    334347variable "date"
    335 value "08.02.2011"
     348value "15.02.2011"
    336349)
    337350(vvPair
    … …  
    345358(vvPair
    346359variable "dd"
    347 value "08"
     360value "15"
    348361)
    349362(vvPair
    … …  
    485498(vvPair
    486499variable "time"
    487 value "11:06:22"
     500value "09:27:14"
    488501)
    489502(vvPair
    … …  
    13631376preAdd 0
    13641377posAdd 0
    1365 o 24
     1378o 25
    13661379suid 9,0
    13671380)
    … …  
    13691382)
    13701383*29 (CptPort
    1371 uid 1388,0
    1372 ps "OnEdgeStrategy"
    1373 shape (Triangle
    1374 uid 1389,0
    1375 ro 90
    1376 va (VaSet
    1377 vasetType 1
    1378 fg "0,65535,0"
    1379 )
    1380 xt "-21750,69625,-21000,70375"
    1381 )
    1382 tg (CPTG
    1383 uid 1390,0
    1384 ps "CptPortTextPlaceStrategy"
    1385 stg "VerticalLayoutStrategy"
    1386 f (Text
    1387 uid 1391,0
    1388 va (VaSet
    1389 )
    1390 xt "-20000,69500,-13200,70500"
    1391 st "trigger_id : (47:0)"
    1392 blo "-20000,70300"
    1393 )
    1394 )
    1395 thePort (LogicalPort
    1396 decl (Decl
    1397 n "trigger_id"
    1398 t "std_logic_vector"
    1399 b "(47 downto 0)"
    1400 preAdd 0
    1401 posAdd 0
    1402 o 26
    1403 suid 10,0
    1404 )
    1405 )
    1406 )
    1407 *30 (CptPort
    14081384uid 1392,0
    14091385ps "OnEdgeStrategy"
    … …  
    14361412preAdd 0
    14371413posAdd 0
    1438 o 27
     1414o 28
    14391415suid 11,0
    14401416)
    14411417)
    14421418)
    1443 *31 (CptPort
     1419*30 (CptPort
    14441420uid 1676,0
    14451421ps "OnEdgeStrategy"
    … …  
    14711447t "std_logic_vector"
    14721448b "(1 downto 0)"
    1473 o 25
     1449o 26
    14741450suid 12,0
    14751451)
    14761452)
    14771453)
    1478 *32 (CptPort
     1454*31 (CptPort
    14791455uid 2562,0
    14801456ps "OnEdgeStrategy"
    … …  
    15111487)
    15121488)
    1513 *33 (CptPort
     1489*32 (CptPort
    15141490uid 2566,0
    15151491ps "OnEdgeStrategy"
    … …  
    15491525)
    15501526)
    1551 *34 (CptPort
     1527*33 (CptPort
    15521528uid 2570,0
    15531529ps "OnEdgeStrategy"
    … …  
    15841560)
    15851561)
    1586 *35 (CptPort
     1562*34 (CptPort
    15871563uid 2614,0
    15881564ps "OnEdgeStrategy"
    … …  
    16191595)
    16201596)
    1621 *36 (CptPort
     1597*35 (CptPort
    16221598uid 2624,0
    16231599ps "OnEdgeStrategy"
    … …  
    16551631)
    16561632)
    1657 *37 (CptPort
     1633*36 (CptPort
    16581634uid 2760,0
    16591635ps "OnEdgeStrategy"
    … …  
    16851661n "adc_oeb"
    16861662t "std_logic"
    1687 o 31
     1663o 32
    16881664suid 23,0
    16891665i "'1'"
    … …  
    16911667)
    16921668)
    1693 *38 (CptPort
     1669*37 (CptPort
    16941670uid 2764,0
    16951671ps "OnEdgeStrategy"
    … …  
    17211697t "std_logic_vector"
    17221698b "(3 downto 0)"
    1723 o 33
     1699o 34
    17241700suid 24,0
    17251701)
    17261702)
    17271703)
    1728 *39 (CptPort
     1704*38 (CptPort
    17291705uid 3918,0
    17301706ps "OnEdgeStrategy"
    … …  
    17581734b "(3 downto 0)"
    17591735posAdd 0
    1760 o 34
     1736o 35
    17611737suid 25,0
    17621738i "(others => '0')"
    … …  
    17641740)
    17651741)
    1766 *40 (CptPort
     1742*39 (CptPort
    17671743uid 3922,0
    17681744ps "OnEdgeStrategy"
    … …  
    17971773preAdd 0
    17981774posAdd 0
    1799 o 37
     1775o 38
    18001776suid 26,0
    18011777i "'0'"
    … …  
    18031779)
    18041780)
    1805 *41 (CptPort
     1781*40 (CptPort
    18061782uid 3930,0
    18071783ps "OnEdgeStrategy"
    … …  
    18351811prec "-- --"
    18361812preAdd 0
    1837 o 38
     1813o 39
    18381814suid 33,0
    18391815i "'0'"
    … …  
    18411817)
    18421818)
    1843 *42 (CptPort
     1819*41 (CptPort
    18441820uid 3934,0
    18451821ps "OnEdgeStrategy"
    … …  
    18701846n "drs_read_s_cell_ready"
    18711847t "std_logic"
    1872 o 43
     1848o 44
    18731849suid 34,0
    18741850)
    18751851)
    18761852)
    1877 *43 (CptPort
     1853*42 (CptPort
    18781854uid 3938,0
    18791855ps "OnEdgeStrategy"
    … …  
    19041880n "drs_s_cell_array"
    19051881t "drs_s_cell_array_type"
    1906 o 44
     1882o 45
    19071883suid 35,0
    19081884)
    19091885)
    19101886)
    1911 *44 (CptPort
     1887*43 (CptPort
    19121888uid 4246,0
    19131889ps "OnEdgeStrategy"
    … …  
    19381914n "adc_data_array"
    19391915t "adc_data_array_type"
    1940 o 30
     1916o 31
    19411917suid 37,0
    19421918)
    19431919)
    19441920)
    1945 *45 (CptPort
     1921*44 (CptPort
    19461922uid 5174,0
    19471923ps "OnEdgeStrategy"
    … …  
    19781954)
    19791955)
    1980 *46 (CptPort
     1956*45 (CptPort
    19811957uid 5178,0
    19821958ps "OnEdgeStrategy"
    … …  
    20181994)
    20191995)
    2020 *47 (CptPort
     1996*46 (CptPort
    20211997uid 5392,0
    20221998ps "OnEdgeStrategy"
    … …  
    20532029)
    20542030)
    2055 *48 (CptPort
     2031*47 (CptPort
    20562032uid 5396,0
    20572033ps "OnEdgeStrategy"
    … …  
    20882064)
    20892065)
    2090 *49 (CptPort
     2066*48 (CptPort
    20912067uid 5464,0
    20922068ps "OnEdgeStrategy"
    … …  
    21232099)
    21242100)
    2125 *50 (CptPort
     2101*49 (CptPort
    21262102uid 5468,0
    21272103ps "OnEdgeStrategy"
    … …  
    21582134)
    21592135)
    2160 *51 (CptPort
     2136*50 (CptPort
    21612137uid 5735,0
    21622138ps "OnEdgeStrategy"
    … …  
    21982174)
    21992175)
    2200 *52 (CptPort
     2176*51 (CptPort
    22012177uid 5739,0
    22022178ps "OnEdgeStrategy"
    … …  
    22372213)
    22382214)
    2239 *53 (CptPort
     2215*52 (CptPort
    22402216uid 5916,0
    22412217ps "OnEdgeStrategy"
    … …  
    22682244n "config_started"
    22692245t "std_logic"
    2270 o 29
     2246o 30
    22712247suid 48,0
    22722248i "'0'"
    … …  
    22742250)
    22752251)
    2276 *54 (CptPort
     2252*53 (CptPort
    22772253uid 5920,0
    22782254ps "OnEdgeStrategy"
    … …  
    23062282prec "--      s_trigger      : in std_logic;"
    23072283preAdd 0
    2308 o 28
     2284o 29
    23092285suid 49,0
    23102286)
    23112287)
    23122288)
    2313 *55 (CptPort
     2289*54 (CptPort
    23142290uid 5974,0
    23152291ps "OnEdgeStrategy"
    … …  
    23462322)
    23472323)
    2348 *56 (CptPort
     2324*55 (CptPort
    23492325uid 5978,0
    23502326ps "OnEdgeStrategy"
    … …  
    23812357)
    23822358)
    2383 *57 (CptPort
     2359*56 (CptPort
    23842360uid 5982,0
    23852361ps "OnEdgeStrategy"
    … …  
    24162392)
    24172393)
    2418 *58 (CptPort
     2394*57 (CptPort
    24192395uid 6060,0
    24202396ps "OnEdgeStrategy"
    … …  
    24512427)
    24522428)
    2453 *59 (CptPort
     2429*58 (CptPort
    24542430uid 9000,0
    24552431ps "OnEdgeStrategy"
    … …  
    24812457n "adc_clk_en"
    24822458t "std_logic"
    2483 o 32
     2459o 33
    24842460suid 54,0
    24852461i "'0'"
    … …  
    24872463)
    24882464)
    2489 *60 (CptPort
     2465*59 (CptPort
    24902466uid 10244,0
    24912467ps "OnEdgeStrategy"
    … …  
    25182494t "std_logic_vector"
    25192495b "(7 downto 0)"
    2520 o 41
     2496o 42
    25212497suid 56,0
    25222498i "(others => '0')"
    … …  
    25242500)
    25252501)
    2526 *61 (CptPort
     2502*60 (CptPort
    25272503uid 10248,0
    25282504ps "OnEdgeStrategy"
    … …  
    25542530n "drs_srin_write_8b"
    25552531t "std_logic"
    2556 o 39
     2532o 40
    25572533suid 57,0
    25582534i "'0'"
    … …  
    25602536)
    25612537)
    2562 *62 (CptPort
     2538*61 (CptPort
    25632539uid 10252,0
    25642540ps "OnEdgeStrategy"
    … …  
    25892565n "drs_srin_write_ack"
    25902566t "std_logic"
    2591 o 40
     2567o 41
    25922568suid 58,0
    25932569)
    25942570)
    25952571)
    2596 *63 (CptPort
     2572*62 (CptPort
    25972573uid 10256,0
    25982574ps "OnEdgeStrategy"
    … …  
    26232599n "drs_srin_write_ready"
    26242600t "std_logic"
    2625 o 42
     2601o 43
    26262602suid 59,0
    26272603)
    26282604)
    26292605)
    2630 *64 (CptPort
     2606*63 (CptPort
    26312607uid 10260,0
    26322608ps "OnEdgeStrategy"
    … …  
    26662642)
    26672643)
    2668 *65 (CptPort
     2644*64 (CptPort
    26692645uid 11385,0
    26702646ps "OnEdgeStrategy"
    … …  
    26972673n "drs_readout_started"
    26982674t "std_logic"
    2699 o 45
     2675o 46
    27002676suid 61,0
    27012677i "'0'"
    … …  
    27032679)
    27042680)
    2705 *66 (CptPort
     2681*65 (CptPort
    27062682uid 12597,0
    27072683ps "OnEdgeStrategy"
    … …  
    27372713preAdd 0
    27382714posAdd 0
    2739 o 35
     2715o 36
    27402716suid 62,0
    27412717i "'0'"
    … …  
    27432719)
    27442720)
    2745 *67 (CptPort
     2721*66 (CptPort
    27462722uid 12601,0
    27472723ps "OnEdgeStrategy"
    … …  
    27722748n "drs_readout_ready_ack"
    27732749t "std_logic"
    2774 o 36
     2750o 37
    27752751suid 63,0
     2752)
     2753)
     2754)
     2755*67 (CptPort
     2756uid 15740,0
     2757ps "OnEdgeStrategy"
     2758shape (Triangle
     2759uid 15741,0
     2760ro 90
     2761va (VaSet
     2762vasetType 1
     2763fg "0,65535,0"
     2764)
     2765xt "-21750,69625,-21000,70375"
     2766)
     2767tg (CPTG
     2768uid 15742,0
     2769ps "CptPortTextPlaceStrategy"
     2770stg "VerticalLayoutStrategy"
     2771f (Text
     2772uid 15743,0
     2773va (VaSet
     2774)
     2775xt "-20000,69500,-10200,70500"
     2776st "fad_event_counter : (31:0)"
     2777blo "-20000,70300"
     2778)
     2779)
     2780thePort (LogicalPort
     2781decl (Decl
     2782n "fad_event_counter"
     2783t "std_logic_vector"
     2784b "(31 downto 0)"
     2785o 27
     2786suid 65,0
     2787)
     2788)
     2789)
     2790*68 (CptPort
     2791uid 15744,0
     2792ps "OnEdgeStrategy"
     2793shape (Triangle
     2794uid 15745,0
     2795ro 90
     2796va (VaSet
     2797vasetType 1
     2798fg "0,65535,0"
     2799)
     2800xt "-21750,95625,-21000,96375"
     2801)
     2802tg (CPTG
     2803uid 15746,0
     2804ps "CptPortTextPlaceStrategy"
     2805stg "VerticalLayoutStrategy"
     2806f (Text
     2807uid 15747,0
     2808va (VaSet
     2809)
     2810xt "-20000,95500,-14500,96500"
     2811st "pll_lock : (3:0)"
     2812blo "-20000,96300"
     2813)
     2814)
     2815thePort (LogicalPort
     2816decl (Decl
     2817n "pll_lock"
     2818t "std_logic_vector"
     2819b "( 3 downto 0)"
     2820o 24
     2821suid 64,0
    27762822)
    27772823)
    … …  
    27942840stg "VerticalLayoutStrategy"
    27952841textVec [
    2796 *68 (Text
     2842*69 (Text
    27972843uid 1402,0
    27982844va (VaSet
    … …  
    28042850tm "BdLibraryNameMgr"
    28052851)
    2806 *69 (Text
     2852*70 (Text
    28072853uid 1403,0
    28082854va (VaSet
    … …  
    28142860tm "CptNameMgr"
    28152861)
    2816 *70 (Text
     2862*71 (Text
    28172863uid 1404,0
    28182864va (VaSet
    … …  
    28672913archFileType "UNKNOWN"
    28682914)
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     2915*72 (Net
    28702916uid 1409,0
    28712917decl (Decl
    … …  
    28862932)
    28872933)
    2888 *72 (Net
     2934*73 (Net
    28892935uid 1423,0
    28902936decl (Decl
    … …  
    29062952)
    29072953)
    2908 *73 (PortIoIn
     2954*74 (PortIoIn
    29092955uid 1443,0
    29102956shape (CompositeShape
    … …  
    29512997)
    29522998)
    2953 *74 (SaComponent
     2999*75 (SaComponent
    29543000uid 1606,0
    29553001optionalChildren [
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     3002*76 (CptPort
    29573003uid 1542,0
    29583004ps "OnEdgeStrategy"
    … …  
    29903036)
    29913037)
    2992 *76 (CptPort
     3038*77 (CptPort
    29933039uid 1546,0
    29943040ps "OnEdgeStrategy"
    … …  
    30293075)
    30303076)
    3031 *77 (CptPort
     3077*78 (CptPort
    30323078uid 1550,0
    30333079ps "OnEdgeStrategy"
    … …  
    30683114)
    30693115)
    3070 *78 (CptPort
     3116*79 (CptPort
    30713117uid 1554,0
    30723118ps "OnEdgeStrategy"
    … …  
    31073153)
    31083154)
    3109 *79 (CptPort
     3155*80 (CptPort
    31103156uid 1558,0
    31113157ps "OnEdgeStrategy"
    … …  
    31463192)
    31473193)
    3148 *80 (CptPort
     3194*81 (CptPort
    31493195uid 1562,0
    31503196ps "OnEdgeStrategy"
    … …  
    31853231)
    31863232)
    3187 *81 (CptPort
     3233*82 (CptPort
    31883234uid 1570,0
    31893235ps "OnEdgeStrategy"
    … …  
    32243270)
    32253271)
    3226 *82 (CptPort
     3272*83 (CptPort
    32273273uid 1574,0
    32283274ps "OnEdgeStrategy"
    … …  
    32613307)
    32623308)
    3263 *83 (CptPort
     3309*84 (CptPort
    32643310uid 1578,0
    32653311ps "OnEdgeStrategy"
    … …  
    32983344)
    32993345)
    3300 *84 (CptPort
     3346*85 (CptPort
    33013347uid 1582,0
    33023348ps "OnEdgeStrategy"
    … …  
    33353381)
    33363382)
    3337 *85 (CptPort
     3383*86 (CptPort
    33383384uid 1586,0
    33393385ps "OnEdgeStrategy"
    … …  
    33723418)
    33733419)
    3374 *86 (CptPort
     3420*87 (CptPort
    33753421uid 1590,0
    33763422ps "OnEdgeStrategy"
    … …  
    34103456)
    34113457)
    3412 *87 (CptPort
     3458*88 (CptPort
    34133459uid 1594,0
    34143460ps "OnEdgeStrategy"
    … …  
    34463492)
    34473493)
    3448 *88 (CptPort
     3494*89 (CptPort
    34493495uid 1598,0
    34503496ps "OnEdgeStrategy"
    … …  
    34843530)
    34853531)
    3486 *89 (CptPort
     3532*90 (CptPort
    34873533uid 2218,0
    34883534ps "OnEdgeStrategy"
    … …  
    35203566)
    35213567)
    3522 *90 (CptPort
     3568*91 (CptPort
    35233569uid 2222,0
    35243570ps "OnEdgeStrategy"
    … …  
    35543600)
    35553601)
    3556 *91 (CptPort
     3602*92 (CptPort
    35573603uid 2226,0
    35583604ps "OnEdgeStrategy"
    … …  
    35883634)
    35893635)
    3590 *92 (CptPort
     3636*93 (CptPort
    35913637uid 5216,0
    35923638ps "OnEdgeStrategy"
    … …  
    36273673)
    36283674)
    3629 *93 (CptPort
     3675*94 (CptPort
    36303676uid 5275,0
    36313677ps "OnEdgeStrategy"
    … …  
    36653711)
    36663712)
    3667 *94 (CptPort
     3713*95 (CptPort
    36683714uid 5924,0
    36693715ps "OnEdgeStrategy"
    … …  
    37013747)
    37023748)
    3703 *95 (CptPort
     3749*96 (CptPort
    37043750uid 5928,0
    37053751ps "OnEdgeStrategy"
    … …  
    37373783)
    37383784)
    3739 *96 (CptPort
     3785*97 (CptPort
    37403786uid 5932,0
    37413787ps "OnEdgeStrategy"
    … …  
    37743820)
    37753821)
    3776 *97 (CptPort
     3822*98 (CptPort
    37773823uid 5936,0
    37783824ps "OnEdgeStrategy"
    … …  
    38083854)
    38093855)
    3810 *98 (CptPort
     3856*99 (CptPort
    38113857uid 5940,0
    38123858ps "OnEdgeStrategy"
    … …  
    38443890)
    38453891)
    3846 *99 (CptPort
     3892*100 (CptPort
    38473893uid 5944,0
    38483894ps "OnEdgeStrategy"
    … …  
    38823928)
    38833929)
    3884 *100 (CptPort
     3930*101 (CptPort
    38853931uid 5970,0
    38863932ps "OnEdgeStrategy"
    … …  
    39193965)
    39203966)
    3921 *101 (CptPort
     3967*102 (CptPort
    39223968uid 6356,0
    39233969ps "OnEdgeStrategy"
    … …  
    39584004)
    39594005)
    3960 *102 (CptPort
     4006*103 (CptPort
    39614007uid 6446,0
    39624008ps "OnEdgeStrategy"
    … …  
    39984044)
    39994045)
    4000 *103 (CptPort
     4046*104 (CptPort
    40014047uid 8406,0
    40024048ps "OnEdgeStrategy"
    … …  
    40344080)
    40354081)
    4036 *104 (CptPort
     4082*105 (CptPort
    40374083uid 8748,0
    40384084ps "OnEdgeStrategy"
    … …  
    40734119)
    40744120)
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    40774123ps "OnEdgeStrategy"
    … …  
    41124158)
    41134159)
    4114 *106 (CptPort
     4160*107 (CptPort
    41154161uid 9227,0
    41164162ps "OnEdgeStrategy"
    … …  
    41524198)
    41534199)
    4154 *107 (CptPort
     4200*108 (CptPort
    41554201uid 9933,0
    41564202ps "OnEdgeStrategy"
    … …  
    41914237)
    41924238)
    4193 *108 (CptPort
     4239*109 (CptPort
    41944240uid 9937,0
    41954241ps "OnEdgeStrategy"
    … …  
    42304276)
    42314277)
    4232 *109 (CptPort
     4278*110 (CptPort
    42334279uid 10212,0
    42344280ps "OnEdgeStrategy"
    … …  
    42674313)
    42684314)
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     4315*111 (CptPort
    42704316uid 10216,0
    42714317ps "OnEdgeStrategy"
    … …  
    43044350)
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     4352*112 (CptPort
    43074353uid 10619,0
    43084354ps "OnEdgeStrategy"
    … …  
    43404386)
    43414387)
    4342 *112 (CptPort
     4388*113 (CptPort
    43434389uid 10623,0
    43444390ps "OnEdgeStrategy"
    … …  
    43774423)
    43784424)
    4379 *113 (CptPort
     4425*114 (CptPort
    43804426uid 11838,0
    43814427ps "OnEdgeStrategy"
    … …  
    44164462)
    44174463)
    4418 *114 (CptPort
     4464*115 (CptPort
    44194465uid 13149,0
    44204466ps "OnEdgeStrategy"
    … …  
    44524498)
    44534499)
    4454 *115 (CptPort
     4500*116 (CptPort
    44554501uid 13153,0
    44564502ps "OnEdgeStrategy"
    … …  
    44914537)
    44924538)
    4493 *116 (CptPort
     4539*117 (CptPort
    44944540uid 13806,0
    44954541ps "OnEdgeStrategy"
    … …  
    45264572)
    45274573)
    4528 *117 (CptPort
     4574*118 (CptPort
    45294575uid 13911,0
    45304576ps "OnEdgeStrategy"
    … …  
    45614607)
    45624608)
    4563 *118 (CptPort
     4609*119 (CptPort
    45644610uid 13915,0
    45654611ps "OnEdgeStrategy"
    … …  
    46134659stg "VerticalLayoutStrategy"
    46144660textVec [
    4615 *119 (Text
     4661*120 (Text
    46164662uid 1609,0
    46174663va (VaSet
    … …  
    46234669tm "BdLibraryNameMgr"
    46244670)
    4625 *120 (Text
     4671*121 (Text
    46264672uid 1610,0
    46274673va (VaSet
    … …  
    46334679tm "CptNameMgr"
    46344680)
    4635 *121 (Text
     4681*122 (Text
    46364682uid 1611,0
    46374683va (VaSet
    … …  
    46864732archFileType "UNKNOWN"
    46874733)
    4688 *122 (Net
     4734*123 (Net
    46894735uid 1680,0
    46904736decl (Decl
    … …  
    47054751)
    47064752)
    4707 *123 (SaComponent
     4753*124 (SaComponent
    47084754uid 1768,0
    47094755optionalChildren [
    4710 *124 (CptPort
     4756*125 (CptPort
    47114757uid 1760,0
    47124758ps "OnEdgeStrategy"
    … …  
    47294775)
    47304776xt "-48800,68500,-42000,69500"
    4731 st "trigger_id : (47:0)"
     4777st "trigger_id : (31:0)"
    47324778ju 2
    47334779blo "-42000,69300"
    … …  
    47404786n "trigger_id"
    47414787t "std_logic_vector"
    4742 b "(47 downto 0)"
     4788b "(31 downto 0)"
    47434789preAdd 0
    47444790posAdd 0
    … …  
    47484794)
    47494795)
    4750 *125 (CptPort
     4796*126 (CptPort
    47514797uid 1764,0
    47524798ps "OnEdgeStrategy"
    … …  
    47854831)
    47864832)
    4787 *126 (CptPort
     4833*127 (CptPort
    47884834uid 6207,0
    47894835ps "OnEdgeStrategy"
    … …  
    48374883stg "VerticalLayoutStrategy"
    48384884textVec [
    4839 *127 (Text
     4885*128 (Text
    48404886uid 1771,0
    48414887va (VaSet
    … …  
    48484894tm "BdLibraryNameMgr"
    48494895)
    4850 *128 (Text
     4896*129 (Text
    48514897uid 1772,0
    48524898va (VaSet
    … …  
    48594905tm "CptNameMgr"
    48604906)
    4861 *129 (Text
     4907*130 (Text
    48624908uid 1773,0
    48634909va (VaSet
    … …  
    49074953)
    49084954archFileType "UNKNOWN"
    4909 )
    4910 *130 (Net
    4911 uid 1981,0
    4912 lang 2
    4913 decl (Decl
    4914 n "trigger_id"
    4915 t "std_logic_vector"
    4916 b "(47 downto 0)"
    4917 preAdd 0
    4918 posAdd 0
    4919 o 119
    4920 suid 34,0
    4921 )
    4922 declText (MLText
    4923 uid 1982,0
    4924 va (VaSet
    4925 font "Courier New,8,0"
    4926 )
    4927 xt "-172000,98800,-139500,99600"
    4928 st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)
    4929 "
    4930 )
    49314955)
    49324956*131 (Net
    … …  
    1701117035)
    1701217036)
    17013 *599 (Wire
     17037*599 (SaComponent
     17038uid 15728,0
     17039optionalChildren [
     17040*600 (CptPort
     17041uid 15712,0
     17042ps "OnEdgeStrategy"
     17043shape (Triangle
     17044uid 15713,0
     17045ro 90
     17046va (VaSet
     17047vasetType 1
     17048fg "0,65535,0"
     17049)
     17050xt "-83750,113625,-83000,114375"
     17051)
     17052tg (CPTG
     17053uid 15714,0
     17054ps "CptPortTextPlaceStrategy"
     17055stg "VerticalLayoutStrategy"
     17056f (Text
     17057uid 15715,0
     17058va (VaSet
     17059)
     17060xt "-82000,113500,-80700,114500"
     17061st "clk"
     17062blo "-82000,114300"
     17063)
     17064)
     17065thePort (LogicalPort
     17066decl (Decl
     17067n "clk"
     17068t "STD_LOGIC"
     17069preAdd 0
     17070posAdd 0
     17071o 1
     17072suid 1,0
     17073)
     17074)
     17075)
     17076*601 (CptPort
     17077uid 15716,0
     17078ps "OnEdgeStrategy"
     17079shape (Triangle
     17080uid 15717,0
     17081ro 90
     17082va (VaSet
     17083vasetType 1
     17084fg "0,65535,0"
     17085)
     17086xt "-83750,115625,-83000,116375"
     17087)
     17088tg (CPTG
     17089uid 15718,0
     17090ps "CptPortTextPlaceStrategy"
     17091stg "VerticalLayoutStrategy"
     17092f (Text
     17093uid 15719,0
     17094va (VaSet
     17095)
     17096xt "-82000,115500,-80100,116500"
     17097st "start"
     17098blo "-82000,116300"
     17099)
     17100)
     17101thePort (LogicalPort
     17102decl (Decl
     17103n "start"
     17104t "STD_LOGIC"
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    23294 )
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    23297 ttg (MlTextGroup
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    23302 va (VaSet
    23303 font "Arial,8,1"
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    23310 va (VaSet
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    23312 )
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    23318 va (VaSet
    23319 font "Arial,8,1"
    23320 )
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    23323 blo "500,6300"
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    23325 )
    23326 ]
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    23328 ga (GenericAssociation
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    23332 va (VaSet
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    23339 elements [
    23340 ]
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    … …  
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     23472xt "550,3500,3450,4500"
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     23474blo "550,4300"
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    … …  
    2337223478font "Arial,8,1"
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     23480xt "550,4500,7450,5500"
     23481st "MWComponent"
     23482blo "550,5300"
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    … …  
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     23488xt "550,5500,2350,6500"
    2338323489st "U_0"
    23384 blo "50,6300"
     23490blo "550,6300"
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    … …  
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    … …  
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     26750)
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     26768)
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    2647026774)
    2647126775]
    … …  
    2648026784uid 73,0
    2648126785optionalChildren [
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    26524 *1062 (MRCItem
    26525 litem &803
     26828*1071 (MRCItem
     26829litem &812
    2652626830pos 7
    2652726831dimension 290
    … …  
    2654326847genericsCommonDM (CommonDM
    2654426848ldm (LogicalDM
    26545 emptyRow *1063 (LEmptyRow
     26849emptyRow *1072 (LEmptyRow
    2654626850)
    2654726851uid 83,0
    2654826852optionalChildren [
    26549 *1064 (RefLabelRowHdr
    26550 )
    26551 *1065 (TitleRowHdr
    26552 )
    26553 *1066 (FilterRowHdr
    26554 )
    26555 *1067 (RefLabelColHdr
     26853*1073 (RefLabelRowHdr
     26854)
     26855*1074 (TitleRowHdr
     26856)
     26857*1075 (FilterRowHdr
     26858)
     26859*1076 (RefLabelColHdr
    2655626860tm "RefLabelColHdrMgr"
    2655726861)
    26558 *1068 (RowExpandColHdr
     26862*1077 (RowExpandColHdr
    2655926863tm "RowExpandColHdrMgr"
    2656026864)
    26561 *1069 (GroupColHdr
     26865*1078 (GroupColHdr
    2656226866tm "GroupColHdrMgr"
    2656326867)
    26564 *1070 (NameColHdr
     26868*1079 (NameColHdr
    2656526869tm "GenericNameColHdrMgr"
    2656626870)
    26567 *1071 (TypeColHdr
     26871*1080 (TypeColHdr
    2656826872tm "GenericTypeColHdrMgr"
    2656926873)
    26570 *1072 (InitColHdr
     26874*1081 (InitColHdr
    2657126875tm "GenericValueColHdrMgr"
    2657226876)
    26573 *1073 (PragmaColHdr
     26877*1082 (PragmaColHdr
    2657426878tm "GenericPragmaColHdrMgr"
    2657526879)
    26576 *1074 (EolColHdr
     26880*1083 (EolColHdr
    2657726881tm "GenericEolColHdrMgr"
    2657826882)
    26579 *1075 (LogGeneric
     26883*1084 (LogGeneric
    2658026884generic (GiElement
    2658126885name "RAMADDRWIDTH64b"
    … …  
    2659226896uid 95,0
    2659326897optionalChildren [
    26594 *1076 (Sheet
     26898*1085 (Sheet
    2659526899sheetRow (SheetRow
    2659626900headerVa (MVa
    … …  
    2660926913font "Tahoma,10,0"
    2661026914)
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    … …  
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  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak

    r10138 r10155  
    333333(vvPair
    334334variable "date"
    335 value "08.02.2011"
     335value "14.02.2011"
    336336)
    337337(vvPair
    338338variable "day"
    339 value "Di"
     339value "Mo"
    340340)
    341341(vvPair
    342342variable "day_long"
    343 value "Dienstag"
     343value "Montag"
    344344)
    345345(vvPair
    346346variable "dd"
    347 value "08"
     347value "14"
    348348)
    349349(vvPair
    … …  
    485485(vvPair
    486486variable "time"
    487 value "11:05:26"
     487value "17:05:04"
    488488)
    489489(vvPair
    … …  
    576576font "Courier New,8,0"
    577577)
    578 xt "-172000,106000,-128500,106800"
    579 st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\"
    580 "
     578xt "-172000,106800,-128500,107600"
     579st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\""
    581580)
    582581)
    … …  
    596595)
    597596xt "-172000,42800,-132000,43600"
    598 st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
    599 "
     597st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
    600598)
    601599)
    … …  
    615613)
    616614xt "-172000,62000,-139500,62800"
    617 st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)
    618 "
     615st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)"
    619616)
    620617)
    … …  
    634631)
    635632xt "-172000,80400,-132000,81200"
    636 st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)
    637 "
     633st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)"
    638634)
    639635)
    … …  
    653649)
    654650xt "-172000,81200,-139500,82000"
    655 st "SIGNAL ram_data               : std_logic_vector(15 downto 0)
    656 "
     651st "SIGNAL ram_data               : std_logic_vector(15 downto 0)"
    657652)
    658653)
    … …  
    672667)
    673668xt "-172000,34400,-132000,35200"
    674 st "wiz_reset              : std_logic                                    := '1'
    675 "
     669st "wiz_reset              : std_logic                                    := '1'"
    676670)
    677671)
    … …  
    691685)
    692686xt "-172000,32000,-143500,32800"
    693 st "wiz_addr               : std_logic_vector(9 DOWNTO 0)
    694 "
     687st "wiz_addr               : std_logic_vector(9 DOWNTO 0)"
    695688)
    696689)
    … …  
    710703)
    711704xt "-172000,36800,-143000,37600"
    712 st "wiz_data               : std_logic_vector(15 DOWNTO 0)
    713 "
     705st "wiz_data               : std_logic_vector(15 DOWNTO 0)"
    714706)
    715707)
    … …  
    729721)
    730722xt "-172000,32800,-132000,33600"
    731 st "wiz_cs                 : std_logic                                    := '1'
    732 "
     723st "wiz_cs                 : std_logic                                    := '1'"
    733724)
    734725)
    … …  
    748739)
    749740xt "-172000,35200,-132000,36000"
    750 st "wiz_wr                 : std_logic                                    := '1'
    751 "
     741st "wiz_wr                 : std_logic                                    := '1'"
    752742)
    753743)
    … …  
    767757)
    768758xt "-172000,33600,-132000,34400"
    769 st "wiz_rd                 : std_logic                                    := '1'
    770 "
     759st "wiz_rd                 : std_logic                                    := '1'"
    771760)
    772761)
    … …  
    785774)
    786775xt "-172000,13600,-153500,14400"
    787 st "wiz_int                : std_logic
    788 "
     776st "wiz_int                : std_logic"
    789777)
    790778)
    … …  
    28822870)
    28832871xt "-172000,9600,-143500,10400"
    2884 st "board_id               : std_logic_vector(3 DOWNTO 0)
    2885 "
     2872st "board_id               : std_logic_vector(3 DOWNTO 0)"
    28862873)
    28872874)
    … …  
    29022889)
    29032890xt "-172000,12800,-153500,13600"
    2904 st "trigger                : std_logic
    2905 "
     2891st "trigger                : std_logic"
    29062892)
    29072893)
    … …  
    47014687)
    47024688xt "-172000,10400,-143500,11200"
    4703 st "crate_id               : std_logic_vector(1 DOWNTO 0)
    4704 "
     4689st "crate_id               : std_logic_vector(1 DOWNTO 0)"
    47054690)
    47064691)
    … …  
    49264911)
    49274912xt "-172000,98800,-139500,99600"
    4928 st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)
    4929 "
     4913st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)"
    49304914)
    49314915)
    … …  
    49474931)
    49484932xt "-172000,82000,-132000,82800"
    4949 st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
    4950 "
     4933st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
    49514934)
    49524935)
    … …  
    57995782font "Courier New,8,0"
    58005783)
    5801 xt "-172000,100400,-149500,101200"
    5802 st "SIGNAL wiz_busy               : std_logic
    5803 "
     5784xt "-172000,101200,-149500,102000"
     5785st "SIGNAL wiz_busy               : std_logic"
    58045786)
    58055787)
    … …  
    58195801font "Courier New,8,0"
    58205802)
    5821 xt "-172000,102800,-128500,103600"
    5822 st "SIGNAL wiz_write_ea           : std_logic                                    := '0'
    5823 "
     5803xt "-172000,103600,-128500,104400"
     5804st "SIGNAL wiz_write_ea           : std_logic                                    := '0'"
    58245805)
    58255806)
    … …  
    58405821font "Courier New,8,0"
    58415822)
    5842 xt "-172000,105200,-122500,106000"
    5843 st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')
    5844 "
     5823xt "-172000,106000,-122500,106800"
     5824st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')"
    58455825)
    58465826)
    … …  
    58625842font "Courier New,8,0"
    58635843)
    5864 xt "-172000,102000,-122500,102800"
    5865 st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')
    5866 "
     5844xt "-172000,102800,-122500,103600"
     5845st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')"
    58675846)
    58685847)
    … …  
    58835862font "Courier New,8,0"
    58845863)
    5885 xt "-172000,101200,-122500,102000"
    5886 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')
    5887 "
     5864xt "-172000,102000,-122500,102800"
     5865st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')"
    58885866)
    58895867)
    … …  
    59035881font "Courier New,8,0"
    59045882)
    5905 xt "-172000,103600,-128500,104400"
    5906 st "SIGNAL wiz_write_end          : std_logic                                    := '0'
    5907 "
     5883xt "-172000,104400,-128500,105200"
     5884st "SIGNAL wiz_write_end          : std_logic                                    := '0'"
    59085885)
    59095886)
    … …  
    59235900font "Courier New,8,0"
    59245901)
    5925 xt "-172000,104400,-128500,105200"
    5926 st "SIGNAL wiz_write_header       : std_logic                                    := '0'
    5927 "
     5902xt "-172000,105200,-128500,106000"
     5903st "SIGNAL wiz_write_header       : std_logic                                    := '0'"
    59285904)
    59295905)
    … …  
    59425918)
    59435919xt "-172000,82800,-149500,83600"
    5944 st "SIGNAL ram_write_ea           : std_logic
    5945 "
     5920st "SIGNAL ram_write_ea           : std_logic"
    59465921)
    59475922)
    … …  
    59615936)
    59625937xt "-172000,83600,-128500,84400"
    5963 st "SIGNAL ram_write_ready        : std_logic                                    := '0'
    5964 "
     5938st "SIGNAL ram_write_ready        : std_logic                                    := '0'"
    59655939)
    59665940)
    … …  
    59805954)
    59815955xt "-172000,54800,-128500,55600"
    5982 st "SIGNAL config_start           : std_logic                                    := '0'
    5983 "
     5956st "SIGNAL config_start           : std_logic                                    := '0'"
    59845957)
    59855958)
    … …  
    59985971)
    59995972xt "-172000,49200,-149500,50000"
    6000 st "SIGNAL config_ready           : std_logic
    6001 "
     5973st "SIGNAL config_ready           : std_logic"
    60025974)
    60035975)
    … …  
    60165988)
    60175989xt "-172000,86800,-148000,87600"
    6018 st "SIGNAL roi_max                : roi_max_type
    6019 "
     5990st "SIGNAL roi_max                : roi_max_type"
    60205991)
    60215992)
    … …  
    60356006)
    60366007xt "-172000,77200,-139500,78000"
    6037 st "SIGNAL package_length         : std_logic_vector(15 downto 0)
    6038 "
     6008st "SIGNAL package_length         : std_logic_vector(15 downto 0)"
    60396009)
    60406010)
    … …  
    60546024)
    60556025xt "-172000,19200,-132000,20000"
    6056 st "adc_oeb                : std_logic                                    := '1'
    6057 "
     6026st "adc_oeb                : std_logic                                    := '1'"
    60586027)
    60596028)
    … …  
    61626131)
    61636132xt "-172000,86000,-147000,86800"
    6164 st "SIGNAL roi_array              : roi_array_type
    6165 "
     6133st "SIGNAL roi_array              : roi_array_type"
    61666134)
    61676135)
    … …  
    65966564)
    65976565xt "-172000,14400,-153500,15200"
    6598 st "CLK_25_PS              : std_logic
    6599 "
     6566st "CLK_25_PS              : std_logic"
    66006567)
    66016568)
    … …  
    66596626)
    66606627xt "-172000,15200,-153500,16000"
    6661 st "CLK_50                 : std_logic
    6662 "
     6628st "CLK_50                 : std_logic"
    66636629)
    66646630)
    … …  
    66776643)
    66786644xt "-172000,39600,-149500,40400"
    6679 st "SIGNAL CLK_25                 : std_logic
    6680 "
     6645st "SIGNAL CLK_25                 : std_logic"
    66816646)
    66826647)
    … …  
    67406705)
    67416706xt "-172000,3200,-153500,4000"
    6742 st "CLK                    : std_logic
    6743 "
     6707st "CLK                    : std_logic"
    67446708)
    67456709)
    … …  
    67596723)
    67606724xt "-172000,8800,-143500,9600"
    6761 st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)
    6762 "
     6725st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)"
    67636726)
    67646727)
    … …  
    67776740)
    67786741xt "-172000,8000,-148000,8800"
    6779 st "adc_data_array         : adc_data_array_type
    6780 "
     6742st "adc_data_array         : adc_data_array_type"
    67816743)
    67826744)
    … …  
    68416803)
    68426804xt "-172000,66800,-128500,67600"
    6843 st "SIGNAL drs_clk_en             : std_logic                                    := '0'
    6844 "
     6805st "SIGNAL drs_clk_en             : std_logic                                    := '0'"
    68456806)
    68466807)
    … …  
    68596820)
    68606821xt "-172000,73200,-143500,74000"
    6861 st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type
    6862 "
     6822st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type"
    68636823)
    68646824)
    … …  
    68786838)
    68796839xt "-172000,67600,-128500,68400"
    6880 st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'
    6881 "
     6840st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'"
    68826841)
    68836842)
    … …  
    68986857)
    68996858xt "-172000,25600,-126000,26400"
    6900 st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')
    6901 "
     6859st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')"
    69026860)
    69036861)
    … …  
    69176875)
    69186876xt "-172000,26400,-132000,27200"
    6919 st "drs_dwrite             : std_logic                                    := '1'
    6920 "
     6877st "drs_dwrite             : std_logic                                    := '1'"
    69216878)
    69226879)
    … …  
    70256982)
    70266983xt "-172000,4800,-153500,5600"
    7027 st "SROUT_in_0             : std_logic
    7028 "
     6984st "SROUT_in_0             : std_logic"
    70296985)
    70306986)
    … …  
    70436999)
    70447000xt "-172000,5600,-153500,6400"
    7045 st "SROUT_in_1             : std_logic
    7046 "
     7001st "SROUT_in_1             : std_logic"
    70477002)
    70487003)
    … …  
    70617016)
    70627017xt "-172000,6400,-153500,7200"
    7063 st "SROUT_in_2             : std_logic
    7064 "
     7018st "SROUT_in_2             : std_logic"
    70657019)
    70667020)
    … …  
    70797033)
    70807034xt "-172000,7200,-153500,8000"
    7081 st "SROUT_in_3             : std_logic
    7082 "
     7035st "SROUT_in_3             : std_logic"
    70837036)
    70847037)
    … …  
    72777230)
    72787231xt "-172000,68400,-149500,69200"
    7279 st "SIGNAL drs_read_s_cell_ready  : std_logic
    7280 "
     7232st "SIGNAL drs_read_s_cell_ready  : std_logic"
    72817233)
    72827234)
    … …  
    79337885)
    79347886xt "-172000,16000,-132000,16800"
    7935 st "RSRLOAD                : std_logic                                    := '0'
    7936 "
     7887st "RSRLOAD                : std_logic                                    := '0'"
    79377888)
    79387889)
    … …  
    79977948)
    79987949xt "-172000,16800,-132000,17600"
    7999 st "SRCLK                  : std_logic                                    := '0'
    8000 "
     7950st "SRCLK                  : std_logic                                    := '0'"
    80017951)
    80027952)
    … …  
    86518601)
    86528602xt "-172000,45200,-140000,46000"
    8653 st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)
    8654 "
     8603st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)"
    86558604)
    86568605)
    … …  
    86698618)
    86708619xt "-172000,47600,-149500,48400"
    8671 st "SIGNAL config_data_valid      : std_logic
    8672 "
     8620st "SIGNAL config_data_valid      : std_logic"
    86738621)
    86748622)
    … …  
    86878635)
    86888636xt "-172000,46000,-149500,46800"
    8689 st "SIGNAL config_busy            : std_logic
    8690 "
     8637st "SIGNAL config_busy            : std_logic"
    86918638)
    86928639)
    … …  
    87068653)
    87078654xt "-172000,46800,-139500,47600"
    8708 st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)
    8709 "
     8655st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)"
    87108656)
    87118657)
    … …  
    87248670)
    87258671xt "-172000,60400,-149500,61200"
    8726 st "SIGNAL config_wr_en           : std_logic
    8727 "
     8672st "SIGNAL config_wr_en           : std_logic"
    87288673)
    87298674)
    … …  
    87428687)
    87438688xt "-172000,48400,-149500,49200"
    8744 st "SIGNAL config_rd_en           : std_logic
    8745 "
     8689st "SIGNAL config_rd_en           : std_logic"
    87468690)
    87478691)
    … …  
    87608704)
    87618705xt "-172000,61200,-147000,62000"
    8762 st "SIGNAL dac_array              : dac_array_type
    8763 "
     8706st "SIGNAL dac_array              : dac_array_type"
    87648707)
    87658708)
    … …  
    87788721)
    87798722xt "-172000,55600,-149500,56400"
    8780 st "SIGNAL config_start_cm        : std_logic
    8781 "
     8723st "SIGNAL config_start_cm        : std_logic"
    87828724)
    87838725)
    … …  
    87968738)
    87978739xt "-172000,50000,-149500,50800"
    8798 st "SIGNAL config_ready_cm        : std_logic
    8799 "
     8740st "SIGNAL config_ready_cm        : std_logic"
    88008741)
    88018742)
    … …  
    88178758)
    88188759xt "-172000,28000,-126000,28800"
    8819 st "led                    : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')
    8820 "
     8760st "led                    : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')"
    88218761)
    88228762)
    … …  
    88358775)
    88368776xt "-172000,91600,-149500,92400"
    8837 st "SIGNAL sensor_ready           : std_logic
    8838 "
     8777st "SIGNAL sensor_ready           : std_logic"
    88398778)
    88408779)
    … …  
    88538792)
    88548793xt "-172000,90800,-145500,91600"
    8855 st "SIGNAL sensor_array           : sensor_array_type
    8856 "
     8794st "SIGNAL sensor_array           : sensor_array_type"
    88578795)
    88588796)
    … …  
    88718809)
    88728810xt "-172000,50800,-149500,51600"
    8873 st "SIGNAL config_ready_spi       : std_logic
    8874 "
     8811st "SIGNAL config_ready_spi       : std_logic"
    88758812)
    88768813)
    … …  
    88918828)
    88928829xt "-172000,42000,-140000,42800"
    8893 st "SIGNAL adc_otr                : std_logic_vector(3 DOWNTO 0)
    8894 "
     8830st "SIGNAL adc_otr                : std_logic_vector(3 DOWNTO 0)"
    88958831)
    88968832)
    … …  
    89098845)
    89108846xt "-172000,41200,-144500,42000"
    8911 st "SIGNAL adc_data_array_int     : adc_data_array_type
    8912 "
     8847st "SIGNAL adc_data_array_int     : adc_data_array_type"
    89138848)
    89148849)
    … …  
    92009135)
    92019136xt "-172000,56400,-128500,57200"
    9202 st "SIGNAL config_start_spi       : std_logic                                    := '0'
    9203 "
     9137st "SIGNAL config_start_spi       : std_logic                                    := '0'"
    92049138)
    92059139)
    … …  
    97349668)
    97359669xt "-172000,30400,-153500,31200"
    9736 st "sclk                   : std_logic
    9737 "
     9670st "sclk                   : std_logic"
    97389671)
    97399672)
    … …  
    97549687)
    97559688xt "-172000,36000,-153500,36800"
    9756 st "sio                    : std_logic
    9757 "
     9689st "sio                    : std_logic"
    97589690)
    97599691)
    … …  
    97729704)
    97739705xt "-172000,24000,-153500,24800"
    9774 st "dac_cs                 : std_logic
    9775 "
     9706st "dac_cs                 : std_logic"
    97769707)
    97779708)
    … …  
    97919722)
    97929723xt "-172000,31200,-143500,32000"
    9793 st "sensor_cs              : std_logic_vector(3 DOWNTO 0)
    9794 "
     9724st "sensor_cs              : std_logic_vector(3 DOWNTO 0)"
    97959725)
    97969726)
    … …  
    99909920)
    99919921xt "-172000,76400,-128500,77200"
    9992 st "SIGNAL new_config             : std_logic                                    := '0'
    9993 "
     9922st "SIGNAL new_config             : std_logic                                    := '0'"
    99949923)
    99959924)
    … …  
    100089937)
    100099938xt "-172000,57200,-149500,58000"
    10010 st "SIGNAL config_started         : std_logic
    10011 "
     9939st "SIGNAL config_started         : std_logic"
    100129940)
    100139941)
    … …  
    100279955)
    100289956xt "-172000,59600,-128500,60400"
    10029 st "SIGNAL config_started_spi     : std_logic                                    := '0'
    10030 "
     9957st "SIGNAL config_started_spi     : std_logic                                    := '0'"
    100319958)
    100329959)
    … …  
    100469973)
    100479974xt "-172000,58000,-128500,58800"
    10048 st "SIGNAL config_started_cu      : std_logic                                    := '0'
    10049 "
     9975st "SIGNAL config_started_cu      : std_logic                                    := '0'"
    100509976)
    100519977)
    … …  
    100649990)
    100659991xt "-172000,58800,-149500,59600"
    10066 st "SIGNAL config_started_mm      : std_logic
    10067 "
     9992st "SIGNAL config_started_mm      : std_logic"
    100689993)
    100699994)
    … …  
    1008310008)
    1008410009xt "-172000,28800,-132000,29600"
    10085 st "mosi                   : std_logic                                    := '0'
    10086 "
     10010st "mosi                   : std_logic                                    := '0'"
    1008710011)
    1008810012)
    … …  
    1014910073)
    1015010074xt "-172000,24800,-118500,25600"
    10151 st "denable                : std_logic                                    := '0' -- default domino wave off
    10152 "
     10075st "denable                : std_logic                                    := '0' -- default domino wave off"
    1015310076)
    1015410077)
    … …  
    1021210135)
    1021310136xt "-172000,75600,-128500,76400"
    10214 st "SIGNAL dwrite_enable          : std_logic                                    := '1'
    10215 "
     10137st "SIGNAL dwrite_enable          : std_logic                                    := '1'"
    1021610138)
    1021710139)
    … …  
    1060010522)
    1060110523xt "-172000,74800,-128500,75600"
    10602 st "SIGNAL dwrite                 : std_logic                                    := '1'
    10603 "
     10524st "SIGNAL dwrite                 : std_logic                                    := '1'"
    1060410525)
    1060510526)
    … …  
    1097410895font "Courier New,8,0"
    1097510896)
    10976 xt "-172000,99600,-149500,100400"
    10977 st "SIGNAL wiz_ack                : std_logic
    10978 "
     10897xt "-172000,100400,-149500,101200"
     10898st "SIGNAL wiz_ack                : std_logic"
    1097910899)
    1098010900)
    … …  
    1135911279)
    1136011280xt "-172000,89200,-149500,90000"
    11361 st "SIGNAL sclk1                  : std_logic
    11362 "
     11281st "SIGNAL sclk1                  : std_logic"
    1136311282)
    1136411283)
    … …  
    1137711296)
    1137811297xt "-172000,90000,-149500,90800"
    11379 st "SIGNAL sclk_enable            : std_logic
    11380 "
     11298st "SIGNAL sclk_enable            : std_logic"
    1138111299)
    1138211300)
    … …  
    1139611314)
    1139711315xt "-172000,18400,-132000,19200"
    11398 st "adc_clk_en             : std_logic                                    := '0'
    11399 "
     11316st "adc_clk_en             : std_logic                                    := '0'"
    1140011317)
    1140111318)
    … …  
    1185111768)
    1185211769xt "-172000,78000,-113000,78800"
    11853 st "SIGNAL ps_direction           : std_logic                                    := '1' -- default phase shift upwards
    11854 "
     11770st "SIGNAL ps_direction           : std_logic                                    := '1' -- default phase shift upwards"
    1185511771)
    1185611772)
    … …  
    1187311789)
    1187411790xt "-172000,78800,-112000,79600"
    11875 st "SIGNAL ps_do_phase_shift      : std_logic                                    := '0' --pulse this to phase shift once
    11876 "
     11791st "SIGNAL ps_do_phase_shift      : std_logic                                    := '0' --pulse this to phase shift once"
    1187711792)
    1187811793)
    … …  
    1189411809)
    1189511810xt "-172000,79600,-104500,80400"
    11896 st "SIGNAL ps_reset               : std_logic                                    := '0' -- pulse this to reset the variable phase shift
    11897 "
     11811st "SIGNAL ps_reset               : std_logic                                    := '0' -- pulse this to reset the variable phase shift"
    1189811812)
    1189911813)
    … …  
    1191311827)
    1191411828xt "-172000,94000,-128500,94800"
    11915 st "SIGNAL srclk_enable           : std_logic                                    := '0'
    11916 "
     11829st "SIGNAL srclk_enable           : std_logic                                    := '0'"
    1191711830)
    1191811831)
    … …  
    1229812211)
    1229912212xt "-172000,40400,-128500,41200"
    12300 st "SIGNAL SRCLK1                 : std_logic                                    := '0'
    12301 "
     12213st "SIGNAL SRCLK1                 : std_logic                                    := '0'"
    1230212214)
    1230312215)
    … …  
    1232112233xt "-172000,51600,-128500,53200"
    1232212234st "-- --
    12323 SIGNAL config_rw_ack          : std_logic                                    := '0'
    12324 "
     12235SIGNAL config_rw_ack          : std_logic                                    := '0'"
    1232512236)
    1232612237)
    … …  
    1234412255xt "-172000,53200,-128500,54800"
    1234512256st "-- --
    12346 SIGNAL config_rw_ready        : std_logic                                    := '0'
    12347 "
     12257SIGNAL config_rw_ready        : std_logic                                    := '0'"
    1234812258)
    1234912259)
    … …  
    1236212272)
    1236312273xt "-172000,87600,-149500,88400"
    12364 st "SIGNAL s_trigger              : std_logic
    12365 "
     12274st "SIGNAL s_trigger              : std_logic"
    1236612275)
    1236712276)
    … …  
    1238012289)
    1238112290xt "-172000,96400,-149500,97200"
    12382 st "SIGNAL start_srin_write_8b    : std_logic
    12383 "
     12291st "SIGNAL start_srin_write_8b    : std_logic"
    1238412292)
    1238512293)
    … …  
    1239912307)
    1240012308xt "-172000,94800,-128500,95600"
    12401 st "SIGNAL srin_write_ack         : std_logic                                    := '0'
    12402 "
     12309st "SIGNAL srin_write_ack         : std_logic                                    := '0'"
    1240312310)
    1240412311)
    … …  
    1241812325)
    1241912326xt "-172000,95600,-128500,96400"
    12420 st "SIGNAL srin_write_ready       : std_logic                                    := '0'
    12421 "
     12327st "SIGNAL srin_write_ready       : std_logic                                    := '0'"
    1242212328)
    1242312329)
    … …  
    1243812344)
    1243912345xt "-172000,74000,-122500,74800"
    12440 st "SIGNAL drs_srin_data          : std_logic_vector(7 downto 0)                 := (others => '0')
    12441 "
     12346st "SIGNAL drs_srin_data          : std_logic_vector(7 downto 0)                 := (others => '0')"
    1244212347)
    1244312348)
    … …  
    1245712362)
    1245812363xt "-172000,17600,-132000,18400"
    12459 st "SRIN_out               : std_logic                                    := '0'
    12460 "
     12364st "SRIN_out               : std_logic                                    := '0'"
    1246112365)
    1246212366)
    … …  
    1298012884xt "-172000,84400,-128500,86000"
    1298112885st "-- --
    12982 SIGNAL ram_write_ready_ack    : std_logic                                    := '0'
    12983 "
     12886SIGNAL ram_write_ready_ack    : std_logic                                    := '0'"
    1298412887)
    1298512888)
    … …  
    1299812901)
    1299912902xt "-172000,92400,-149500,93200"
    13000 st "SIGNAL socks_connected        : std_logic
    13001 "
     12903st "SIGNAL socks_connected        : std_logic"
    1300212904)
    1300312905)
    … …  
    1301612918)
    1301712919xt "-172000,93200,-149500,94000"
    13018 st "SIGNAL socks_waiting          : std_logic
    13019 "
     12920st "SIGNAL socks_waiting          : std_logic"
    1302012921)
    1302112922)
    … …  
    1303412935)
    1303512936xt "-172000,27200,-153500,28000"
    13036 st "green                  : std_logic
    13037 "
     12937st "green                  : std_logic"
    1303812938)
    1303912939)
    … …  
    1309612996)
    1309712997xt "-172000,22400,-153500,23200"
    13098 st "amber                  : std_logic
    13099 "
     12998st "amber                  : std_logic"
    1310012999)
    1310113000)
    … …  
    1315813057)
    1315913058xt "-172000,29600,-153500,30400"
    13160 st "red                    : std_logic
    13161 "
     13059st "red                    : std_logic"
    1316213060)
    1316313061)
    … …  
    1359913497)
    1360013498xt "-172000,72400,-149500,73200"
    13601 st "SIGNAL drs_readout_started    : std_logic
    13602 "
     13499st "SIGNAL drs_readout_started    : std_logic"
    1360313500)
    1360413501)
    … …  
    1361713514)
    1361813515xt "-172000,98000,-149500,98800"
    13619 st "SIGNAL trigger_enable         : std_logic
    13620 "
     13516st "SIGNAL trigger_enable         : std_logic"
    1362113517)
    1362213518)
    … …  
    1400613902)
    1400713903xt "-172000,65200,-149500,66000"
    14008 st "SIGNAL dout                   : std_logic
    14009 "
     13904st "SIGNAL dout                   : std_logic"
    1401013905)
    1401113906)
    … …  
    1432014215)
    1432114216xt "-172000,66000,-149500,66800"
    14322 st "SIGNAL dout1                  : std_logic
    14323 "
     14217st "SIGNAL dout1                  : std_logic"
    1432414218)
    1432514219)
    … …  
    1434514239st "-- --
    1434614240--      drs_dwrite : out std_logic := '1';
    14347 SIGNAL drs_readout_ready      : std_logic                                    := '0'
    14348 "
     14241SIGNAL drs_readout_ready      : std_logic                                    := '0'"
    1434914242)
    1435014243)
    … …  
    1436314256)
    1436414257xt "-172000,71600,-149500,72400"
    14365 st "SIGNAL drs_readout_ready_ack  : std_logic
    14366 "
     14258st "SIGNAL drs_readout_ready_ack  : std_logic"
    1436714259)
    1436814260)
    … …  
    1438114273)
    1438214274xt "-172000,20000,-153500,20800"
    14383 st "additional_flasher_out : std_logic
    14384 "
     14275st "additional_flasher_out : std_logic"
    1438514276)
    1438614277)
    … …  
    1467414565)
    1467514566xt "-172000,43600,-128500,44400"
    14676 st "SIGNAL c_trigger_enable       : std_logic                                    := '0'
    14677 "
     14567st "SIGNAL c_trigger_enable       : std_logic                                    := '0'"
    1467814568)
    1467914569)
    … …  
    1469614586)
    1469714587xt "-172000,44400,-112000,45200"
    14698 st "SIGNAL c_trigger_mult         : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '1') --subject to changes
    14699 "
     14588st "SIGNAL c_trigger_mult         : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '1') --subject to changes"
    1470014589)
    1470114590)
    … …  
    1471414603)
    1471514604xt "-172000,88400,-149500,89200"
    14716 st "SIGNAL s_trigger_0            : std_logic
    14717 "
     14605st "SIGNAL s_trigger_0            : std_logic"
    1471814606)
    1471914607)
    … …  
    1473214620)
    1473314621xt "-172000,97200,-149500,98000"
    14734 st "SIGNAL trigger1               : std_logic
    14735 "
     14622st "SIGNAL trigger1               : std_logic"
    1473614623)
    1473714624)
    … …  
    1524715134)
    1524815135xt "-172000,4000,-143500,4800"
    15249 st "D_T_in                 : std_logic_vector(1 DOWNTO 0)
    15250 "
     15136st "D_T_in                 : std_logic_vector(1 DOWNTO 0)"
    1525115137)
    1525215138)
    … …  
    1531115197)
    1531215198xt "-172000,11200,-121500,12000"
    15313 st "drs_refclk_in          : std_logic -- used to check if DRS REFCLK exsists, if not DENABLE inhibit
    15314 "
     15199st "drs_refclk_in          : std_logic -- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
    1531515200)
    1531615201)
    … …  
    1537615261)
    1537715262xt "-172000,12000,-114000,12800"
    15378 st "plllock_in             : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked
    15379 "
     15263st "plllock_in             : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked"
    1538015264)
    1538115265)
    … …  
    1566015544)
    1566115545xt "-172000,20800,-118500,21600"
    15662 st "alarm_refclk_too_high  : std_logic                                    := '0' -- default domino wave off
    15663 "
     15546st "alarm_refclk_too_high  : std_logic                                    := '0' -- default domino wave off"
    1566415547)
    1566515548)
    … …  
    1572515608)
    1572615609xt "-172000,21600,-118500,22400"
    15727 st "alarm_refclk_too_low   : std_logic                                    := '0' -- default domino wave off
    15728 "
     15610st "alarm_refclk_too_low   : std_logic                                    := '0' -- default domino wave off"
    1572915611)
    1573015612)
    … …  
    1578915671)
    1579015672xt "-172000,23200,-126000,24000"
    15791 st "counter_result         : std_logic_vector(11 downto 0)                := (others => '0')
    15792 "
     15673st "counter_result         : std_logic_vector(11 downto 0)                := (others => '0')"
    1579315674)
    1579415675)
    … …  
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    16948 st "SIGNAL denable_prim           : std_logic                                    := '0' -- default domino wave off
    16949 "
     16829st "SIGNAL denable_prim           : std_logic                                    := '0' -- default domino wave off"
    1695016830)
    1695116831)
    … …  
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    1696816848xt "-172000,64400,-115000,65200"
    16969 st "SIGNAL din1                   : std_logic                                    := '0' -- default domino wave off
    16970 "
     16849st "SIGNAL din1                   : std_logic                                    := '0' -- default domino wave off"
    1697116850)
    1697216851)
    … …  
    1698816867)
    1698916868xt "-172000,62800,-115000,63600"
    16990 st "SIGNAL denable_inhibit        : std_logic                                    := '0' -- default domino wave off
    16991 "
    16992 )
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    16994 *598 (Wire
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    2547325457)
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    … …  
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    … …  
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    … …  
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    … …  
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    2638326386dimension 100
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     26401*1062 (MRCItem
     26402litem &803
    2640026403pos 7
    2640126404dimension 290
    … …  
    2641726420genericsCommonDM (CommonDM
    2641826421ldm (LogicalDM
    26419 emptyRow *1057 (LEmptyRow
     26422emptyRow *1063 (LEmptyRow
    2642026423)
    2642126424uid 83,0
    2642226425optionalChildren [
    26423 *1058 (RefLabelRowHdr
    26424 )
    26425 *1059 (TitleRowHdr
    26426 )
    26427 *1060 (FilterRowHdr
    26428 )
    26429 *1061 (RefLabelColHdr
     26426*1064 (RefLabelRowHdr
     26427)
     26428*1065 (TitleRowHdr
     26429)
     26430*1066 (FilterRowHdr
     26431)
     26432*1067 (RefLabelColHdr
    2643026433tm "RefLabelColHdrMgr"
    2643126434)
    26432 *1062 (RowExpandColHdr
     26435*1068 (RowExpandColHdr
    2643326436tm "RowExpandColHdrMgr"
    2643426437)
    26435 *1063 (GroupColHdr
     26438*1069 (GroupColHdr
    2643626439tm "GroupColHdrMgr"
    2643726440)
    26438 *1064 (NameColHdr
     26441*1070 (NameColHdr
    2643926442tm "GenericNameColHdrMgr"
    2644026443)
    26441 *1065 (TypeColHdr
     26444*1071 (TypeColHdr
    2644226445tm "GenericTypeColHdrMgr"
    2644326446)
    26444 *1066 (InitColHdr
     26447*1072 (InitColHdr
    2644526448tm "GenericValueColHdrMgr"
    2644626449)
    26447 *1067 (PragmaColHdr
     26450*1073 (PragmaColHdr
    2644826451tm "GenericPragmaColHdrMgr"
    2644926452)
    26450 *1068 (EolColHdr
     26453*1074 (EolColHdr
    2645126454tm "GenericEolColHdrMgr"
    2645226455)
    26453 *1069 (LogGeneric
     26456*1075 (LogGeneric
    2645426457generic (GiElement
    2645526458name "RAMADDRWIDTH64b"
    … …  
    2646626469uid 95,0
    2646726470optionalChildren [
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     26471*1076 (Sheet
    2646926472sheetRow (SheetRow
    2647026473headerVa (MVa
    … …  
    2648326486font "Tahoma,10,0"
    2648426487)
    26485 emptyMRCItem *1071 (MRCItem
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    … …  
    2649026493uid 97,0
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     26507*1080 (MRCItem
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    2650726510hidden 1
    … …  
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    … …  
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  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb

    r10138 r10155  
    11991199(vvPair
    12001200variable "date"
    1201 value "08.02.2011"
     1201value "15.02.2011"
    12021202)
    12031203(vvPair
    … …  
    12111211(vvPair
    12121212variable "dd"
    1213 value "08"
     1213value "15"
    12141214)
    12151215(vvPair
    … …  
    13511351(vvPair
    13521352variable "time"
    1353 value "11:06:22"
     1353value "09:27:14"
    13541354)
    13551355(vvPair
    … …  
    40004000)
    40014001)
    4002 lastUid 5942,0
     4002lastUid 5988,0
    40034003okToSyncOnLoad 1
    40044004OkToSyncGenericsOnLoad 1

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/struct.bd

    r10129 r10155  
    1515unitName "numeric_std"
    1616)
     17(DmPackageRef
     18library "FACT_FAD_lib"
     19unitName "fad_definitions"
     20)
    1721]
    1822instances [
    … …  
    5761"ieee"
    5862"UNISIM"
     63"FACT_FAD_lib"
    5964]
    6065)
    … …  
    107112(vvPair
    108113variable "date"
    109 value "04.02.2011"
     114value "12.02.2011"
    110115)
    111116(vvPair
    112117variable "day"
    113 value "Fr"
     118value "Sa"
    114119)
    115120(vvPair
    116121variable "day_long"
    117 value "Freitag"
     122value "Samstag"
    118123)
    119124(vvPair
    120125variable "dd"
    121 value "04"
     126value "12"
    122127)
    123128(vvPair
    … …  
    255260(vvPair
    256261variable "time"
    257 value "12:52:25"
     262value "13:16:51"
    258263)
    259264(vvPair
    … …  
    761766)
    762767xt "11000,-9200,24000,-8400"
    763 st "CLK_50      : std_logic"
     768st "CLK_50      : std_logic
     769"
    764770)
    765771)
    … …  
    778784)
    779785xt "11000,-10800,24000,-10000"
    780 st "CLK_25      : std_logic"
     786st "CLK_25      : std_logic
     787"
    781788)
    782789)
    … …  
    795802)
    796803xt "11000,-14000,24000,-13200"
    797 st "CLK         : std_logic"
     804st "CLK         : std_logic
     805"
    798806)
    799807)
    … …  
    15631571)
    15641572xt "11000,-6600,27500,-5800"
    1565 st "SIGNAL CLK0_OUT    : std_logic"
     1573st "SIGNAL CLK0_OUT    : std_logic
     1574"
    15661575)
    15671576)
    … …  
    15801589)
    15811590xt "11000,-5000,27500,-4200"
    1582 st "SIGNAL PSCLK_IN    : std_logic"
     1591st "SIGNAL PSCLK_IN    : std_logic
     1592"
    15831593)
    15841594)
    … …  
    15971607)
    15981608xt "11000,-3400,27500,-2600"
    1599 st "SIGNAL PSEN_IN     : std_logic"
     1609st "SIGNAL PSEN_IN     : std_logic
     1610"
    16001611)
    16011612)
    … …  
    16141625)
    16151626xt "11000,-2600,27500,-1800"
    1616 st "SIGNAL PSINCDEC_IN : std_logic"
     1627st "SIGNAL PSINCDEC_IN : std_logic
     1628"
    16171629)
    16181630)
    … …  
    16311643)
    16321644xt "11000,-4200,27500,-3400"
    1633 st "SIGNAL PSDONE_OUT  : std_logic"
     1645st "SIGNAL PSDONE_OUT  : std_logic
     1646"
    16341647)
    16351648)
    … …  
    16481661)
    16491662xt "11000,-5800,27500,-5000"
    1650 st "SIGNAL LOCKED_OUT  : std_logic"
     1663st "SIGNAL LOCKED_OUT  : std_logic
     1664"
    16511665)
    16521666)
    … …  
    18741888n "LOCKED"
    18751889t "std_logic"
     1890eolc "-- when is this going high?"
    18761891preAdd 0
    18771892posAdd 0
    … …  
    19892004preAdd 0
    19902005posAdd 0
    1991 o 10
     2006o 11
    19922007suid 10,0
    19932008i "'0'"
    … …  
    20282043preAdd 0
    20292044posAdd 0
    2030 o 11
     2045o 12
    20312046suid 11,0
    20322047i "'0'"
    … …  
    20682083preAdd 0
    20692084posAdd 0
    2070 o 12
     2085o 13
    20712086suid 12,0
    20722087i "(OTHERS => '0')"
    … …  
    20752090)
    20762091*62 (CptPort
    2077 uid 815,0
    2078 ps "OnEdgeStrategy"
    2079 shape (Triangle
    2080 uid 816,0
    2081 ro 90
    2082 va (VaSet
    2083 vasetType 1
    2084 fg "0,65535,0"
    2085 )
    2086 xt "64000,32625,64750,33375"
    2087 )
    2088 tg (CPTG
    2089 uid 817,0
    2090 ps "CptPortTextPlaceStrategy"
    2091 stg "RightVerticalLayoutStrategy"
    2092 f (Text
    2093 uid 818,0
    2094 va (VaSet
    2095 )
    2096 xt "57800,32500,63000,33500"
    2097 st "DCM_locked"
    2098 ju 2
    2099 blo "63000,33300"
    2100 )
    2101 )
    2102 thePort (LogicalPort
    2103 m 1
    2104 decl (Decl
    2105 n "DCM_locked"
    2106 t "std_logic"
    2107 preAdd 0
    2108 posAdd 0
    2109 o 13
    2110 suid 13,0
    2111 )
    2112 )
    2113 )
    2114 *63 (CptPort
    21152092uid 1621,0
    21162093ps "OnEdgeStrategy"
    21172094shape (Triangle
    2118 uid 1622,0
    2119 ro 90
     2095ro 270
    21202096va (VaSet
    21212097vasetType 1
    … …  
    21382114)
    21392115thePort (LogicalPort
     2116m 1
    21402117decl (Decl
    21412118n "rst"
    … …  
    21452122o 2
    21462123suid 15,0
     2124i "'0'"
     2125)
     2126)
     2127)
     2128*63 (CptPort
     2129uid 1975,0
     2130ps "OnEdgeStrategy"
     2131shape (Triangle
     2132uid 1976,0
     2133ro 90
     2134va (VaSet
     2135vasetType 1
     2136fg "0,65535,0"
     2137)
     2138xt "37250,41625,38000,42375"
     2139)
     2140tg (CPTG
     2141uid 1977,0
     2142ps "CptPortTextPlaceStrategy"
     2143stg "VerticalLayoutStrategy"
     2144f (Text
     2145uid 1978,0
     2146va (VaSet
     2147)
     2148xt "39000,41500,43400,42500"
     2149st "reset_DCM"
     2150blo "39000,42300"
     2151)
     2152)
     2153thePort (LogicalPort
     2154decl (Decl
     2155n "reset_DCM"
     2156t "std_logic"
     2157eolc "-- asynch in: orders us, to reset the DCM"
     2158posAdd 0
     2159o 10
     2160suid 17,0
    21472161)
    21482162)
    … …  
    21572171lineWidth 2
    21582172)
    2159 xt "38000,28000,64000,43000"
     2173xt "38000,28000,64000,44000"
    21602174)
    21612175oxt "50000,7000,63000,25000"
    … …  
    22212235fg "49152,49152,49152"
    22222236)
    2223 xt "38250,41250,39750,42750"
     2237xt "38250,42250,39750,43750"
    22242238iconName "VhdlFileViewIcon.png"
    22252239iconMaskName "VhdlFileViewIcon.msk"
    … …  
    22912305)
    22922306xt "11000,-10000,24000,-9200"
    2293 st "CLK_25_PS   : std_logic"
     2307st "CLK_25_PS   : std_logic
     2308"
    22942309)
    22952310)
    … …  
    23542369)
    23552370xt "11000,-11600,24000,-10800"
    2356 st "do_shift    : std_logic"
     2371st "do_shift    : std_logic
     2372"
    23572373)
    23582374)
    … …  
    24172433)
    24182434xt "11000,-12400,24000,-11600"
    2419 st "direction   : std_logic"
     2435st "direction   : std_logic
     2436"
    24202437)
    24212438)
    … …  
    24342451)
    24352452xt "11000,-13200,24000,-12400"
    2436 st "RST_IN      : std_logic"
     2453st "RST_IN      : std_logic
     2454"
    24372455)
    24382456)
    … …  
    24502468sl 0
    24512469ro 270
    2452 xt "6000,35625,7500,36375"
     2470xt "28000,42625,29500,43375"
    24532471)
    24542472(Line
    … …  
    24562474sl 0
    24572475ro 270
    2458 xt "7500,36000,8000,36000"
     2476xt "29500,43000,30000,43000"
    24592477pts [
    2460 "7500,36000"
    2461 "8000,36000"
     2478"29500,43000"
     2479"30000,43000"
    24622480]
    24632481)
    … …  
    24752493font "arial,8,0"
    24762494)
    2477 xt "1800,35500,5000,36500"
     2495xt "23800,42500,27000,43500"
    24782496st "RST_IN"
    24792497ju 2
    2480 blo "5000,36300"
     2498blo "27000,43300"
    24812499tm "WireNameMgr"
    24822500)
    … …  
    25012519)
    25022520xt "11000,-8400,43500,-7600"
    2503 st "offset      : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"
     2521st "offset      : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')
     2522"
    25042523)
    25052524)
    … …  
    25492568)
    25502569)
    2551 *77 (Wire
     2570*77 (Net
     2571uid 1979,0
     2572decl (Decl
     2573n "rst"
     2574t "std_logic"
     2575eolc "--asynch in of DCM"
     2576posAdd 0
     2577o 15
     2578suid 40,0
     2579i "'0'"
     2580)
     2581declText (MLText
     2582uid 1980,0
     2583va (VaSet
     2584font "Courier New,8,0"
     2585)
     2586xt "11000,-1800,50500,-1000"
     2587st "SIGNAL rst         : std_logic                    := '0' --asynch in of DCM
     2588"
     2589)
     2590)
     2591*78 (Wire
    25522592uid 163,0
    25532593shape (OrthoPolyLine
    … …  
    25882628on &17
    25892629)
    2590 *78 (Wire
     2630*79 (Wire
    25912631uid 191,0
    25922632shape (OrthoPolyLine
    … …  
    26272667on &15
    26282668)
    2629 *79 (Wire
     2669*80 (Wire
    26302670uid 209,0
    26312671optionalChildren [
    2632 *80 (BdJunction
     2672*81 (BdJunction
    26332673uid 233,0
    26342674ps "OnConnectorStrategy"
    … …  
    26802720on &16
    26812721)
    2682 *81 (Wire
     2722*82 (Wire
    26832723uid 229,0
    26842724shape (OrthoPolyLine
    … …  
    26942734]
    26952735)
    2696 start &80
     2736start &81
    26972737end &19
    26982738sat 32
    … …  
    27192759on &16
    27202760)
    2721 *82 (Wire
     2761*83 (Wire
    27222762uid 526,0
    27232763shape (OrthoPolyLine
    … …  
    27602800on &44
    27612801)
    2762 *83 (Wire
     2802*84 (Wire
    27632803uid 532,0
    27642804shape (OrthoPolyLine
    … …  
    28032843on &45
    28042844)
    2805 *84 (Wire
     2845*85 (Wire
    28062846uid 546,0
    28072847shape (OrthoPolyLine
    … …  
    28462886on &46
    28472887)
    2848 *85 (Wire
     2888*86 (Wire
    28492889uid 588,0
    28502890shape (OrthoPolyLine
    … …  
    28852925on &48
    28862926)
    2887 *86 (Wire
     2927*87 (Wire
    28882928uid 602,0
    28892929shape (OrthoPolyLine
    … …  
    29242964on &49
    29252965)
    2926 *87 (Wire
     2966*88 (Wire
    29272967uid 841,0
    29282968shape (OrthoPolyLine
    … …  
    29673007on &47
    29683008)
    2969 *88 (Wire
     3009*89 (Wire
    29703010uid 1254,0
    29713011shape (OrthoPolyLine
    … …  
    30063046on &68
    30073047)
    3008 *89 (Wire
     3048*90 (Wire
    30093049uid 1272,0
    30103050shape (OrthoPolyLine
    … …  
    30453085on &70
    30463086)
    3047 *90 (Wire
     3087*91 (Wire
    30483088uid 1286,0
    30493089shape (OrthoPolyLine
    … …  
    30843124on &72
    30853125)
    3086 *91 (Wire
     3126*92 (Wire
    30873127uid 1458,0
    30883128shape (OrthoPolyLine
    … …  
    31213161on &44
    31223162)
    3123 *92 (Wire
     3163*93 (Wire
    31243164uid 1493,0
    3125 optionalChildren [
    3126 *93 (BdJunction
    3127 uid 1629,0
    3128 ps "OnConnectorStrategy"
    3129 shape (Circle
    3130 uid 1630,0
    3131 va (VaSet
    3132 vasetType 1
    3133 )
    3134 xt "9600,35600,10400,36400"
    3135 radius 400
    3136 )
    3137 )
    3138 ]
    31393165shape (OrthoPolyLine
    31403166uid 1494,0
    … …  
    31423168vasetType 3
    31433169)
    3144 xt "8000,36000,13250,36000"
     3170xt "30000,42000,37250,43000"
    31453171pts [
    3146 "8000,36000"
    3147 "13250,36000"
     3172"30000,43000"
     3173"37250,42000"
    31483174]
    31493175)
    31503176start &74
    3151 end &40
     3177end &63
     3178es 0
    31523179sat 32
    31533180eat 32
    … …  
    31663193font "arial,8,0"
    31673194)
    3168 xt "9000,35000,12200,36000"
     3195xt "31000,42000,34200,43000"
    31693196st "RST_IN"
    3170 blo "9000,35800"
     3197blo "31000,42800"
    31713198tm "WireNameMgr"
    31723199)
    … …  
    32163243)
    32173244*95 (Wire
    3218 uid 1625,0
     3245uid 1981,0
    32193246shape (OrthoPolyLine
    3220 uid 1626,0
     3247uid 1982,0
    32213248va (VaSet
    32223249vasetType 3
    32233250)
    3224 xt "10000,36000,37250,41000"
     3251xt "8000,36000,37250,41000"
    32253252pts [
    32263253"37250,41000"
    3227 "10000,41000"
    3228 "10000,36000"
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    … …  
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    32913318LIBRARY UNISIM;
    3292 --USE UNISIM.Vcomponents.all;"
     3319--USE UNISIM.Vcomponents.all;
     3320LIBRARY FACT_FAD_lib;
     3321USE FACT_FAD_lib.fad_definitions.all;"
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  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/struct.bd.bak

    r10129 r10155  
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     114value "12.02.2011"
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     118value "Sa"
    114119)
    115120(vvPair
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    117 value "Freitag"
     122value "Samstag"
    118123)
    119124(vvPair
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    121 value "04"
     126value "12"
    122127)
    123128(vvPair
    … …  
    255260(vvPair
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     262value "13:14:23"
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    32883307USE ieee.std_logic_1164.all;
    … …  
    32903309USE ieee.numeric_std.all;
    32913310LIBRARY UNISIM;
    3292 --USE UNISIM.Vcomponents.all;"
     3311--USE UNISIM.Vcomponents.all;
     3312LIBRARY FACT_FAD_lib;
     3313USE FACT_FAD_lib.fad_definitions.all;"
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    4411 xt "20000,0,20000,0"
     4432xt "9000,-16000,9000,-16000"
    44124433tm "BdDeclarativeTextMgr"
    44134434)

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/symbol.sb

    r10129 r10155  
    523523(vvPair
    524524variable "date"
    525 value "04.02.2011"
     525value "12.02.2011"
    526526)
    527527(vvPair
    528528variable "day"
    529 value "Fr"
     529value "Sa"
    530530)
    531531(vvPair
    532532variable "day_long"
    533 value "Freitag"
     533value "Samstag"
    534534)
    535535(vvPair
    536536variable "dd"
    537 value "04"
     537value "12"
    538538)
    539539(vvPair
    … …  
    671671(vvPair
    672672variable "time"
    673 value "12:52:25"
     673value "13:16:51"
    674674)
    675675(vvPair
    … …  
    17521752)
    17531753)
    1754 lastUid 1044,0
     1754lastUid 1113,0
    17551755okToSyncOnLoad 1
    17561756OkToSyncGenericsOnLoad 1

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/data_generator/symbol.sb

    r10121 r10155  
    2929)
    3030version "24.1"
    31 appVersion "2009.1 (Build 12)"
     31appVersion "2009.2 (Build 10)"
    3232model (Symbol
    3333commonDM (CommonDM
    3434ldm (LogicalDM
    3535ordering 1
    36 suid 63,0
     36suid 75,0
    3737usingSuid 1
    3838emptyRow *1 (LEmptyRow
    … …  
    153153t "std_logic_vector"
    154154b "(3 downto 0)"
     155prec "--
     156
     157-- EVT HEADER - part 4"
    155158preAdd 0
    156159posAdd 0
    157 o 24
     160o 31
    158161suid 9,0
    159162)
    … …  
    164167port (LogicalPort
    165168decl (Decl
    166 n "trigger_id"
    167 t "std_logic_vector"
    168 b "(47 downto 0)"
     169n "trigger"
     170t "std_logic"
     171prec "--"
    169172preAdd 0
    170173posAdd 0
    171 o 26
    172 suid 10,0
    173 )
    174 )
    175 uid 127,0
     174o 38
     175suid 11,0
     176)
     177)
     178uid 129,0
    176179)
    177180*21 (LogPort
    178 port (LogicalPort
    179 decl (Decl
    180 n "trigger"
    181 t "std_logic"
    182 preAdd 0
    183 posAdd 0
    184 o 27
    185 suid 11,0
    186 )
    187 )
    188 uid 129,0
    189 )
    190 *22 (LogPort
    191181port (LogicalPort
    192182decl (Decl
    … …  
    194184t "std_logic_vector"
    195185b "(1 downto 0)"
    196 o 25
     186posAdd 0
     187o 32
    197188suid 12,0
    198189)
    … …  
    200191uid 290,0
    201192)
    202 *23 (LogPort
     193*22 (LogPort
    203194port (LogicalPort
    204195decl (Decl
    … …  
    211202uid 421,0
    212203)
    213 *24 (LogPort
     204*23 (LogPort
    214205port (LogicalPort
    215206m 1
    … …  
    225216uid 423,0
    226217)
    227 *25 (LogPort
     218*24 (LogPort
    228219port (LogicalPort
    229220decl (Decl
    … …  
    236227uid 425,0
    237228)
    238 *26 (LogPort
     229*25 (LogPort
    239230port (LogicalPort
    240231decl (Decl
    … …  
    247238uid 478,0
    248239)
    249 *27 (LogPort
     240*26 (LogPort
    250241port (LogicalPort
    251242decl (Decl
    … …  
    253244t "std_logic_vector"
    254245b "(15 downto 0)"
     246prec "-- EVT HEADER - part 1"
     247preAdd 0
    255248o 23
    256249suid 20,0
    … …  
    259252uid 531,0
    260253)
    261 *28 (LogPort
     254*27 (LogPort
    262255port (LogicalPort
    263256m 1
    … …  
    265258n "adc_oeb"
    266259t "std_logic"
    267 o 31
     260o 42
    268261suid 23,0
    269262i "'1'"
    … …  
    272265uid 649,0
    273266)
    274 *29 (LogPort
     267*28 (LogPort
    275268port (LogicalPort
    276269m 1
    … …  
    280273b "(3 downto 0)"
    281274posAdd 0
    282 o 34
     275o 45
    283276suid 25,0
    284277i "(others => '0')"
    … …  
    287280uid 701,0
    288281)
    289 *30 (LogPort
     282*29 (LogPort
    290283port (LogicalPort
    291284m 1
    … …  
    296289preAdd 0
    297290posAdd 0
    298 o 37
     291o 48
    299292suid 26,0
    300293i "'0'"
    … …  
    303296uid 703,0
    304297)
    305 *31 (LogPort
     298*30 (LogPort
    306299port (LogicalPort
    307300m 1
    … …  
    311304prec "-- --"
    312305preAdd 0
    313 o 38
     306o 49
    314307suid 33,0
    315308i "'0'"
    … …  
    318311uid 816,0
    319312)
     313*31 (LogPort
     314port (LogicalPort
     315decl (Decl
     316n "drs_read_s_cell_ready"
     317t "std_logic"
     318o 54
     319suid 34,0
     320)
     321)
     322uid 818,0
     323)
    320324*32 (LogPort
    321 port (LogicalPort
    322 decl (Decl
    323 n "drs_read_s_cell_ready"
    324 t "std_logic"
    325 o 43
    326 suid 34,0
    327 )
    328 )
    329 uid 818,0
    330 )
    331 *33 (LogPort
    332325port (LogicalPort
    333326decl (Decl
    334327n "drs_s_cell_array"
    335328t "drs_s_cell_array_type"
    336 o 44
     329o 55
    337330suid 35,0
    338331)
    … …  
    340333uid 820,0
    341334)
    342 *34 (LogPort
     335*33 (LogPort
    343336port (LogicalPort
    344337decl (Decl
    345338n "adc_data_array"
    346339t "adc_data_array_type"
    347 o 30
     340o 41
    348341suid 37,0
    349342)
    … …  
    351344uid 903,0
    352345)
    353 *35 (LogPort
     346*34 (LogPort
    354347port (LogicalPort
    355348decl (Decl
    … …  
    362355uid 968,0
    363356)
    364 *36 (LogPort
     357*35 (LogPort
    365358port (LogicalPort
    366359m 1
    … …  
    378371uid 970,0
    379372)
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     373*36 (LogPort
    381374port (LogicalPort
    382375decl (Decl
    … …  
    389382uid 1058,0
    390383)
    391 *38 (LogPort
     384*37 (LogPort
    392385port (LogicalPort
    393386decl (Decl
    … …  
    400393uid 1060,0
    401394)
    402 *39 (LogPort
     395*38 (LogPort
    403396port (LogicalPort
    404397decl (Decl
    … …  
    411404uid 1095,0
    412405)
    413 *40 (LogPort
     406*39 (LogPort
    414407port (LogicalPort
    415408decl (Decl
    … …  
    422415uid 1097,0
    423416)
    424 *41 (LogPort
     417*40 (LogPort
    425418port (LogicalPort
    426419m 1
    … …  
    438431uid 1132,0
    439432)
    440 *42 (LogPort
     433*41 (LogPort
    441434port (LogicalPort
    442435m 1
    … …  
    453446uid 1134,0
    454447)
    455 *43 (LogPort
     448*42 (LogPort
    456449port (LogicalPort
    457450m 1
    … …  
    459452n "config_started"
    460453t "std_logic"
    461 o 29
     454o 40
    462455suid 48,0
    463456i "'0'"
    … …  
    466459uid 1169,0
    467460)
    468 *44 (LogPort
     461*43 (LogPort
    469462port (LogicalPort
    470463decl (Decl
    … …  
    473466prec "--      s_trigger      : in std_logic;"
    474467preAdd 0
    475 o 28
     468o 39
    476469suid 49,0
    477470)
    … …  
    479472uid 1171,0
    480473)
    481 *45 (LogPort
     474*44 (LogPort
    482475port (LogicalPort
    483476decl (Decl
    … …  
    490483uid 1211,0
    491484)
    492 *46 (LogPort
     485*45 (LogPort
    493486port (LogicalPort
    494487decl (Decl
    … …  
    501494uid 1213,0
    502495)
    503 *47 (LogPort
     496*46 (LogPort
    504497port (LogicalPort
    505498decl (Decl
    … …  
    512505uid 1215,0
    513506)
    514 *48 (LogPort
     507*47 (LogPort
    515508port (LogicalPort
    516509decl (Decl
    517510n "dac_array"
    518511t "dac_array_type"
     512posAdd 0
    519513o 22
    520514suid 53,0
    … …  
    523517uid 1245,0
    524518)
    525 *49 (LogPort
     519*48 (LogPort
    526520port (LogicalPort
    527521m 1
    … …  
    529523n "adc_clk_en"
    530524t "std_logic"
    531 o 32
     525o 43
    532526suid 54,0
    533527i "'0'"
    … …  
    536530uid 1400,0
    537531)
    538 *50 (LogPort
     532*49 (LogPort
    539533port (LogicalPort
    540534decl (Decl
    … …  
    542536t "std_logic_vector"
    543537b "(3 downto 0)"
    544 o 33
     538o 44
    545539suid 55,0
    546540)
    … …  
    548542uid 1432,0
    549543)
    550 *51 (LogPort
     544*50 (LogPort
    551545port (LogicalPort
    552546m 1
    … …  
    555549t "std_logic_vector"
    556550b "(7 downto 0)"
    557 o 41
     551o 52
    558552suid 56,0
    559553i "(others => '0')"
    … …  
    562556uid 1484,0
    563557)
    564 *52 (LogPort
     558*51 (LogPort
    565559port (LogicalPort
    566560m 1
    … …  
    568562n "drs_srin_write_8b"
    569563t "std_logic"
    570 o 39
     564o 50
    571565suid 57,0
    572566i "'0'"
    … …  
    575569uid 1486,0
    576570)
     571*52 (LogPort
     572port (LogicalPort
     573decl (Decl
     574n "drs_srin_write_ack"
     575t "std_logic"
     576o 51
     577suid 58,0
     578)
     579)
     580uid 1488,0
     581)
    577582*53 (LogPort
    578583port (LogicalPort
    579584decl (Decl
    580 n "drs_srin_write_ack"
    581 t "std_logic"
    582 o 40
    583 suid 58,0
    584 )
    585 )
    586 uid 1488,0
     585n "drs_srin_write_ready"
     586t "std_logic"
     587o 53
     588suid 59,0
     589)
     590)
     591uid 1490,0
    587592)
    588593*54 (LogPort
    589 port (LogicalPort
    590 decl (Decl
    591 n "drs_srin_write_ready"
    592 t "std_logic"
    593 o 42
    594 suid 59,0
    595 )
    596 )
    597 uid 1490,0
    598 )
    599 *55 (LogPort
    600594port (LogicalPort
    601595decl (Decl
    … …  
    611605uid 1492,0
    612606)
    613 *56 (LogPort
     607*55 (LogPort
    614608port (LogicalPort
    615609m 1
    … …  
    617611n "drs_readout_started"
    618612t "std_logic"
    619 o 45
     613o 56
    620614suid 61,0
    621615i "'0'"
    … …  
    624618uid 1524,0
    625619)
    626 *57 (LogPort
     620*56 (LogPort
    627621port (LogicalPort
    628622m 1
    … …  
    634628preAdd 0
    635629posAdd 0
    636 o 35
     630o 46
    637631suid 62,0
    638632i "'0'"
    … …  
    641635uid 1556,0
    642636)
     637*57 (LogPort
     638port (LogicalPort
     639decl (Decl
     640n "drs_readout_ready_ack"
     641t "std_logic"
     642o 47
     643suid 63,0
     644)
     645)
     646uid 1588,0
     647)
    643648*58 (LogPort
    644649port (LogicalPort
    645650decl (Decl
    646 n "drs_readout_ready_ack"
    647 t "std_logic"
     651n "pll_lock"
     652t "std_logic_vector"
     653b "( 3 downto 0)"
     654posAdd 0
     655o 24
     656suid 64,0
     657)
     658)
     659uid 1620,0
     660)
     661*59 (LogPort
     662port (LogicalPort
     663decl (Decl
     664n "fad_event_counter"
     665t "std_logic_vector"
     666b "(31 downto 0)"
     667prec "--
     668
     669-- EVT HEADER - part 3"
     670preAdd 0
     671o 27
     672suid 65,0
     673)
     674)
     675uid 1652,0
     676)
     677*60 (LogPort
     678port (LogicalPort
     679decl (Decl
     680n "refclk_counter"
     681t "std_logic_vector"
     682b "(11 downto 0)"
     683o 28
     684suid 66,0
     685)
     686)
     687uid 1694,0
     688)
     689*61 (LogPort
     690port (LogicalPort
     691decl (Decl
     692n "refclk_too_high"
     693t "std_logic"
     694o 29
     695suid 67,0
     696)
     697)
     698uid 1696,0
     699)
     700*62 (LogPort
     701port (LogicalPort
     702decl (Decl
     703n "refclk_too_low"
     704t "std_logic"
     705posAdd 0
     706o 30
     707suid 68,0
     708)
     709)
     710uid 1698,0
     711)
     712*63 (LogPort
     713port (LogicalPort
     714decl (Decl
     715n "FTM_RS485_ready"
     716t "std_logic"
     717prec "--
     718
     719-- EVT HEADER - part 2  --> FTM trigger informaton, comes in late ...
     720-- during EVT header wrinting, this field is left out ... and only written into event header,
     721-- when the DRS chip were read out already."
     722preAdd 0
     723o 25
     724suid 69,0
     725)
     726)
     727uid 1735,0
     728)
     729*64 (LogPort
     730port (LogicalPort
     731decl (Decl
     732n "FTM_trigger_info"
     733t "std_logic_vector"
     734b "(55 downto 0)"
     735eolc "--7 byte"
     736posAdd 0
     737o 26
     738suid 70,0
     739)
     740)
     741uid 1737,0
     742)
     743*65 (LogPort
     744port (LogicalPort
     745decl (Decl
     746n "DCM_PS_status"
     747t "std_logic_vector"
     748b "(7 downto 0)"
     749o 33
     750suid 71,0
     751)
     752)
     753uid 1779,0
     754)
     755*66 (LogPort
     756port (LogicalPort
     757decl (Decl
     758n "TRG_GEN_div"
     759t "std_logic_vector"
     760b "(15 downto 0)"
     761posAdd 0
     762o 35
     763suid 72,0
     764)
     765)
     766uid 1781,0
     767)
     768*67 (LogPort
     769port (LogicalPort
     770decl (Decl
     771n "TRG_GEN_no"
     772t "std_logic_vector"
     773b "(15 downto 0)"
     774o 34
     775suid 73,0
     776)
     777)
     778uid 1783,0
     779)
     780*68 (LogPort
     781port (LogicalPort
     782decl (Decl
     783n "dna"
     784t "std_logic_vector"
     785b "(63 downto 0)"
     786prec "--
     787
     788-- EVT HEADER - part 5"
     789preAdd 0
     790posAdd 0
    648791o 36
    649 suid 63,0
    650 )
    651 )
    652 uid 1588,0
     792suid 74,0
     793)
     794)
     795uid 1815,0
     796)
     797*69 (LogPort
     798port (LogicalPort
     799decl (Decl
     800n "timer_value"
     801t "std_logic_vector"
     802b "(31 downto 0)"
     803prec "--
     804
     805-- EVT HEADER - part 6"
     806eolc "-- time in units of 100us"
     807preAdd 0
     808posAdd 0
     809o 37
     810suid 75,0
     811)
     812)
     813uid 1847,0
    653814)
    654815]
    … …  
    659820uid 149,0
    660821optionalChildren [
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     822*70 (Sheet
    662823sheetRow (SheetRow
    663824headerVa (MVa
    … …  
    676837font "Tahoma,10,0"
    677838)
    678 emptyMRCItem *60 (MRCItem
     839emptyMRCItem *71 (MRCItem
    679840litem &1
    680841pos 3
    … …  
    683844uid 151,0
    684845optionalChildren [
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    … …  
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    690851)
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    693854pos 1
    … …  
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    696857)
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    698859litem &4
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    … …  
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    703864)
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    … …  
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    … …  
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    … …  
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     906)
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     912)
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     936)
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     942)
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     948)
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     954)
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    12351462(vvPair
    … …  
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    12711498(vvPair
    … …  
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    12991526(vvPair
    … …  
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    13351562(vvPair
    … …  
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    13541581)
    13551582(vvPair
    … …  
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    13791606(vvPair
    … …  
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    … …  
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     1948-- EVT HEADER - part 4
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    … …  
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     1959-- EVT HEADER - part 4"
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    1746 tg (CPTG
    1747 uid 95,0
    1748 ps "CptPortTextPlaceStrategy"
    1749 stg "VerticalLayoutStrategy"
    1750 f (Text
    1751 uid 96,0
    1752 va (VaSet
    1753 )
    1754 xt "38000,11500,44800,12500"
    1755 st "trigger_id : (47:0)"
    1756 blo "38000,12300"
    1757 tm "CptPortNameMgr"
    1758 )
    1759 )
    1760 dt (MLText
    1761 uid 97,0
    1762 va (VaSet
    1763 font "Courier New,8,0"
    1764 )
    1765 xt "2000,36000,35500,36800"
    1766 st "trigger_id            : IN     std_logic_vector (47 downto 0) ;
    1767 "
    1768 )
    1769 thePort (LogicalPort
    1770 decl (Decl
    1771 n "trigger_id"
    1772 t "std_logic_vector"
    1773 b "(47 downto 0)"
    1774 preAdd 0
    1775 posAdd 0
    1776 o 26
    1777 suid 10,0
    1778 )
    1779 )
    1780 )
    1781 *151 (CptPort
     1967*172 (CptPort
    17821968uid 98,0
    17831969ps "OnEdgeStrategy"
    … …  
    18101996font "Courier New,8,0"
    18111997)
    1812 xt "2000,36800,25500,37600"
    1813 st "trigger               : IN     std_logic  ;
     1998xt "2000,60000,25500,61600"
     1999st "--
     2000trigger               : IN     std_logic  ;
    18142001"
    18152002)
    … …  
    18182005n "trigger"
    18192006t "std_logic"
     2007prec "--"
    18202008preAdd 0
    18212009posAdd 0
    1822 o 27
     2010o 38
    18232011suid 11,0
    18242012)
    18252013)
    18262014)
    1827 *152 (CommentText
     2015*173 (CommentText
    18282016uid 106,0
    18292017ps "EdgeToEdgeStrategy"
    … …  
    18592047excludeCommentLeader 1
    18602048)
    1861 *153 (CptPort
     2049*174 (CptPort
    18622050uid 285,0
    18632051ps "OnEdgeStrategy"
    … …  
    18902078font "Courier New,8,0"
    18912079)
    1892 xt "2000,35200,35000,36000"
     2080xt "2000,50400,35000,51200"
    18932081st "crate_id              : IN     std_logic_vector (1 downto 0) ;
    18942082"
    … …  
    18992087t "std_logic_vector"
    19002088b "(1 downto 0)"
    1901 o 25
     2089posAdd 0
     2090o 32
    19022091suid 12,0
    19032092)
    19042093)
    19052094)
    1906 *154 (CptPort
     2095*175 (CptPort
    19072096uid 402,0
    19082097ps "OnEdgeStrategy"
    … …  
    19482137)
    19492138)
    1950 *155 (CptPort
     2139*176 (CptPort
    19512140uid 407,0
    19522141ps "OnEdgeStrategy"
    … …  
    19962185)
    19972186)
    1998 *156 (CptPort
     2187*177 (CptPort
    19992188uid 412,0
    20002189ps "OnEdgeStrategy"
    … …  
    20402229)
    20412230)
    2042 *157 (CptPort
     2231*178 (CptPort
    20432232uid 473,0
    20442233ps "OnEdgeStrategy"
    … …  
    20842273)
    20852274)
    2086 *158 (CptPort
     2275*179 (CptPort
    20872276uid 526,0
    20882277ps "OnEdgeStrategy"
    … …  
    21152304font "Courier New,8,0"
    21162305)
    2117 xt "2000,33600,35500,34400"
    2118 st "package_length        : IN     std_logic_vector (15 downto 0) ;
     2306xt "2000,33600,35500,35200"
     2307st "-- EVT HEADER - part 1
     2308package_length        : IN     std_logic_vector (15 downto 0) ;
    21192309"
    21202310)
    … …  
    21242314t "std_logic_vector"
    21252315b "(15 downto 0)"
     2316prec "-- EVT HEADER - part 1"
     2317preAdd 0
    21262318o 23
    21272319suid 20,0
    … …  
    21292321)
    21302322)
    2131 *159 (CptPort
     2323*180 (CptPort
    21322324uid 637,0
    21332325ps "OnEdgeStrategy"
    … …  
    21612353font "Courier New,8,0"
    21622354)
    2163 xt "2000,40800,38500,41600"
     2355xt "2000,64800,38500,65600"
    21642356st "adc_oeb               : OUT    std_logic                     := '1' ;
    21652357"
    … …  
    21702362n "adc_oeb"
    21712363t "std_logic"
    2172 o 31
     2364o 42
    21732365suid 23,0
    21742366i "'1'"
    … …  
    21762368)
    21772369)
    2178 *160 (CptPort
     2370*181 (CptPort
    21792371uid 676,0
    21802372ps "OnEdgeStrategy"
    … …  
    22082400font "Courier New,8,0"
    22092401)
    2210 xt "2000,43200,44500,44000"
     2402xt "2000,67200,44500,68000"
    22112403st "drs_channel_id        : OUT    std_logic_vector (3 downto 0) := (others => '0') ;
    22122404"
    … …  
    22192411b "(3 downto 0)"
    22202412posAdd 0
    2221 o 34
     2413o 45
    22222414suid 25,0
    22232415i "(others => '0')"
    … …  
    22252417)
    22262418)
    2227 *161 (CptPort
     2419*182 (CptPort
    22282420uid 681,0
    22292421ps "OnEdgeStrategy"
    … …  
    22572449font "Courier New,8,0"
    22582450)
    2259 xt "2000,47200,38500,48800"
     2451xt "2000,71200,38500,72800"
    22602452st "-- --
    22612453drs_clk_en            : OUT    std_logic                     := '0' ;
    … …  
    22702462preAdd 0
    22712463posAdd 0
    2272 o 37
     2464o 48
    22732465suid 26,0
    22742466i "'0'"
    … …  
    22762468)
    22772469)
    2278 *162 (CptPort
     2470*183 (CptPort
    22792471uid 801,0
    22802472ps "OnEdgeStrategy"
    … …  
    23082500font "Courier New,8,0"
    23092501)
    2310 xt "2000,48800,38500,50400"
     2502xt "2000,72800,38500,74400"
    23112503st "-- --
    23122504drs_read_s_cell       : OUT    std_logic                     := '0' ;
    … …  
    23202512prec "-- --"
    23212513preAdd 0
    2322 o 38
     2514o 49
    23232515suid 33,0
    23242516i "'0'"
    … …  
    23262518)
    23272519)
    2328 *163 (CptPort
     2520*184 (CptPort
    23292521uid 806,0
    23302522ps "OnEdgeStrategy"
    … …  
    23572549font "Courier New,8,0"
    23582550)
    2359 xt "2000,53600,25500,54400"
     2551xt "2000,77600,25500,78400"
    23602552st "drs_read_s_cell_ready : IN     std_logic  ;
    23612553"
    … …  
    23652557n "drs_read_s_cell_ready"
    23662558t "std_logic"
    2367 o 43
     2559o 54
    23682560suid 34,0
    23692561)
    23702562)
    23712563)
    2372 *164 (CptPort
     2564*185 (CptPort
    23732565uid 811,0
    23742566ps "OnEdgeStrategy"
    … …  
    24012593font "Courier New,8,0"
    24022594)
    2403 xt "2000,54400,31500,55200"
     2595xt "2000,78400,31500,79200"
    24042596st "drs_s_cell_array      : IN     drs_s_cell_array_type  ;
    24052597"
    … …  
    24092601n "drs_s_cell_array"
    24102602t "drs_s_cell_array_type"
    2411 o 44
     2603o 55
    24122604suid 35,0
    24132605)
    24142606)
    24152607)
    2416 *165 (CptPort
     2608*186 (CptPort
    24172609uid 898,0
    24182610ps "OnEdgeStrategy"
    … …  
    24452637font "Courier New,8,0"
    24462638)
    2447 xt "2000,40000,30500,40800"
     2639xt "2000,64000,30500,64800"
    24482640st "adc_data_array        : IN     adc_data_array_type  ;
    24492641"
    … …  
    24532645n "adc_data_array"
    24542646t "adc_data_array_type"
    2455 o 30
     2647o 41
    24562648suid 37,0
    24572649)
    24582650)
    24592651)
    2460 *166 (CptPort
     2652*187 (CptPort
    24612653uid 958,0
    24622654ps "OnEdgeStrategy"
    … …  
    25022694)
    25032695)
    2504 *167 (CptPort
     2696*188 (CptPort
    25052697uid 963,0
    25062698ps "OnEdgeStrategy"
    … …  
    25532745)
    25542746)
    2555 *168 (CptPort
     2747*189 (CptPort
    25562748uid 1048,0
    25572749ps "OnEdgeStrategy"
    … …  
    25972789)
    25982790)
    2599 *169 (CptPort
     2791*190 (CptPort
    26002792uid 1053,0
    26012793ps "OnEdgeStrategy"
    … …  
    26412833)
    26422834)
    2643 *170 (CptPort
     2835*191 (CptPort
    26442836uid 1085,0
    26452837ps "OnEdgeStrategy"
    … …  
    26852877)
    26862878)
    2687 *171 (CptPort
     2879*192 (CptPort
    26882880uid 1090,0
    26892881ps "OnEdgeStrategy"
    … …  
    27292921)
    27302922)
    2731 *172 (CptPort
     2923*193 (CptPort
    27322924uid 1122,0
    27332925ps "OnEdgeStrategy"
    … …  
    27802972)
    27812973)
    2782 *173 (CptPort
     2974*194 (CptPort
    27832975uid 1127,0
    27842976ps "OnEdgeStrategy"
    … …  
    28303022)
    28313023)
    2832 *174 (CptPort
     3024*195 (CptPort
    28333025uid 1159,0
    28343026ps "OnEdgeStrategy"
    … …  
    28623054font "Courier New,8,0"
    28633055)
    2864 xt "2000,39200,38500,40000"
     3056xt "2000,63200,38500,64000"
    28653057st "config_started        : OUT    std_logic                     := '0' ;
    28663058"
    … …  
    28713063n "config_started"
    28723064t "std_logic"
    2873 o 29
     3065o 40
    28743066suid 48,0
    28753067i "'0'"
    … …  
    28773069)
    28783070)
    2879 *175 (CptPort
     3071*196 (CptPort
    28803072uid 1164,0
    28813073ps "OnEdgeStrategy"
    … …  
    29083100font "Courier New,8,0"
    29093101)
    2910 xt "2000,37600,25500,39200"
     3102xt "2000,61600,25500,63200"
    29113103st "--      s_trigger      : in std_logic;
    29123104new_config            : IN     std_logic  ;
    … …  
    29193111prec "--      s_trigger      : in std_logic;"
    29203112preAdd 0
    2921 o 28
     3113o 39
    29223114suid 49,0
    29233115)
    29243116)
    29253117)
    2926 *176 (CptPort
     3118*197 (CptPort
    29273119uid 1196,0
    29283120ps "OnEdgeStrategy"
    … …  
    29683160)
    29693161)
    2970 *177 (CptPort
     3162*198 (CptPort
    29713163uid 1201,0
    29723164ps "OnEdgeStrategy"
    … …  
    30123204)
    30133205)
    3014 *178 (CptPort
     3206*199 (CptPort
    30153207uid 1206,0
    30163208ps "OnEdgeStrategy"
    … …  
    30563248)
    30573249)
    3058 *179 (CptPort
     3250*200 (CptPort
    30593251uid 1240,0
    30603252ps "OnEdgeStrategy"
    … …  
    30953287n "dac_array"
    30963288t "dac_array_type"
     3289posAdd 0
    30973290o 22
    30983291suid 53,0
    … …  
    31003293)
    31013294)
    3102 *180 (CptPort
     3295*201 (CptPort
    31033296uid 1395,0
    31043297ps "OnEdgeStrategy"
    … …  
    31323325font "Courier New,8,0"
    31333326)
    3134 xt "2000,41600,38500,42400"
     3327xt "2000,65600,38500,66400"
    31353328st "adc_clk_en            : OUT    std_logic                     := '0' ;
    31363329"
    … …  
    31413334n "adc_clk_en"
    31423335t "std_logic"
    3143 o 32
     3336o 43
    31443337suid 54,0
    31453338i "'0'"
    … …  
    31473340)
    31483341)
    3149 *181 (CptPort
     3342*202 (CptPort
    31503343uid 1427,0
    31513344ps "OnEdgeStrategy"
    … …  
    31783371font "Courier New,8,0"
    31793372)
    3180 xt "2000,42400,35000,43200"
     3373xt "2000,66400,35000,67200"
    31813374st "adc_otr               : IN     std_logic_vector (3 downto 0) ;
    31823375"
    … …  
    31873380t "std_logic_vector"
    31883381b "(3 downto 0)"
    3189 o 33
     3382o 44
    31903383suid 55,0
    31913384)
    31923385)
    31933386)
    3194 *182 (CptPort
     3387*203 (CptPort
    31953388uid 1459,0
    31963389ps "OnEdgeStrategy"
    … …  
    32243417font "Courier New,8,0"
    32253418)
    3226 xt "2000,52000,44500,52800"
     3419xt "2000,76000,44500,76800"
    32273420st "drs_srin_data         : OUT    std_logic_vector (7 downto 0) := (others => '0') ;
    32283421"
    … …  
    32343427t "std_logic_vector"
    32353428b "(7 downto 0)"
    3236 o 41
     3429o 52
    32373430suid 56,0
    32383431i "(others => '0')"
    … …  
    32403433)
    32413434)
    3242 *183 (CptPort
     3435*204 (CptPort
    32433436uid 1464,0
    32443437ps "OnEdgeStrategy"
    … …  
    32723465font "Courier New,8,0"
    32733466)
    3274 xt "2000,50400,38500,51200"
     3467xt "2000,74400,38500,75200"
    32753468st "drs_srin_write_8b     : OUT    std_logic                     := '0' ;
    32763469"
    … …  
    32813474n "drs_srin_write_8b"
    32823475t "std_logic"
    3283 o 39
     3476o 50
    32843477suid 57,0
    32853478i "'0'"
    … …  
    32873480)
    32883481)
    3289 *184 (CptPort
     3482*205 (CptPort
    32903483uid 1469,0
    32913484ps "OnEdgeStrategy"
    … …  
    33183511font "Courier New,8,0"
    33193512)
    3320 xt "2000,51200,25500,52000"
     3513xt "2000,75200,25500,76000"
    33213514st "drs_srin_write_ack    : IN     std_logic  ;
    33223515"
    … …  
    33263519n "drs_srin_write_ack"
    33273520t "std_logic"
    3328 o 40
     3521o 51
    33293522suid 58,0
    33303523)
    33313524)
    33323525)
    3333 *185 (CptPort
     3526*206 (CptPort
    33343527uid 1474,0
    33353528ps "OnEdgeStrategy"
    … …  
    33623555font "Courier New,8,0"
    33633556)
    3364 xt "2000,52800,25500,53600"
     3557xt "2000,76800,25500,77600"
    33653558st "drs_srin_write_ready  : IN     std_logic  ;
    33663559"
    … …  
    33703563n "drs_srin_write_ready"
    33713564t "std_logic"
    3372 o 42
     3565o 53
    33733566suid 59,0
    33743567)
    33753568)
    33763569)
    3377 *186 (CptPort
     3570*207 (CptPort
    33783571uid 1479,0
    33793572ps "OnEdgeStrategy"
    … …  
    34233616)
    34243617)
    3425 *187 (CptPort
     3618*208 (CptPort
    34263619uid 1519,0
    34273620ps "OnEdgeStrategy"
    … …  
    34553648font "Courier New,8,0"
    34563649)
    3457 xt "2000,55200,37500,56000"
     3650xt "2000,79200,37500,80000"
    34583651st "drs_readout_started   : OUT    std_logic                     := '0'
    34593652"
    … …  
    34643657n "drs_readout_started"
    34653658t "std_logic"
    3466 o 45
     3659o 56
    34673660suid 61,0
    34683661i "'0'"
    … …  
    34703663)
    34713664)
    3472 *188 (CptPort
     3665*209 (CptPort
    34733666uid 1551,0
    34743667ps "OnEdgeStrategy"
    … …  
    35023695font "Courier New,8,0"
    35033696)
    3504 xt "2000,44000,38500,46400"
     3697xt "2000,68000,38500,70400"
    35053698st "-- --
    35063699--      drs_dwrite : out std_logic := '1';
    … …  
    35173710preAdd 0
    35183711posAdd 0
    3519 o 35
     3712o 46
    35203713suid 62,0
    35213714i "'0'"
    … …  
    35233716)
    35243717)
    3525 *189 (CptPort
     3718*210 (CptPort
    35263719uid 1583,0
    35273720ps "OnEdgeStrategy"
    … …  
    35543747font "Courier New,8,0"
    35553748)
     3749xt "2000,70400,25500,71200"
     3750st "drs_readout_ready_ack : IN     std_logic  ;
     3751"
     3752)
     3753thePort (LogicalPort
     3754decl (Decl
     3755n "drs_readout_ready_ack"
     3756t "std_logic"
     3757o 47
     3758suid 63,0
     3759)
     3760)
     3761)
     3762*211 (CptPort
     3763uid 1615,0
     3764ps "OnEdgeStrategy"
     3765shape (Triangle
     3766uid 1616,0
     3767ro 90
     3768va (VaSet
     3769vasetType 1
     3770fg "0,65535,0"
     3771)
     3772xt "36250,39625,37000,40375"
     3773)
     3774tg (CPTG
     3775uid 1617,0
     3776ps "CptPortTextPlaceStrategy"
     3777stg "VerticalLayoutStrategy"
     3778f (Text
     3779uid 1618,0
     3780va (VaSet
     3781)
     3782xt "38000,39500,43500,40500"
     3783st "pll_lock : (3:0)"
     3784blo "38000,40300"
     3785tm "CptPortNameMgr"
     3786)
     3787)
     3788dt (MLText
     3789uid 1619,0
     3790va (VaSet
     3791font "Courier New,8,0"
     3792)
     3793xt "2000,35200,35500,36000"
     3794st "pll_lock              : IN     std_logic_vector ( 3 downto 0) ;
     3795"
     3796)
     3797thePort (LogicalPort
     3798decl (Decl
     3799n "pll_lock"
     3800t "std_logic_vector"
     3801b "( 3 downto 0)"
     3802posAdd 0
     3803o 24
     3804suid 64,0
     3805)
     3806)
     3807)
     3808*212 (CptPort
     3809uid 1647,0
     3810ps "OnEdgeStrategy"
     3811shape (Triangle
     3812uid 1648,0
     3813ro 90
     3814va (VaSet
     3815vasetType 1
     3816fg "0,65535,0"
     3817)
     3818xt "36250,40625,37000,41375"
     3819)
     3820tg (CPTG
     3821uid 1649,0
     3822ps "CptPortTextPlaceStrategy"
     3823stg "VerticalLayoutStrategy"
     3824f (Text
     3825uid 1650,0
     3826va (VaSet
     3827)
     3828xt "38000,40500,47800,41500"
     3829st "fad_event_counter : (31:0)"
     3830blo "38000,41300"
     3831tm "CptPortNameMgr"
     3832)
     3833)
     3834dt (MLText
     3835uid 1651,0
     3836va (VaSet
     3837font "Courier New,8,0"
     3838)
     3839xt "2000,41600,35500,44800"
     3840st "--
     3841
     3842-- EVT HEADER - part 3
     3843fad_event_counter     : IN     std_logic_vector (31 downto 0) ;
     3844"
     3845)
     3846thePort (LogicalPort
     3847decl (Decl
     3848n "fad_event_counter"
     3849t "std_logic_vector"
     3850b "(31 downto 0)"
     3851prec "--
     3852
     3853-- EVT HEADER - part 3"
     3854preAdd 0
     3855o 27
     3856suid 65,0
     3857)
     3858)
     3859)
     3860*213 (CptPort
     3861uid 1679,0
     3862ps "OnEdgeStrategy"
     3863shape (Triangle
     3864uid 1680,0
     3865ro 90
     3866va (VaSet
     3867vasetType 1
     3868fg "0,65535,0"
     3869)
     3870xt "36250,41625,37000,42375"
     3871)
     3872tg (CPTG
     3873uid 1681,0
     3874ps "CptPortTextPlaceStrategy"
     3875stg "VerticalLayoutStrategy"
     3876f (Text
     3877uid 1682,0
     3878va (VaSet
     3879)
     3880xt "38000,41500,46500,42500"
     3881st "refclk_counter : (11:0)"
     3882blo "38000,42300"
     3883tm "CptPortNameMgr"
     3884)
     3885)
     3886dt (MLText
     3887uid 1683,0
     3888va (VaSet
     3889font "Courier New,8,0"
     3890)
     3891xt "2000,44800,35500,45600"
     3892st "refclk_counter        : IN     std_logic_vector (11 downto 0) ;
     3893"
     3894)
     3895thePort (LogicalPort
     3896decl (Decl
     3897n "refclk_counter"
     3898t "std_logic_vector"
     3899b "(11 downto 0)"
     3900o 28
     3901suid 66,0
     3902)
     3903)
     3904)
     3905*214 (CptPort
     3906uid 1684,0
     3907ps "OnEdgeStrategy"
     3908shape (Triangle
     3909uid 1685,0
     3910ro 90
     3911va (VaSet
     3912vasetType 1
     3913fg "0,65535,0"
     3914)
     3915xt "36250,42625,37000,43375"
     3916)
     3917tg (CPTG
     3918uid 1686,0
     3919ps "CptPortTextPlaceStrategy"
     3920stg "VerticalLayoutStrategy"
     3921f (Text
     3922uid 1687,0
     3923va (VaSet
     3924)
     3925xt "38000,42500,43900,43500"
     3926st "refclk_too_high"
     3927blo "38000,43300"
     3928tm "CptPortNameMgr"
     3929)
     3930)
     3931dt (MLText
     3932uid 1688,0
     3933va (VaSet
     3934font "Courier New,8,0"
     3935)
     3936xt "2000,45600,25500,46400"
     3937st "refclk_too_high       : IN     std_logic  ;
     3938"
     3939)
     3940thePort (LogicalPort
     3941decl (Decl
     3942n "refclk_too_high"
     3943t "std_logic"
     3944o 29
     3945suid 67,0
     3946)
     3947)
     3948)
     3949*215 (CptPort
     3950uid 1689,0
     3951ps "OnEdgeStrategy"
     3952shape (Triangle
     3953uid 1690,0
     3954ro 90
     3955va (VaSet
     3956vasetType 1
     3957fg "0,65535,0"
     3958)
     3959xt "36250,43625,37000,44375"
     3960)
     3961tg (CPTG
     3962uid 1691,0
     3963ps "CptPortTextPlaceStrategy"
     3964stg "VerticalLayoutStrategy"
     3965f (Text
     3966uid 1692,0
     3967va (VaSet
     3968)
     3969xt "38000,43500,43500,44500"
     3970st "refclk_too_low"
     3971blo "38000,44300"
     3972tm "CptPortNameMgr"
     3973)
     3974)
     3975dt (MLText
     3976uid 1693,0
     3977va (VaSet
     3978font "Courier New,8,0"
     3979)
    35563980xt "2000,46400,25500,47200"
    3557 st "drs_readout_ready_ack : IN     std_logic  ;
    3558 "
    3559 )
    3560 thePort (LogicalPort
    3561 decl (Decl
    3562 n "drs_readout_ready_ack"
    3563 t "std_logic"
     3981st "refclk_too_low        : IN     std_logic  ;
     3982"
     3983)
     3984thePort (LogicalPort
     3985decl (Decl
     3986n "refclk_too_low"
     3987t "std_logic"
     3988posAdd 0
     3989o 30
     3990suid 68,0
     3991)
     3992)
     3993)
     3994*216 (CptPort
     3995uid 1725,0
     3996ps "OnEdgeStrategy"
     3997shape (Triangle
     3998uid 1726,0
     3999ro 90
     4000va (VaSet
     4001vasetType 1
     4002fg "0,65535,0"
     4003)
     4004xt "36250,44625,37000,45375"
     4005)
     4006tg (CPTG
     4007uid 1727,0
     4008ps "CptPortTextPlaceStrategy"
     4009stg "VerticalLayoutStrategy"
     4010f (Text
     4011uid 1728,0
     4012va (VaSet
     4013)
     4014xt "38000,44500,45400,45500"
     4015st "FTM_RS485_ready"
     4016blo "38000,45300"
     4017tm "CptPortNameMgr"
     4018)
     4019)
     4020dt (MLText
     4021uid 1729,0
     4022va (VaSet
     4023font "Courier New,8,0"
     4024)
     4025xt "2000,36000,50500,40800"
     4026st "--
     4027
     4028-- EVT HEADER - part 2  --> FTM trigger informaton, comes in late ...
     4029-- during EVT header wrinting, this field is left out ... and only written into event header,
     4030-- when the DRS chip were read out already.
     4031FTM_RS485_ready       : IN     std_logic  ;
     4032"
     4033)
     4034thePort (LogicalPort
     4035decl (Decl
     4036n "FTM_RS485_ready"
     4037t "std_logic"
     4038prec "--
     4039
     4040-- EVT HEADER - part 2  --> FTM trigger informaton, comes in late ...
     4041-- during EVT header wrinting, this field is left out ... and only written into event header,
     4042-- when the DRS chip were read out already."
     4043preAdd 0
     4044o 25
     4045suid 69,0
     4046)
     4047)
     4048)
     4049*217 (CptPort
     4050uid 1730,0
     4051ps "OnEdgeStrategy"
     4052shape (Triangle
     4053uid 1731,0
     4054ro 90
     4055va (VaSet
     4056vasetType 1
     4057fg "0,65535,0"
     4058)
     4059xt "36250,45625,37000,46375"
     4060)
     4061tg (CPTG
     4062uid 1732,0
     4063ps "CptPortTextPlaceStrategy"
     4064stg "VerticalLayoutStrategy"
     4065f (Text
     4066uid 1733,0
     4067va (VaSet
     4068)
     4069xt "38000,45500,47900,46500"
     4070st "FTM_trigger_info : (55:0)"
     4071blo "38000,46300"
     4072tm "CptPortNameMgr"
     4073)
     4074)
     4075dt (MLText
     4076uid 1734,0
     4077va (VaSet
     4078font "Courier New,8,0"
     4079)
     4080xt "2000,40800,40000,41600"
     4081st "FTM_trigger_info      : IN     std_logic_vector (55 downto 0) ; --7 byte
     4082"
     4083)
     4084thePort (LogicalPort
     4085decl (Decl
     4086n "FTM_trigger_info"
     4087t "std_logic_vector"
     4088b "(55 downto 0)"
     4089eolc "--7 byte"
     4090posAdd 0
     4091o 26
     4092suid 70,0
     4093)
     4094)
     4095)
     4096*218 (CptPort
     4097uid 1764,0
     4098ps "OnEdgeStrategy"
     4099shape (Triangle
     4100uid 1765,0
     4101ro 90
     4102va (VaSet
     4103vasetType 1
     4104fg "0,65535,0"
     4105)
     4106xt "36250,46625,37000,47375"
     4107)
     4108tg (CPTG
     4109uid 1766,0
     4110ps "CptPortTextPlaceStrategy"
     4111stg "VerticalLayoutStrategy"
     4112f (Text
     4113uid 1767,0
     4114va (VaSet
     4115)
     4116xt "38000,46500,47100,47500"
     4117st "DCM_PS_status : (7:0)"
     4118blo "38000,47300"
     4119tm "CptPortNameMgr"
     4120)
     4121)
     4122dt (MLText
     4123uid 1768,0
     4124va (VaSet
     4125font "Courier New,8,0"
     4126)
     4127xt "2000,51200,35000,52000"
     4128st "DCM_PS_status         : IN     std_logic_vector (7 downto 0) ;
     4129"
     4130)
     4131thePort (LogicalPort
     4132decl (Decl
     4133n "DCM_PS_status"
     4134t "std_logic_vector"
     4135b "(7 downto 0)"
     4136o 33
     4137suid 71,0
     4138)
     4139)
     4140)
     4141*219 (CptPort
     4142uid 1769,0
     4143ps "OnEdgeStrategy"
     4144shape (Triangle
     4145uid 1770,0
     4146ro 90
     4147va (VaSet
     4148vasetType 1
     4149fg "0,65535,0"
     4150)
     4151xt "36250,47625,37000,48375"
     4152)
     4153tg (CPTG
     4154uid 1771,0
     4155ps "CptPortTextPlaceStrategy"
     4156stg "VerticalLayoutStrategy"
     4157f (Text
     4158uid 1772,0
     4159va (VaSet
     4160)
     4161xt "38000,47500,46900,48500"
     4162st "TRG_GEN_div : (15:0)"
     4163blo "38000,48300"
     4164tm "CptPortNameMgr"
     4165)
     4166)
     4167dt (MLText
     4168uid 1773,0
     4169va (VaSet
     4170font "Courier New,8,0"
     4171)
     4172xt "2000,52800,35500,53600"
     4173st "TRG_GEN_div           : IN     std_logic_vector (15 downto 0) ;
     4174"
     4175)
     4176thePort (LogicalPort
     4177decl (Decl
     4178n "TRG_GEN_div"
     4179t "std_logic_vector"
     4180b "(15 downto 0)"
     4181posAdd 0
     4182o 35
     4183suid 72,0
     4184)
     4185)
     4186)
     4187*220 (CptPort
     4188uid 1774,0
     4189ps "OnEdgeStrategy"
     4190shape (Triangle
     4191uid 1775,0
     4192ro 90
     4193va (VaSet
     4194vasetType 1
     4195fg "0,65535,0"
     4196)
     4197xt "36250,48625,37000,49375"
     4198)
     4199tg (CPTG
     4200uid 1776,0
     4201ps "CptPortTextPlaceStrategy"
     4202stg "VerticalLayoutStrategy"
     4203f (Text
     4204uid 1777,0
     4205va (VaSet
     4206)
     4207xt "38000,48500,46400,49500"
     4208st "TRG_GEN_no : (15:0)"
     4209blo "38000,49300"
     4210tm "CptPortNameMgr"
     4211)
     4212)
     4213dt (MLText
     4214uid 1778,0
     4215va (VaSet
     4216font "Courier New,8,0"
     4217)
     4218xt "2000,52000,35500,52800"
     4219st "TRG_GEN_no            : IN     std_logic_vector (15 downto 0) ;
     4220"
     4221)
     4222thePort (LogicalPort
     4223decl (Decl
     4224n "TRG_GEN_no"
     4225t "std_logic_vector"
     4226b "(15 downto 0)"
     4227o 34
     4228suid 73,0
     4229)
     4230)
     4231)
     4232*221 (CptPort
     4233uid 1810,0
     4234ps "OnEdgeStrategy"
     4235shape (Triangle
     4236uid 1811,0
     4237ro 90
     4238va (VaSet
     4239vasetType 1
     4240fg "0,65535,0"
     4241)
     4242xt "36250,49625,37000,50375"
     4243)
     4244tg (CPTG
     4245uid 1812,0
     4246ps "CptPortTextPlaceStrategy"
     4247stg "VerticalLayoutStrategy"
     4248f (Text
     4249uid 1813,0
     4250va (VaSet
     4251)
     4252xt "38000,49500,42600,50500"
     4253st "dna : (63:0)"
     4254blo "38000,50300"
     4255tm "CptPortNameMgr"
     4256)
     4257)
     4258dt (MLText
     4259uid 1814,0
     4260va (VaSet
     4261font "Courier New,8,0"
     4262)
     4263xt "2000,53600,35500,56800"
     4264st "--
     4265
     4266-- EVT HEADER - part 5
     4267dna                   : IN     std_logic_vector (63 downto 0) ;
     4268"
     4269)
     4270thePort (LogicalPort
     4271decl (Decl
     4272n "dna"
     4273t "std_logic_vector"
     4274b "(63 downto 0)"
     4275prec "--
     4276
     4277-- EVT HEADER - part 5"
     4278preAdd 0
     4279posAdd 0
    35644280o 36
    3565 suid 63,0
     4281suid 74,0
     4282)
     4283)
     4284)
     4285*222 (CptPort
     4286uid 1842,0
     4287ps "OnEdgeStrategy"
     4288shape (Triangle
     4289uid 1843,0
     4290ro 90
     4291va (VaSet
     4292vasetType 1
     4293fg "0,65535,0"
     4294)
     4295xt "36250,50625,37000,51375"
     4296)
     4297tg (CPTG
     4298uid 1844,0
     4299ps "CptPortTextPlaceStrategy"
     4300stg "VerticalLayoutStrategy"
     4301f (Text
     4302uid 1845,0
     4303va (VaSet
     4304)
     4305xt "38000,50500,45600,51500"
     4306st "timer_value : (31:0)"
     4307blo "38000,51300"
     4308tm "CptPortNameMgr"
     4309)
     4310)
     4311dt (MLText
     4312uid 1846,0
     4313va (VaSet
     4314font "Courier New,8,0"
     4315)
     4316xt "2000,56800,48500,60000"
     4317st "--
     4318
     4319-- EVT HEADER - part 6
     4320timer_value           : IN     std_logic_vector (31 downto 0) ; -- time in units of 100us
     4321"
     4322)
     4323thePort (LogicalPort
     4324decl (Decl
     4325n "timer_value"
     4326t "std_logic_vector"
     4327b "(31 downto 0)"
     4328prec "--
     4329
     4330-- EVT HEADER - part 6"
     4331eolc "-- time in units of 100us"
     4332preAdd 0
     4333posAdd 0
     4334o 37
     4335suid 75,0
    35664336)
    35674337)
    … …  
    35764346lineWidth 2
    35774347)
    3578 xt "37000,1000,67000,40000"
     4348xt "37000,1000,67000,52000"
    35794349)
    35804350oxt "37000,1000,51000,21000"
    … …  
    36024372)
    36034373)
    3604 gi *190 (GenericInterface
     4374gi *223 (GenericInterface
    36054375uid 13,0
    36064376ps "CenterOffsetStrategy"
    … …  
    36354405)
    36364406)
    3637 *191 (Grouping
     4407*224 (Grouping
    36384408uid 16,0
    36394409optionalChildren [
    3640 *192 (CommentText
     4410*225 (CommentText
    36414411uid 18,0
    36424412shape (Rectangle
    … …  
    36694439titleBlock 1
    36704440)
    3671 *193 (CommentText
     4441*226 (CommentText
    36724442uid 21,0
    36734443shape (Rectangle
    … …  
    37004470titleBlock 1
    37014471)
    3702 *194 (CommentText
     4472*227 (CommentText
    37034473uid 24,0
    37044474shape (Rectangle
    … …  
    37314501titleBlock 1
    37324502)
    3733 *195 (CommentText
     4503*228 (CommentText
    37344504uid 27,0
    37354505shape (Rectangle
    … …  
    37624532titleBlock 1
    37634533)
    3764 *196 (CommentText
     4534*229 (CommentText
    37654535uid 30,0
    37664536shape (Rectangle
    … …  
    37924562titleBlock 1
    37934563)
    3794 *197 (CommentText
     4564*230 (CommentText
    37954565uid 33,0
    37964566shape (Rectangle
    … …  
    38234593titleBlock 1
    38244594)
    3825 *198 (CommentText
     4595*231 (CommentText
    38264596uid 36,0
    38274597shape (Rectangle
    … …  
    38544624titleBlock 1
    38554625)
    3856 *199 (CommentText
     4626*232 (CommentText
    38574627uid 39,0
    38584628shape (Rectangle
    … …  
    38854655titleBlock 1
    38864656)
    3887 *200 (CommentText
     4657*233 (CommentText
    38884658uid 42,0
    38894659shape (Rectangle
    … …  
    39164686titleBlock 1
    39174687)
    3918 *201 (CommentText
     4688*234 (CommentText
    39194689uid 45,0
    39204690shape (Rectangle
    … …  
    39604730oxt "14000,66000,55000,71000"
    39614731)
    3962 *202 (CommentText
     4732*235 (CommentText
    39634733uid 103,0
    39644734shape (Rectangle
    … …  
    40034773color "26368,26368,26368"
    40044774)
    4005 packageList *203 (PackageList
     4775packageList *236 (PackageList
    40064776uid 131,0
    40074777stg "VerticalLayoutStrategy"
    40084778textVec [
    4009 *204 (Text
     4779*237 (Text
    40104780uid 132,0
    40114781va (VaSet
    … …  
    40164786blo "0,1800"
    40174787)
    4018 *205 (MLText
     4788*238 (MLText
    40194789uid 133,0
    40204790va (VaSet
    … …  
    41174887)
    41184888)
    4119 gi *206 (GenericInterface
     4889gi *239 (GenericInterface
    41204890ps "CenterOffsetStrategy"
    41214891matrix (Matrix
    … …  
    42144984)
    42154985)
    4216 DeclarativeBlock *207 (SymDeclBlock
     4986DeclarativeBlock *240 (SymDeclBlock
    42174987uid 1,0
    42184988stg "SymDeclLayoutStrategy"
    … …  
    42405010font "Arial,8,1"
    42415011)
    4242 xt "0,56000,2400,57000"
     5012xt "0,80000,2400,81000"
    42435013st "User:"
    4244 blo "0,56800"
     5014blo "0,80800"
    42455015)
    42465016internalLabel (Text
    … …  
    42595029font "Courier New,8,0"
    42605030)
    4261 xt "2000,57000,2000,57000"
     5031xt "2000,81000,2000,81000"
    42625032tm "SyDeclarativeTextMgr"
    42635033)
    … …  
    42725042)
    42735043)
    4274 lastUid 1591,0
     5044lastUid 1850,0
    42755045activeModelName "Symbol:CDM"
    42765046)

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/phase_shifter/symbol.sb

    r10129 r10155  
    2727ldm (LogicalDM
    2828ordering 1
    29 suid 15,0
     29suid 17,0
    3030usingSuid 1
    3131emptyRow *1 (LEmptyRow
    … …  
    144144n "LOCKED"
    145145t "std_logic"
     146eolc "-- when is this going high?"
    146147preAdd 0
    147148posAdd 0
    … …  
    189190preAdd 0
    190191posAdd 0
    191 o 10
     192o 11
    192193suid 10,0
    193194i "'0'"
    … …  
    204205preAdd 0
    205206posAdd 0
    206 o 11
     207o 12
    207208suid 11,0
    208209i "'0'"
    … …  
    220221preAdd 0
    221222posAdd 0
    222 o 12
     223o 13
    223224suid 12,0
    224225i "(OTHERS => '0')"
    … …  
    231232m 1
    232233decl (Decl
    233 n "DCM_locked"
    234 t "std_logic"
    235 preAdd 0
    236 posAdd 0
    237 o 13
    238 suid 13,0
    239 )
    240 )
    241 uid 148,0
     234n "rst"
     235t "std_logic"
     236eolc "--asynch in of DCM"
     237posAdd 0
     238o 2
     239suid 15,0
     240i "'0'"
     241)
     242)
     243uid 286,0
    242244)
    243245*26 (LogPort
    244246port (LogicalPort
    245247decl (Decl
    246 n "rst"
    247 t "std_logic"
    248 eolc "--asynch in of DCM"
    249 posAdd 0
    250 o 2
    251 suid 15,0
    252 )
    253 )
    254 uid 286,0
     248n "reset_DCM"
     249t "std_logic"
     250eolc "-- asynch in: orders us, to reset the DCM"
     251posAdd 0
     252o 10
     253suid 17,0
     254)
     255)
     256uid 369,0
    255257)
    256258]
    … …  
    374376pos 11
    375377dimension 20
    376 uid 149,0
     378uid 287,0
    377379)
    378380*44 (MRCItem
    … …  
    380382pos 12
    381383dimension 20
    382 uid 287,0
     384uid 370,0
    383385)
    384386]
    … …  
    651653(vvPair
    652654variable "date"
    653 value "04.02.2011"
     655value "12.02.2011"
    654656)
    655657(vvPair
    656658variable "day"
    657 value "Fr"
     659value "Sa"
    658660)
    659661(vvPair
    660662variable "day_long"
    661 value "Freitag"
     663value "Samstag"
    662664)
    663665(vvPair
    664666variable "dd"
    665 value "04"
     667value "12"
    666668)
    667669(vvPair
    … …  
    799801(vvPair
    800802variable "time"
    801 value "11:34:15"
     803value "13:16:20"
    802804)
    803805(vvPair
    … …  
    889891fg "0,65535,0"
    890892)
    891 xt "63000,8625,63750,9375"
     893xt "65000,8625,65750,9375"
    892894)
    893895tg (CPTG
    … …  
    899901va (VaSet
    900902)
    901 xt "59100,8500,62000,9500"
     903xt "61100,8500,64000,9500"
    902904st "PSCLK"
    903905ju 2
    904 blo "62000,9300"
     906blo "64000,9300"
    905907tm "CptPortNameMgr"
    906908)
    … …  
    939941fg "0,65535,0"
    940942)
    941 xt "63000,10625,63750,11375"
     943xt "65000,10625,65750,11375"
    942944)
    943945tg (CPTG
    … …  
    949951va (VaSet
    950952)
    951 xt "59500,10500,62000,11500"
     953xt "61500,10500,64000,11500"
    952954st "PSEN"
    953955ju 2
    954 blo "62000,11300"
     956blo "64000,11300"
    955957tm "CptPortNameMgr"
    956958)
    … …  
    988990fg "0,65535,0"
    989991)
    990 xt "63000,12625,63750,13375"
     992xt "65000,12625,65750,13375"
    991993)
    992994tg (CPTG
    … …  
    9981000va (VaSet
    9991001)
    1000 xt "57500,12500,62000,13500"
     1002xt "59500,12500,64000,13500"
    10011003st "PSINCDEC"
    10021004ju 2
    1003 blo "62000,13300"
     1005blo "64000,13300"
    10041006tm "CptPortNameMgr"
    10051007)
    … …  
    11061108font "Courier New,8,0"
    11071109)
    1108 xt "2000,13600,20000,14400"
    1109 st "LOCKED      : IN     std_logic  ;
     1110xt "2000,13600,34500,14400"
     1111st "LOCKED      : IN     std_logic  ; -- when is this going high?
    11101112"
    11111113)
    … …  
    11141116n "LOCKED"
    11151117t "std_logic"
     1118eolc "-- when is this going high?"
    11161119preAdd 0
    11171120posAdd 0
    … …  
    12261229fg "0,65535,0"
    12271230)
    1228 xt "63000,14625,63750,15375"
     1231xt "65000,14625,65750,15375"
    12291232)
    12301233tg (CPTG
    … …  
    12361239va (VaSet
    12371240)
    1238 xt "59100,14500,62000,15500"
     1241xt "61100,14500,64000,15500"
    12391242st "shifting"
    12401243ju 2
    1241 blo "62000,15300"
     1244blo "64000,15300"
    12421245tm "CptPortNameMgr"
    12431246)
    … …  
    12481251font "Courier New,8,0"
    12491252)
    1250 xt "2000,16800,33500,18400"
     1253xt "2000,17600,33500,19200"
    12511254st "-- status:
    12521255shifting    : OUT    std_logic                     := '0' ;
    … …  
    12611264preAdd 0
    12621265posAdd 0
    1263 o 10
     1266o 11
    12641267suid 10,0
    12651268i "'0'"
    … …  
    12771280fg "0,65535,0"
    12781281)
    1279 xt "63000,16625,63750,17375"
     1282xt "65000,16625,65750,17375"
    12801283)
    12811284tg (CPTG
    … …  
    12871290va (VaSet
    12881291)
    1289 xt "59800,16500,62000,17500"
     1292xt "61800,16500,64000,17500"
    12901293st "ready"
    12911294ju 2
    1292 blo "62000,17300"
     1295blo "64000,17300"
    12931296tm "CptPortNameMgr"
    12941297)
    … …  
    12991302font "Courier New,8,0"
    13001303)
    1301 xt "2000,18400,33500,19200"
     1304xt "2000,19200,33500,20000"
    13021305st "ready       : OUT    std_logic                     := '0' ;
    13031306"
    … …  
    13101313preAdd 0
    13111314posAdd 0
    1312 o 11
     1315o 12
    13131316suid 11,0
    13141317i "'0'"
    … …  
    13261329fg "0,65535,0"
    13271330)
    1328 xt "63000,18625,63750,19375"
     1331xt "65000,18625,65750,19375"
    13291332)
    13301333tg (CPTG
    … …  
    13361339va (VaSet
    13371340)
    1338 xt "59800,18500,62000,19500"
     1341xt "61800,18500,64000,19500"
    13391342st "offset"
    13401343ju 2
    1341 blo "62000,19300"
     1344blo "64000,19300"
    13421345tm "CptPortNameMgr"
    13431346)
    … …  
    13481351font "Courier New,8,0"
    13491352)
    1350 xt "2000,19200,39500,20000"
    1351 st "offset      : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ;
     1353xt "2000,20000,38500,20800"
     1354st "offset      : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0')
    13521355"
    13531356)
    … …  
    13601363preAdd 0
    13611364posAdd 0
    1362 o 12
     1365o 13
    13631366suid 12,0
    13641367i "(OTHERS => '0')"
    … …  
    13661369)
    13671370)
    1368 *89 (CptPort
    1369 uid 108,0
    1370 ps "OnEdgeStrategy"
    1371 shape (Triangle
    1372 uid 109,0
    1373 ro 90
    1374 va (VaSet
    1375 vasetType 1
    1376 fg "0,65535,0"
    1377 )
    1378 xt "63000,20625,63750,21375"
    1379 )
    1380 tg (CPTG
    1381 uid 110,0
    1382 ps "CptPortTextPlaceStrategy"
    1383 stg "RightVerticalLayoutStrategy"
    1384 f (Text
    1385 uid 111,0
    1386 va (VaSet
    1387 )
    1388 xt "56800,20500,62000,21500"
    1389 st "DCM_locked"
    1390 ju 2
    1391 blo "62000,21300"
    1392 tm "CptPortNameMgr"
    1393 )
    1394 )
    1395 dt (MLText
    1396 uid 112,0
    1397 va (VaSet
    1398 font "Courier New,8,0"
    1399 )
    1400 xt "2000,20000,19000,20800"
    1401 st "DCM_locked  : OUT    std_logic
    1402 "
    1403 )
    1404 thePort (LogicalPort
    1405 m 1
    1406 decl (Decl
    1407 n "DCM_locked"
    1408 t "std_logic"
    1409 preAdd 0
    1410 posAdd 0
    1411 o 13
    1412 suid 13,0
    1413 )
    1414 )
    1415 )
    1416 *90 (CommentText
     1371*89 (CommentText
    14171372uid 121,0
    14181373ps "EdgeToEdgeStrategy"
    … …  
    14451400excludeCommentLeader 1
    14461401)
    1447 *91 (CptPort
     1402*90 (CptPort
    14481403uid 281,0
    14491404ps "OnEdgeStrategy"
    14501405shape (Triangle
    1451 uid 282,0
    1452 ro 90
     1406uid 394,0
     1407ro 270
    14531408va (VaSet
    14541409vasetType 1
    … …  
    14761431font "Courier New,8,0"
    14771432)
    1478 xt "2000,8800,30000,9600"
    1479 st "rst         : IN     std_logic ; --asynch in of DCM
     1433xt "2000,8800,43000,9600"
     1434st "rst         : OUT    std_logic                     := '0' ; --asynch in of DCM
    14801435"
    14811436)
    14821437thePort (LogicalPort
     1438m 1
    14831439decl (Decl
    14841440n "rst"
    … …  
    14881444o 2
    14891445suid 15,0
     1446i "'0'"
     1447)
     1448)
     1449)
     1450*91 (CptPort
     1451uid 362,0
     1452ps "OnEdgeStrategy"
     1453shape (Triangle
     1454uid 363,0
     1455ro 90
     1456va (VaSet
     1457vasetType 1
     1458fg "0,65535,0"
     1459)
     1460xt "49250,21625,50000,22375"
     1461)
     1462tg (CPTG
     1463uid 364,0
     1464ps "CptPortTextPlaceStrategy"
     1465stg "VerticalLayoutStrategy"
     1466f (Text
     1467uid 365,0
     1468va (VaSet
     1469)
     1470xt "51000,21500,55400,22500"
     1471st "reset_DCM"
     1472blo "51000,22300"
     1473tm "CptPortNameMgr"
     1474)
     1475)
     1476dt (MLText
     1477uid 366,0
     1478va (VaSet
     1479font "Courier New,8,0"
     1480)
     1481xt "2000,16800,41500,17600"
     1482st "reset_DCM   : IN     std_logic  ; -- asynch in: orders us, to reset the DCM
     1483"
     1484)
     1485thePort (LogicalPort
     1486decl (Decl
     1487n "reset_DCM"
     1488t "std_logic"
     1489eolc "-- asynch in: orders us, to reset the DCM"
     1490posAdd 0
     1491o 10
     1492suid 17,0
    14901493)
    14911494)
    … …  
    15001503lineWidth 2
    15011504)
    1502 xt "50000,7000,63000,25000"
    1503 )
     1505xt "50000,7000,65000,25000"
     1506)
     1507oxt "50000,7000,63000,25000"
    15041508biTextGroup (BiTextGroup
    15051509uid 10,0
    … …  
    21892193)
    21902194)
    2191 lastUid 333,0
     2195lastUid 394,0
    21922196activeModelName "Symbol:CDM"
    21932197)

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/trigger_counter/symbol.sb

    r9912 r10155  
    7272n "trigger_id"
    7373t "std_logic_vector"
    74 b "(47 downto 0)"
     74b "(31 downto 0)"
    7575preAdd 0
    7676posAdd 0
    … …  
    404404(vvPair
    405405variable "HDLDir"
    406 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hdl"
     406value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
    407407)
    408408(vvPair
    409409variable "HDSDir"
    410 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds"
     410value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
    411411)
    412412(vvPair
    413413variable "SideDataDesignDir"
    414 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb.info"
     414value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb.info"
    415415)
    416416(vvPair
    417417variable "SideDataUserDir"
    418 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb.user"
     418value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb.user"
    419419)
    420420(vvPair
    421421variable "SourceDir"
    422 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds"
     422value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
    423423)
    424424(vvPair
    … …  
    436436(vvPair
    437437variable "d"
    438 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter"
     438value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter"
    439439)
    440440(vvPair
    441441variable "d_logical"
    442 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter"
     442value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter"
    443443)
    444444(vvPair
    445445variable "date"
    446 value "22.06.2010"
     446value "15.02.2011"
    447447)
    448448(vvPair
    … …  
    456456(vvPair
    457457variable "dd"
    458 value "22"
     458value "15"
    459459)
    460460(vvPair
    … …  
    484484(vvPair
    485485variable "host"
    486 value "TU-CC4900F8C7D2"
     486value "E5B-LABOR6"
    487487)
    488488(vvPair
    … …  
    495495)
    496496(vvPair
     497variable "library_downstream_HdsLintPlugin"
     498value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
     499)
     500(vvPair
    497501variable "library_downstream_ISEPARInvoke"
    498502value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
    … …  
    512516(vvPair
    513517variable "mm"
    514 value "06"
     518value "02"
    515519)
    516520(vvPair
    … …  
    520524(vvPair
    521525variable "month"
    522 value "Jun"
     526value "Feb"
    523527)
    524528(vvPair
    525529variable "month_long"
    526 value "Juni"
     530value "Februar"
    527531)
    528532(vvPair
    529533variable "p"
    530 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb"
     534value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb"
    531535)
    532536(vvPair
    533537variable "p_logical"
    534 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb"
     538value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb"
    535539)
    536540(vvPair
    … …  
    556560(vvPair
    557561variable "task_ModelSimPath"
    558 value "<TBD>"
     562value "C:\\modeltech_6.6a\\win32"
    559563)
    560564(vvPair
    … …  
    588592(vvPair
    589593variable "time"
    590 value "10:22:01"
     594value "09:26:17"
    591595)
    592596(vvPair
    … …  
    608612(vvPair
    609613variable "year"
    610 value "2010"
     614value "2011"
    611615)
    612616(vvPair
    613617variable "yy"
    614 value "10"
     618value "11"
    615619)
    616620]
    … …  
    655659)
    656660xt "2000,9000,30000,9800"
    657 st "trigger_id : OUT    std_logic_vector (47 downto 0) ;"
     661st "trigger_id : OUT    std_logic_vector (31 downto 0) ;
     662"
    658663)
    659664thePort (LogicalPort
    … …  
    663668n "trigger_id"
    664669t "std_logic_vector"
    665 b "(47 downto 0)"
     670b "(31 downto 0)"
    666671preAdd 0
    667672posAdd 0
    … …  
    703708)
    704709xt "2000,9800,19500,10600"
    705 st "trigger    : IN     std_logic  ;"
     710st "trigger    : IN     std_logic  ;
     711"
    706712)
    707713thePort (LogicalPort
    … …  
    749755)
    750756xt "2000,10600,18500,11400"
    751 st "clk        : IN     std_logic "
     757st "clk        : IN     std_logic
     758"
    752759)
    753760thePort (LogicalPort
    … …  
    844851bg "0,0,32768"
    845852)
    846 xt "36200,20000,44500,21000"
     853xt "36200,20000,45700,21000"
    847854st "
    848855by %user on %dd %month %year
    … …  
    14601467)
    14611468)
    1462 lastUid 177,0
     1469lastUid 200,0
    14631470activeModelName "Symbol:CDM"
    14641471)

  • firmware/FAD/doc/memory_manager.tex

    r10150 r10155  
    1941940x200A  & trg pos 3     & trg pos 2     & trg pos 1     & trg pos 0     \\
    1951950x200B  & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\
    196 0x200C  & data adc3     & data adc2     & data adc1     & data adc0     \\
     1960x200C  & -fill- & -fill- & -fill- & -fill-  \\
     1970x200D  & data adc3     & data adc2     & data adc1     & data adc0     \\
    1971980x20..  &&&& ... \\
    198 0x206F  & data adc3     & data adc2     & data adc1     & data adc0     \\
     1990x2070  & data adc3     & data adc2     & data adc1     & data adc0     \\
    199200\hline
    2002010x20..  &&&& ... \\
    … …  
    2032040x23??  & trg pos 3     & trg pos 2     & trg pos 1     & trg pos 0     \\
    2042050x23??  & ROI 3         & ROI 2         & ROI 1         & ROI 0 \\
     2060x23??  & -fill- & -fill- & -fill- & -fill-  \\
    2052070x23??  & data adc3     & data adc2     & data adc1     & data adc0     \\
    2062080x23..  &&&& ... \\
    … …  
    318320        unsigned short start_cell;
    319321        unsigned short roi;
     322        unsigned short filling;
    320323        unsigned short adc_data[];
    321324}  __attribute__((__packed__)) PCHANNEL;
    … …  
    327330\end{verbatim}
    328331
     332\subsection{mem manager calculations}
     333
     334Memory manager knows the size of FADs internal data RAM. This is implemented as VHDL-Generics called {\tt RAM_ADD_WIDTH_64B}
     335and {\tt RAM_ADD_WIDTH_16B}. Since word width is 64bit on the input side and 16bit on the outpt two generics are used.
     336Currently the values are:
     337\begin{table}[htbp]
     338\begin{tabular}{ll}
     339RAM_ADD_WIDTH_64B & 12 \\
     340RAM_ADD_WIDTH_16B & 14 \\
     341\end {tabular}
     342\caption{values of RAM width}
     343\label{RAM_GENERICS}
     344\end{table}
     345
     346Which results in
     347\begin{equation}
     348\mathtt{RAM size} = 2^{12} \cdot 8 byte= 2^14 * 2 byte = 32768 byte .
     349\end{equation}
     350
     351Now the memory manager is able to calculate the number of Events, fitting into this RAM.
     352
     353The number of samples of each channel beeing digitized is called region of interest(ROI). Since the ROI of each of the 36 input channel may be defined independently, but the RAM is organized in 64bit words on the input side, the memory manager needs to calculate the effective ROI of each channel first. The DRS Chips are digitized in a parallel manner, but their 9 channels are digitized serially. So first each DRS is ordered to output its channel 0 data, until as many samples are digitized as the maximum of all channel 0 ROIs is.
     354
     355In the states called MAX_ROI0..2 the array containing the maxima of each group of channels is calculated.
     356In addition the so called channel size array is calculated. This is the number of 16bit words which is needed to store a group of
     357channels in the W5300 FIFO. The header is included into the group of channels 0, while the package footer is included into group of channels 9.
     358
     359In the next state called FIFO CALC. Here
     360
     361
    329362
    330363\end{document}
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