Changeset 10156
- Timestamp:
- 02/16/11 08:02:46 (14 years ago)
- Location:
- firmware/FAD
- Files:
-
- 3 edited
-
FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (modified) (1 diff)
-
FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd (modified) (3 diffs)
-
doc/memory_manager.tex (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10155 r10156 55 55 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"02"; 56 56 constant PACKAGE_HEADER_LENGTH : integer := 22; 57 constant PACKAGE_HEADER_ZEROS : integer := 6; 57 58 constant PACKAGE_END_LENGTH : integer := 2; -- CRC and END-Flag 59 constant PACKAGE_END_ZEROS : integer := 2; 58 60 constant CHANNEL_HEADER_SIZE : integer := 3; 61 constant NUMBER_OF_DRS : integer := 4; 59 62 60 63 constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd
r10155 r10156 166 166 channel_id <= 0; 167 167 fifo_package_size_ram <= (others => 0); 168 fifo_package_size_ram (0) <= PACKAGE_HEADER_LENGTH + 6;168 fifo_package_size_ram (0) <= PACKAGE_HEADER_LENGTH + PACKAGE_HEADER_ZEROS; 169 169 event_size_ram <= 0; 170 170 event_size_ram_64b <= 0; … … 176 176 if (package_index < number_of_packages) then 177 177 if (channel_index < fifo_channels_array (package_index)) then 178 fifo_package_size_ram (package_index) <= fifo_package_size_ram (package_index) + ((roi_max_array (channel_id) + 3) * 4); 178 fifo_package_size_ram (package_index) <= 179 fifo_package_size_ram (package_index) + ((roi_max_array (channel_id) + CHANNEL_HEADER_SIZE) * NUMBER_OF_DRS); 179 180 channel_index <= channel_index + 1; 180 181 channel_id <= channel_id + 1; … … 185 186 end if; 186 187 else 187 fifo_package_size_ram (package_index - 1) <= fifo_package_size_ram (package_index - 1) + 4;188 event_size_ram <= event_size_ram + 4; -- Size of Event in RAM (16 Bit), + CRC + Endflag + 2 Spare188 fifo_package_size_ram (package_index - 1) <= fifo_package_size_ram (package_index - 1) + PACKAGE_END_LENGTH + PACKAGE_END_ZEROS; 189 event_size_ram <= event_size_ram + PACKAGE_END_LENGTH + PACKAGE_END_ZEROS; 189 190 state_mm <= RAM_CALC1; 190 191 end if; -
firmware/FAD/doc/memory_manager.tex
r10155 r10156 179 179 \begin{tabular}{||l||l|l|l|l||} 180 180 \hline 181 address & word 3 & word 2 & word 1 & word 0\\182 \hline 183 0x2000 & 12bit status + PLLLOCK & version & length & 0xFB01 \\184 0x2001 & 0xT1T0 & 0xT3T2 & 0xT5T4 & 0x00T6\\185 0x2002 & REFCLK cntr 10 & REFCLK cntr 32 & EVT cntr 10 & EVT cntr 32\\186 0x2003 & TRG-GEN-DIV & TRG-GEN-No& DCM-PS-STATUS & 0x0(cid)8(bid) \\187 0x2004 & DNA10 & DNA32 & DNA54 & 0x00DNA6\\188 0x2005 & more status & more status & time10 & time32\\189 0x2006 & Temp 3 & Temp 2 & Temp 1 & Temp 0\\190 0x2007 & DAC 3 & DAC 2 & DAC 1 & DAC 0\\191 0x2008 & DAC 7 & DAC 6 & DAC 5 & DAC 4\\192 \hline 193 0x2009 & 0x0030 & 0x0020 & 0x0010 & 0x0000\\194 0x200A & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0\\195 0x200B & ROI 3 & ROI 2 & ROI 1 & ROI 0\\196 0x200C & -fill- & -fill- & -fill- & -fill-\\197 0x200D & data adc3 & data adc2 & data adc1 & data adc0\\198 0x20.. & &&& ...\\199 0x2070 & data adc3 & data adc2 & data adc1 & data adc0\\200 \hline 201 0x20.. & &&& ...\\202 \hline 203 0x23?? & 0x0039 & 0x0029 & 0x0019 & 0x0009\\204 0x23?? & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0\\205 0x23?? & ROI 3 & ROI 2 & ROI 1 & ROI 0\\206 0x23?? & -fill- & -fill- & -fill- & -fill-\\207 0x23?? & data adc3 & data adc2 & data adc1 & data adc0\\208 0x23.. & &&& ...\\209 0x23?? & data adc3 & data adc2 & data adc1 & data adc0\\210 \hline 211 0x23?? & 0x0000 & 0x0000 & 0x04FE & 0x4242\\181 address & word 3 & word 2 & word 1 & word 0 \\ 182 \hline 183 0x2000 & 12bit status + PLLLOCK & version & length & 0xFB01 \\ 184 0x2001 & 0xT1T0 & 0xT3T2 & 0xT5T4 & 0x00T6 \\ 185 0x2002 & REFCLK cntr 10 & REFCLK cntr 32 & EVT cntr 10 & EVT cntr 32 \\ 186 0x2003 & TRG-GEN-DIV & TRG-GEN-No & DCM-PS-STATUS & 0x0(cid)8(bid) \\ 187 0x2004 & DNA10 & DNA32 & DNA54 & 0x00DNA6 \\ 188 0x2005 & more status & more status & time10 & time32 \\ 189 0x2006 & Temp 3 & Temp 2 & Temp 1 & Temp 0 \\ 190 0x2007 & DAC 3 & DAC 2 & DAC 1 & DAC 0 \\ 191 0x2008 & DAC 7 & DAC 6 & DAC 5 & DAC 4 \\ 192 \hline 193 0x2009 & 0x0030 & 0x0020 & 0x0010 & 0x0000 \\ 194 0x200A & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 \\ 195 0x200B & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\ 196 0x200C & -fill- & -fill- & -fill- & -fill- \\ 197 0x200D & data adc3 & data adc2 & data adc1 & data adc0 \\ 198 0x20.. & ... & ... & ... & ... \\ 199 0x2070 & data adc3 & data adc2 & data adc1 & data adc0 \\ 200 \hline 201 0x20.. & ... & ... & ... & ... \\ 202 \hline 203 0x23?? & 0x0039 & 0x0029 & 0x0019 & 0x0009 \\ 204 0x23?? & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 \\ 205 0x23?? & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\ 206 0x23?? & -fill- & -fill- & -fill- & -fill- \\ 207 0x23?? & data adc3 & data adc2 & data adc1 & data adc0 \\ 208 0x23.. & ... & ... & ... & ... \\ 209 0x23?? & data adc3 & data adc2 & data adc1 & data adc0 \\ 210 \hline 211 0x23?? & 0x0000 & 0x0000 & 0x04FE & 0x4242 \\ 212 212 \hline 213 213 \end {tabular} … … 357 357 channels in the W5300 FIFO. The header is included into the group of channels 0, while the package footer is included into group of channels 9. 358 358 359 In the next state called FIFO CALC. Here 360 361 359 \subsubsection{state: MM CONFIG} 360 Here all local variables are reset to zero. Let me shortly explain the meaning of each of them: 361 \begin{table}[htbp] 362 \begin{tabular}{lll} 363 roi\_max\_array & array (0 to 8) of integer range 0 to 1024 & maximum for each channel group\\ 364 channel\_size & array (0 to 8) of integer range 0 to W5300\_TX\_FIFO\_SIZE & size of each channel group in 16b words \\ 365 fifo\_write\_length & array (0 to 8) of integer range 0 to W5300\_TX\_FIFO\_SIZE & similar ??? \\ 366 fifo\_channels\_array & array (0 to 8) of integer range 0 to 9 & ??? \\ 367 \hline \\ 368 event_size & integer range 0 to RAM\_SIZE\_16B & ???\\ 369 event_size_ram & integer range 0 to RAM\_SIZE\_16B & ???\\ 370 event_size_ram_64b & integer range 0 to RAM\_SIZE\_64B & ??? \\ 371 \end {tabular} 372 \caption{ -no caption- -no label-} 373 %\label{} 374 \end{table} 375 376 The input is only: 377 \begin{table}[htbp] 378 \begin{tabular}{lll} 379 roi\_array & array (0 to 35) of integer range 0 to 1024 & ROI of each channel\\ 380 \end {tabular} 381 \caption{ -no caption- -no label-} 382 %\label{} 383 \end{table} 384 385 \subsubsection{states: MAX ROI\bf{n} and state: FIFO\_CALC} 386 \begin{itemize} 387 \item find maxium in roi\_array for each channel and store it as the maximum roi of each channel group inside roi\_max\_array. 388 \item calculate channel\_size(n) as $sum_{drs=0}^{3} \left( roi_{drs,n} + CHANNEL\_HEADER\_SIZE \right)$. 389 For $n=0$ the size of the package header is added and for $n=8$ the size of the package footer is added to the channel\_size. 390 So channel\_size(n) stores the number of 16bit words, which will be transmitted over ethernet for this particular group of channels n. \\ 391 Note: this is not the number of 16bit words, which will be stored inside the internal data RAM, since this number is defined by the maximum roi of each channel group. 392 \item calculate into how many pieces the package need to be devided. fifo\_write\_length(m) contains a certain sum of channel\_sizes. So again 393 fifo\_write\_length is a size measures in 16bit words, which will actually be transmitted over ethernet. 394 \end{itemize} 395 396 397 \subsubsection{states: RAM\_CALC\bf{n}} 398 Here we need to know how many of these packages will fit into our data RAM. 399 There 362 400 363 401 \end{document}
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