Changeset 10155 for firmware/FAD/doc/memory_manager.tex

Timestamp:

02/15/11 12:07:05 (14 years ago)

Author:

neise

Message:

highly unstable version !!!

File:

• firmware/FAD/doc/memory_manager.tex (modified) (4 diffs)

firmware/FAD/doc/memory_manager.tex

@@ -194 +194 @@
 0x200A  & trg pos 3     & trg pos 2     & trg pos 1     & trg pos 0     \\
 0x200B  & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\
-0x200C  & data adc3     & data adc2     & data adc1     & data adc0     \\
+0x200C  & -fill- & -fill- & -fill- & -fill-  \\
+0x200D  & data adc3     & data adc2     & data adc1     & data adc0     \\
 0x20..  &&&& ... \\
-0x206F  & data adc3     & data adc2     & data adc1     & data adc0     \\
+0x2070  & data adc3     & data adc2     & data adc1     & data adc0     \\
 \hline
 0x20..  &&&& ... \\
@@ -203 +204 @@
 0x23??  & trg pos 3     & trg pos 2     & trg pos 1     & trg pos 0     \\
 0x23??  & ROI 3         & ROI 2         & ROI 1         & ROI 0 \\
+0x23??  & -fill- & -fill- & -fill- & -fill-  \\
 0x23??  & data adc3     & data adc2     & data adc1     & data adc0     \\
 0x23..  &&&& ... \\
@@ -318 +320 @@
         unsigned short start_cell;
         unsigned short roi;
+        unsigned short filling;
         unsigned short adc_data[];
 }  __attribute__((__packed__)) PCHANNEL;
@@ -327 +330 @@
 \end{verbatim} 
 
+\subsection{mem manager calculations}
+
+Memory manager knows the size of FADs internal data RAM. This is implemented as VHDL-Generics called {\tt RAM_ADD_WIDTH_64B}
+and {\tt RAM_ADD_WIDTH_16B}. Since word width is 64bit on the input side and 16bit on the outpt two generics are used.
+Currently the values are:
+\begin{table}[htbp]
+\begin{tabular}{ll} 
+RAM_ADD_WIDTH_64B & 12 \\
+RAM_ADD_WIDTH_16B & 14 \\
+\end {tabular}
+\caption{values of RAM width}
+\label{RAM_GENERICS}
+\end{table}
+
+Which results in 
+\begin{equation}
+\mathtt{RAM size} = 2^{12} \cdot 8 byte= 2^14 * 2 byte = 32768 byte .
+\end{equation}
+
+Now the memory manager is able to calculate the number of Events, fitting into this RAM.
+
+The number of samples of each channel beeing digitized is called region of interest(ROI). Since the ROI of each of the 36 input channel may be defined independently, but the RAM is organized in 64bit words on the input side, the memory manager needs to calculate the effective ROI of each channel first. The DRS Chips are digitized in a parallel manner, but their 9 channels are digitized serially. So first each DRS is ordered to output its channel 0 data, until as many samples are digitized as the maximum of all channel 0 ROIs is.
+
+In the states called MAX_ROI0..2 the array containing the maxima of each group of channels is calculated.
+In addition the so called channel size array is calculated. This is the number of 16bit words which is needed to store a group of 
+channels in the W5300 FIFO. The header is included into the group of channels 0, while the package footer is included into group of channels 9.
+
+In the next state called FIFO CALC. Here 
+
+
 
 \end{document}