Changeset 10150 for firmware/FAD/doc/memory_manager.tex
- Timestamp:
- 02/09/11 11:16:48 (14 years ago)
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- 1 edited
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firmware/FAD/doc/memory_manager.tex (modified) (4 diffs)
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firmware/FAD/doc/memory_manager.tex
r10144 r10150 185 185 0x2002 & REFCLK cntr 10 & REFCLK cntr 32 & EVT cntr 10 & EVT cntr 32 \\ 186 186 0x2003 & TRG-GEN-DIV & TRG-GEN-No & DCM-PS-STATUS & 0x0(cid)8(bid) \\ 187 0x2004 & more status & more status & time10 & time32 \\ 188 0x2005 & Temp 3 & Temp 2 & Temp 1 & Temp 0 \\ 189 0x2006 & DAC 3 & DAC 2 & DAC 1 & DAC 0 \\ 190 0x2007 & DAC 7 & DAC 6 & DAC 5 & DAC 4 \\ 191 \hline 192 0x2007 & 0x0030 & 0x0020 & 0x0010 & 0x0000 \\ 193 0x2008 & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 \\ 194 0x2009 & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\ 195 0x200A & data adc3 & data adc2 & data adc1 & data adc0 \\ 187 0x2004 & DNA10 & DNA32 & DNA54 & 0x00DNA6 \\ 188 0x2005 & more status & more status & time10 & time32 \\ 189 0x2006 & Temp 3 & Temp 2 & Temp 1 & Temp 0 \\ 190 0x2007 & DAC 3 & DAC 2 & DAC 1 & DAC 0 \\ 191 0x2008 & DAC 7 & DAC 6 & DAC 5 & DAC 4 \\ 192 \hline 193 0x2009 & 0x0030 & 0x0020 & 0x0010 & 0x0000 \\ 194 0x200A & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 \\ 195 0x200B & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\ 196 0x200C & data adc3 & data adc2 & data adc1 & data adc0 \\ 196 197 0x20.. &&&& ... \\ 197 0x206 D& data adc3 & data adc2 & data adc1 & data adc0 \\198 0x206F & data adc3 & data adc2 & data adc1 & data adc0 \\ 198 199 \hline 199 200 0x20.. &&&& ... \\ 200 201 \hline 201 0x23 3F& 0x0039 & 0x0029 & 0x0019 & 0x0009 \\202 0x23 40& trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 \\203 0x23 41& ROI 3 & ROI 2 & ROI 1 & ROI 0 \\204 0x23 42& data adc3 & data adc2 & data adc1 & data adc0 \\202 0x23?? & 0x0039 & 0x0029 & 0x0019 & 0x0009 \\ 203 0x23?? & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 \\ 204 0x23?? & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\ 205 0x23?? & data adc3 & data adc2 & data adc1 & data adc0 \\ 205 206 0x23.. &&&& ... \\ 206 0x23 A5& data adc3 & data adc2 & data adc1 & data adc0 \\207 \hline 208 0x23 A6& 0x0000 & 0x0000 & 0x04FE & 0x4242\\207 0x23?? & data adc3 & data adc2 & data adc1 & data adc0 \\ 208 \hline 209 0x23?? & 0x0000 & 0x0000 & 0x04FE & 0x4242\\ 209 210 \hline 210 211 \end {tabular} 211 212 212 \caption{NEW word order of event in Data RAM. 64bit addressing. As of > 08.02.2011} 213 213 \label{new64bitRAM} 214 214 \end{table} 215 215 216 A detailed description is given after, next table.\\ 217 216 218 \newpage 217 219 Which in turn changes the the word order in the 16bit address space like this … … 221 223 address & 16bit word & description \\ 222 224 \hline 223 0x8000 & 0xFB01 & Start Flag - fix value \\225 0x8000 & 0xFB01 & Start Flag - fix value: "FB01" \\ 224 226 0x8001 & 0xllll & package length in 16bit words \\ 225 227 0x8002 & 0xvvvv & version - deduced from SVN revision number \\ 226 0x8003 & 0xsssP & 12 bits for status - TBD - 4 bit showing PLLLCK status \\ \hdashline 228 0x8003 & 0xsssP & 12 bits for status - TBD - 4 bit showing PLLLCK status \\ 229 \hdashline 227 230 0x8004 & 0x00T6 & FTM trigger ID byte 6 : CRC \\ 228 231 0x8005 & 0xT5T4 & ... bytes 5 and 4 : Type 2 and Type 1\\ 229 232 0x8006 & 0xT3T2 & ... bytes 3 and 2 : TRG number high word \\ 230 0x8007 & 0xT1T0 & ... bytes 1 and 0 : TRG number low word \\ \hdashline 233 0x8007 & 0xT1T0 & ... bytes 1 and 0 : TRG number low word \\ 234 \hdashline 231 235 0x8008 & 0xev32 & FAD event counter high word \\ 232 236 0x8009 & 0xev10 & FAD event counter low word -- should be equal to T3T2T1T0\\ 233 237 0x800A & 0xRC32 & REFCLK counter high word \\ 234 0x800B & 0xRC10 & REFCLK counter low word \\ \hdashline 238 0x800B & 0xRC10 & REFCLK counter low word \\ 239 \hdashline 235 240 0x800C & 0x0(cid)8(bid) & Board ID \\ 236 241 0x800D & DCM-PS & status of ADC clock phase shifter , value and locked-bit\\ 237 242 0x800E & TRG-GEN-No& Number of Triggers to generare, when 'trigger continous' issued \\ 238 0x800F & TRG-GEN-DIV& continous trigger generator clock prescaler \\ \hdashline 239 0x8010 & timer32 & timer high word \\ 240 0x8011 & timer10 & timer low word \\ 241 0x8012 & more status1 & reserved for status info; high word \\ 242 0x8013 & more status0 & reserved for status info; low word \\ \hdashline 243 0x8014 & 0xttt0 & temperature sensor next to DRS 0 \\ 244 0x8015 & 0xttt1 & temperature sensor next to DRS 1 \\ 245 0x8016 & 0xttt2 & temperature sensor next to DRS 2 \\ 246 0x8017 & 0xttt3 & temperature sensor next to DRS 3 \\ \hdashline 247 0x8018 & 0xdac0 & setting of DAC channel A \\ 248 0x8019 & 0xdac1 & setting of DAC channel B \\ 249 0x801A & 0xdac2 & setting of DAC channel C \\ 250 0x801B & 0xdac3 & setting of DAC channel D \\ \hdashline 251 0x801C & 0xdac4 & setting of DAC channel E \\ 252 0x801D & 0xdac5 & setting of DAC channel F \\ 253 0x801E & 0xdac6 & setting of DAC channel G \\ 254 0x801F & 0xdac7 & setting of DAC channel H \\ 243 0x800F & TRG-GEN-DIV& continous trigger generator clock prescaler \\ 244 \hdashline 245 0x8010 & 0x00 DNA6 & MSB of DNA \\ 246 0x8011 & DNA54 & ... DNA ... \\ 247 0x8012 & DNA32 & ... DNA ... \\ 248 0x8013 & DNA10 & LSB of DNA \\ 249 \hdashline 250 0x8014 & timer32 & timer high word \\ 251 0x8015 & timer10 & timer low word \\ 252 0x8016 & more status1 & reserved for status info; high word \\ 253 0x8017 & more status0 & reserved for status info; low word \\ 254 \hdashline 255 0x8018 & 0xttt0 & temperature sensor next to DRS 0 \\ 256 0x8019 & 0xttt1 & temperature sensor next to DRS 1 \\ 257 0x801A & 0xttt2 & temperature sensor next to DRS 2 \\ 258 0x801B & 0xttt3 & temperature sensor next to DRS 3 \\ 259 \hdashline 260 0x801C & 0xdac0 & setting of DAC channel A \\ 261 0x801D & 0xdac1 & setting of DAC channel B \\ 262 0x801E & 0xdac2 & setting of DAC channel C \\ 263 0x801F & 0xdac3 & setting of DAC channel D \\ 264 \hdashline 265 0x8020 & 0xdac4 & setting of DAC channel E \\ 266 0x8021 & 0xdac5 & setting of DAC channel F \\ 267 0x8022 & 0xdac6 & setting of DAC channel G \\ 268 0x8023 & 0xdac7 & setting of DAC channel H \\ 255 269 \hline 256 270 0x8... & ... & ...data ... \\ … … 261 275 \label{16bitRAM} 262 276 \end{table} 263 264 277 This new order has several advantages apart from the additional information included. 265 All data may be treated as 64bit aligned. And the data readout process does not have to jump over word during data sending. 278 All data may be treated as 64bit aligned. And the data readout process does not need jump over words during data sending. 279 266 280 267 281 \newpage … … 287 301 unsgined short number_of_triggers_to_generate; 288 302 unsigned short trigger_generator_prescaler; 303 // ------------------------------ 304 unsigned char reserved; 305 unsigned char DNA[7]; // '1' & 55 unique bits of Xilinx DNA 289 306 // ------------------------------ 290 307 unsigned long time;
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