Changeset 10170
- Timestamp:
- 02/22/11 17:10:31 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 2 added
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/dna_gen.vhd
r10155 r10170 32 32 Port ( 33 33 clk : IN STD_LOGIC; 34 start : IN STD_LOGIC;35 34 dna : OUT STD_LOGIC_VECTOR(63 downto 0) := (others => '0'); 36 35 ready : OUT STD_LOGIC := '0' … … 49 48 50 49 signal shift_cntr : INTEGER range 0 to 64 := 0; 50 signal start_sig : std_logic := '0'; 51 51 52 52 begin … … 66 66 begin 67 67 if Falling_edge(clk) then 68 if (start_sig = '0') then 69 start_sig <= '1'; 70 end if; 68 71 case FTU_dna_gen_State is 69 72 when IDLE => … … 71 74 read_sig <= '0'; 72 75 shift_sig <= '0'; 73 if (start = '1') then76 if (start_sig = '1') then 74 77 FTU_dna_gen_State <= READ_DNA; 75 78 else … … 99 102 when DNA_READY => 100 103 ready <= '1'; 104 start_sig <= '0'; 101 105 read_sig <= '0'; 102 106 shift_sig <= '0'; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10155 r10170 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 3:26:28 14.02.20115 -- at - 17:38:00 16.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 76 76 -- Created: 77 77 -- by - dneise.UNKNOWN (E5B-LABOR6) 78 -- at - 1 3:26:28 14.02.201178 -- at - 17:38:00 16.02.2011 79 79 -- 80 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10156 r10170 54 54 constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"01"; 55 55 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"02"; 56 constant PACKAGE_HEADER_LENGTH : integer := 22;57 constant PACKAGE_HEADER_ZEROS : integer := 6;56 constant PACKAGE_HEADER_LENGTH : integer := 36; 57 constant PACKAGE_HEADER_ZEROS : integer := 0; 58 58 constant PACKAGE_END_LENGTH : integer := 2; -- CRC and END-Flag 59 59 constant PACKAGE_END_ZEROS : integer := 2; 60 constant CHANNEL_HEADER_SIZE : integer := 3;60 constant CHANNEL_HEADER_SIZE : integer := 4; 61 61 constant NUMBER_OF_DRS : integer := 4; 62 62 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10155 r10170 1 -- VHDL Entity FACT_FAD_lib.FAD_main.symbol2 --3 -- Created:4 -- by - dneise.UNKNOWN (E5B-LABOR6)5 -- at - 13:26:27 14.02.20116 --7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)8 --9 LIBRARY ieee;10 USE ieee.std_logic_1164.all;11 USE ieee.std_logic_arith.all;12 LIBRARY FACT_FAD_lib;13 USE FACT_FAD_lib.fad_definitions.all;14 15 ENTITY FAD_main IS16 GENERIC(17 RAMADDRWIDTH64b : integer := 1218 );19 PORT(20 CLK : IN std_logic;21 D_T_in : IN std_logic_vector (1 DOWNTO 0);22 SROUT_in_0 : IN std_logic;23 SROUT_in_1 : IN std_logic;24 SROUT_in_2 : IN std_logic;25 SROUT_in_3 : IN std_logic;26 adc_data_array : IN adc_data_array_type;27 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);28 board_id : IN std_logic_vector (3 DOWNTO 0);29 crate_id : IN std_logic_vector (1 DOWNTO 0);30 drs_refclk_in : IN std_logic; -- used to check if DRS REFCLK exsists, if not DENABLE inhibit31 plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked32 trigger : IN std_logic;33 wiz_int : IN std_logic;34 CLK_25_PS : OUT std_logic;35 CLK_50 : OUT std_logic;36 RSRLOAD : OUT std_logic := '0';37 SRCLK : OUT std_logic := '0';38 SRIN_out : OUT std_logic := '0';39 adc_clk_en : OUT std_logic := '0';40 adc_oeb : OUT std_logic := '1';41 additional_flasher_out : OUT std_logic;42 alarm_refclk_too_high : OUT std_logic := '0'; -- default domino wave off43 alarm_refclk_too_low : OUT std_logic := '0'; -- default domino wave off44 amber : OUT std_logic;45 counter_result : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');46 dac_cs : OUT std_logic;47 denable : OUT std_logic := '0'; -- default domino wave off48 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');49 drs_dwrite : OUT std_logic := '1';50 green : OUT std_logic;51 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');52 mosi : OUT std_logic := '0';53 red : OUT std_logic;54 sclk : OUT std_logic;55 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);56 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);57 wiz_cs : OUT std_logic := '1';58 wiz_rd : OUT std_logic := '1';59 wiz_reset : OUT std_logic := '1';60 wiz_wr : OUT std_logic := '1';61 sio : INOUT std_logic;62 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)63 );64 65 -- Declarations66 67 END FAD_main ;68 69 --70 -- VHDL Architecture FACT_FAD_lib.FAD_main.struct71 --72 -- Created:73 -- by - dneise.UNKNOWN (E5B-LABOR6)74 -- at - 13:26:28 14.02.201175 --76 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)77 --78 library ieee;79 use ieee.std_logic_1164.all;80 use IEEE.STD_LOGIC_ARITH.all;81 use ieee.STD_LOGIC_UNSIGNED.all;82 83 library fact_fad_lib;84 use fact_fad_lib.fad_definitions.all;85 86 library UNISIM;87 --use UNISIM.VComponents.all;88 USE IEEE.NUMERIC_STD.all;89 USE IEEE.std_logic_signed.all;90 91 LIBRARY FACT_FAD_lib;92 93 ARCHITECTURE struct OF FAD_main IS94 95 -- Architecture declarations96 97 -- Internal signal declarations98 SIGNAL CLK_25 : std_logic;99 SIGNAL SRCLK1 : std_logic := '0';100 SIGNAL adc_data_array_int : adc_data_array_type;101 SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0);102 SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);103 SIGNAL c_trigger_enable : std_logic := '0';104 SIGNAL c_trigger_mult : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1'); --subject to changes105 SIGNAL config_addr : std_logic_vector(7 DOWNTO 0);106 SIGNAL config_busy : std_logic;107 SIGNAL config_data : std_logic_vector(15 DOWNTO 0);108 SIGNAL config_data_valid : std_logic;109 SIGNAL config_rd_en : std_logic;110 SIGNAL config_ready : std_logic;111 SIGNAL config_ready_cm : std_logic;112 SIGNAL config_ready_spi : std_logic;113 -- --114 SIGNAL config_rw_ack : std_logic := '0';115 -- --116 SIGNAL config_rw_ready : std_logic := '0';117 SIGNAL config_start : std_logic := '0';118 SIGNAL config_start_cm : std_logic;119 SIGNAL config_start_spi : std_logic := '0';120 SIGNAL config_started : std_logic;121 SIGNAL config_started_cu : std_logic := '0';122 SIGNAL config_started_mm : std_logic;123 SIGNAL config_started_spi : std_logic := '0';124 SIGNAL config_wr_en : std_logic;125 SIGNAL dac_array : dac_array_type;126 SIGNAL data_out : std_logic_vector(63 DOWNTO 0);127 SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off128 SIGNAL denable_prim : std_logic := '0'; -- default domino wave off129 SIGNAL din1 : std_logic := '0'; -- default domino wave off130 SIGNAL dout : std_logic;131 SIGNAL dout1 : std_logic;132 SIGNAL drs_clk_en : std_logic := '0';133 SIGNAL drs_read_s_cell : std_logic := '0';134 SIGNAL drs_read_s_cell_ready : std_logic;135 -- --136 -- drs_dwrite : out std_logic := '1';137 SIGNAL drs_readout_ready : std_logic := '0';138 SIGNAL drs_readout_ready_ack : std_logic;139 SIGNAL drs_readout_started : std_logic;140 SIGNAL drs_s_cell_array : drs_s_cell_array_type;141 SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0');142 SIGNAL dwrite : std_logic := '1';143 SIGNAL dwrite_enable : std_logic := '1';144 SIGNAL new_config : std_logic := '0';145 SIGNAL package_length : std_logic_vector(15 DOWNTO 0);146 SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards147 SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once148 SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift149 SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0);150 SIGNAL ram_data : std_logic_vector(15 DOWNTO 0);151 SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);152 SIGNAL ram_write_ea : std_logic;153 SIGNAL ram_write_ready : std_logic := '0';154 -- --155 SIGNAL ram_write_ready_ack : std_logic := '0';156 SIGNAL roi_array : roi_array_type;157 SIGNAL roi_max : roi_max_type;158 SIGNAL s_trigger : std_logic;159 SIGNAL s_trigger_0 : std_logic;160 SIGNAL sclk1 : std_logic;161 SIGNAL sclk_enable : std_logic;162 SIGNAL sensor_array : sensor_array_type;163 SIGNAL sensor_ready : std_logic;164 SIGNAL socks_connected : std_logic;165 SIGNAL socks_waiting : std_logic;166 SIGNAL srclk_enable : std_logic := '0';167 SIGNAL srin_write_ack : std_logic := '0';168 SIGNAL srin_write_ready : std_logic := '0';169 SIGNAL start_srin_write_8b : std_logic;170 SIGNAL trigger1 : std_logic;171 SIGNAL trigger_enable : std_logic;172 SIGNAL trigger_id : std_logic_vector(47 DOWNTO 0);173 SIGNAL trigger_out : std_logic := '0';174 SIGNAL wiz_ack : std_logic;175 SIGNAL wiz_busy : std_logic;176 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0');177 SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0');178 SIGNAL wiz_write_ea : std_logic := '0';179 SIGNAL wiz_write_end : std_logic := '0';180 SIGNAL wiz_write_header : std_logic := '0';181 SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0');182 SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0";183 184 -- Implicit buffer signal declarations185 SIGNAL CLK_25_PS_internal : std_logic;186 SIGNAL CLK_50_internal : std_logic;187 SIGNAL alarm_refclk_too_high_internal : std_logic;188 SIGNAL alarm_refclk_too_low_internal : std_logic;189 190 191 -- Component Declarations192 COMPONENT REFCLK_counter193 PORT (194 clk : IN std_logic;195 refclk_in : IN std_logic;196 alarm_refclk_too_high : OUT std_logic := '0';197 alarm_refclk_too_low : OUT std_logic := '0';198 counter_result : OUT std_logic_vector (11 DOWNTO 0) := (others => '0')199 );200 END COMPONENT;201 COMPONENT adc_buffer202 PORT (203 adc_data_array : IN adc_data_array_type;204 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);205 clk_ps : IN std_logic;206 adc_data_array_int : OUT adc_data_array_type;207 adc_otr : OUT std_logic_vector (3 DOWNTO 0)208 );209 END COMPONENT;210 COMPONENT clock_generator_var_ps211 PORT (212 CLK : IN std_logic ;213 RST_IN : IN std_logic ;214 direction : IN std_logic ;215 do_shift : IN std_logic ;216 CLK_25 : OUT std_logic ;217 CLK_25_PS : OUT std_logic ;218 CLK_50 : OUT std_logic ;219 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0')220 );221 END COMPONENT;222 COMPONENT continous_pulser223 GENERIC (224 MINIMAL_TRIGGER_WAIT_TIME : integer := 250000225 );226 PORT (227 CLK : IN std_logic;228 enable : IN std_logic;229 multiplier : IN std_logic_vector (7 DOWNTO 0);230 trigger : OUT std_logic231 );232 END COMPONENT;233 COMPONENT control_unit234 PORT (235 clk : IN STD_LOGIC ;236 config_addr : IN std_logic_vector (7 DOWNTO 0);237 config_rd_en : IN std_logic ;238 config_start : IN std_logic ;239 config_wr_en : IN std_logic ;240 config_busy : OUT std_logic ;241 config_data_valid : OUT std_logic ;242 config_ready : OUT std_logic ;243 -- --244 config_rw_ack : OUT std_logic := '0';245 -- --246 config_rw_ready : OUT std_logic := '0';247 config_started : OUT std_logic := '0';248 dac_array : OUT dac_array_type ;249 roi_array : OUT roi_array_type ;250 config_data : INOUT std_logic_vector (15 DOWNTO 0)251 );252 END COMPONENT;253 COMPONENT dataRAM_64b_16b_width14_5254 PORT (255 clka : IN std_logic ;256 dina : IN std_logic_VECTOR (63 DOWNTO 0);257 addra : IN std_logic_VECTOR (14 DOWNTO 0);258 wea : IN std_logic_VECTOR (0 DOWNTO 0);259 clkb : IN std_logic ;260 addrb : IN std_logic_VECTOR (16 DOWNTO 0);261 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)262 );263 END COMPONENT;264 COMPONENT data_generator265 GENERIC (266 RAM_ADDR_WIDTH : integer := 12267 );268 PORT (269 -- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');270 clk : IN std_logic ;271 data_out : OUT std_logic_vector (63 DOWNTO 0);272 addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);273 write_ea : OUT std_logic_vector (0 DOWNTO 0) := "0";274 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);275 ram_write_ea : IN std_logic ;276 ram_write_ready : OUT std_logic := '0';277 -- --278 ram_write_ready_ack : IN std_logic ;279 -- --280 config_start_mm : OUT std_logic := '0';281 -- --282 config_start_cm : OUT std_logic := '0';283 -- --284 config_start_spi : OUT std_logic := '0';285 config_ready_mm : IN std_logic ;286 config_ready_cm : IN std_logic ;287 config_ready_spi : IN std_logic ;288 config_started_mm : IN std_logic ;289 config_started_cm : IN std_logic ;290 config_started_spi : IN std_logic ;291 roi_array : IN roi_array_type ;292 roi_max : IN roi_max_type ;293 sensor_array : IN sensor_array_type ;294 sensor_ready : IN std_logic ;295 dac_array : IN dac_array_type ;296 package_length : IN std_logic_vector (15 DOWNTO 0);297 board_id : IN std_logic_vector (3 DOWNTO 0);298 crate_id : IN std_logic_vector (1 DOWNTO 0);299 trigger_id : IN std_logic_vector (47 DOWNTO 0);300 trigger : IN std_logic ;301 -- s_trigger : in std_logic;302 new_config : IN std_logic ;303 config_started : OUT std_logic := '0';304 adc_data_array : IN adc_data_array_type ;305 adc_oeb : OUT std_logic := '1';306 adc_clk_en : OUT std_logic := '0';307 adc_otr : IN std_logic_vector (3 DOWNTO 0);308 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');309 -- --310 -- drs_dwrite : out std_logic := '1';311 drs_readout_ready : OUT std_logic := '0';312 drs_readout_ready_ack : IN std_logic ;313 -- --314 drs_clk_en : OUT std_logic := '0';315 -- --316 drs_read_s_cell : OUT std_logic := '0';317 drs_srin_write_8b : OUT std_logic := '0';318 drs_srin_write_ack : IN std_logic ;319 drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');320 drs_srin_write_ready : IN std_logic ;321 drs_read_s_cell_ready : IN std_logic ;322 drs_s_cell_array : IN drs_s_cell_array_type ;323 drs_readout_started : OUT std_logic := '0'324 );325 END COMPONENT;326 COMPONENT drs_pulser327 PORT (328 CLK : IN std_logic;329 SROUT_in_0 : IN std_logic;330 SROUT_in_1 : IN std_logic;331 SROUT_in_2 : IN std_logic;332 SROUT_in_3 : IN std_logic;333 srin_data : IN std_logic_vector (7 DOWNTO 0);334 start_endless_mode : IN std_logic;335 start_read_stop_pos_mode : IN std_logic;336 start_srin_write_8b : IN std_logic;337 RSRLOAD : OUT std_logic := '0';338 SRCLK : OUT std_logic := '0';339 SRIN_out : OUT std_logic := '0';340 srin_write_ack : OUT std_logic := '0';341 srin_write_ready : OUT std_logic := '0';342 stop_pos : OUT drs_s_cell_array_type;343 stop_pos_valid : OUT std_logic := '0'344 );345 END COMPONENT;346 COMPONENT led_controller347 GENERIC (348 HEARTBEAT_PWM_DIVIDER : integer := 500;349 MAX_DELAY : integer := 100; --not used anymore at all :-(350 WAITING_DIVIDER : integer := 500000000351 );352 PORT (353 CLK : IN std_logic;354 socks_connected : IN std_logic;355 socks_waiting : IN std_logic;356 trigger : IN std_logic;357 additional_flasher_out : OUT std_logic;358 amber : OUT std_logic;359 green : OUT std_logic;360 red : OUT std_logic361 );362 END COMPONENT;363 COMPONENT memory_manager364 GENERIC (365 RAM_ADDR_WIDTH_64B : integer := 12;366 RAM_ADDR_WIDTH_16B : integer := 14367 );368 PORT (369 clk : IN std_logic ;370 config_start : IN std_logic ;371 ram_write_ready : IN std_logic ;372 -- --373 ram_write_ready_ack : OUT std_logic := '0';374 -- --375 roi_array : IN roi_array_type ;376 ram_write_ea : OUT std_logic := '0';377 config_ready : OUT std_logic := '0';378 config_started : OUT std_logic := '0';379 roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11));380 package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');381 wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 DOWNTO 0) := (others => '0');382 wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0');383 wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');384 wiz_write_ea : OUT std_logic := '0';385 wiz_write_header : OUT std_logic := '0';386 wiz_write_end : OUT std_logic := '0';387 wiz_busy : IN std_logic ;388 wiz_ack : IN std_logic ;389 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0')390 );391 END COMPONENT;392 COMPONENT spi_interface393 PORT (394 clk_50MHz : IN std_logic ;395 config_start : IN std_logic ;396 dac_array : IN dac_array_type ;397 config_ready : OUT std_logic ;398 config_started : OUT std_logic := '0';399 dac_cs : OUT std_logic ;400 mosi : OUT std_logic := '0';401 sclk : OUT std_logic ;402 sensor_array : OUT sensor_array_type ;403 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);404 sensor_ready : OUT std_logic ;405 miso : INOUT std_logic406 );407 END COMPONENT;408 COMPONENT trigger_counter409 PORT (410 trigger_id : OUT std_logic_vector (47 DOWNTO 0);411 trigger : IN std_logic ;412 clk : IN std_logic413 );414 END COMPONENT;415 COMPONENT trigger_manager416 PORT (417 clk : IN std_logic;418 drs_readout_ready : IN std_logic;419 trigger_in : IN std_logic;420 drs_readout_ready_ack : OUT std_logic := '0';421 drs_write : OUT std_logic := '1';422 trigger_out : OUT std_logic := '0'423 );424 END COMPONENT;425 COMPONENT w5300_modul426 GENERIC (427 RAM_ADDR_WIDTH : integer := 14428 );429 PORT (430 clk : IN std_logic ;431 wiz_reset : OUT std_logic := '1';432 addr : OUT std_logic_vector (9 DOWNTO 0);433 data : INOUT std_logic_vector (15 DOWNTO 0);434 cs : OUT std_logic := '1';435 wr : OUT std_logic := '1';436 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');437 rd : OUT std_logic := '1';438 int : IN std_logic ;439 write_length : IN std_logic_vector (16 DOWNTO 0);440 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);441 ram_data : IN std_logic_vector (15 DOWNTO 0);442 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);443 data_valid : IN std_logic ;444 data_valid_ack : OUT std_logic := '0';445 busy : OUT std_logic := '1';446 write_header_flag : IN std_logic ;447 write_end_flag : IN std_logic ;448 fifo_channels : IN std_logic_vector (3 DOWNTO 0);449 -- softtrigger:450 s_trigger : OUT std_logic := '0';451 c_trigger_enable : OUT std_logic := '0';452 c_trigger_mult : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '1'); --subject TO changes453 -- FAD configuration signals:454 ------------------------------------------------------------------------------455 -- start entire configuration chain456 new_config : OUT std_logic := '0';457 config_started : IN std_logic ;458 -- read/write configRAM459 config_addr : OUT std_logic_vector (7 DOWNTO 0);460 config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z');461 config_wr_en : OUT std_logic := '0';462 config_rd_en : OUT std_logic := '0';463 config_rw_ack : IN std_logic ;464 config_rw_ready : IN std_logic ;465 config_busy : IN std_logic ;466 ------------------------------------------------------------------------------467 468 -- MAC/IP calculation signals:469 ------------------------------------------------------------------------------470 MAC_jumper : IN std_logic_vector (1 DOWNTO 0);471 BoardID : IN std_logic_vector (3 DOWNTO 0);472 CrateID : IN std_logic_vector (1 DOWNTO 0);473 ------------------------------------------------------------------------------474 475 -- user controllable enable signals476 ------------------------------------------------------------------------------477 trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted478 denable : OUT std_logic := '0'; -- default domino wave off479 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low.480 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH.481 srclk_enable : OUT std_logic := '1'; -- default SRCLK on.482 ------------------------------------------------------------------------------483 484 -- ADC CLK generator, is able to shift phase with respect to X_50M485 -- these signals control the behavior of the digital clock manager (DCM)486 ------------------------------------------------------------------------------487 ps_direction : OUT std_logic := '1'; -- default phase shift upwards488 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once489 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift490 ------------------------------------------------------------------------------491 492 -- signals used to control FAD LED bahavior:493 -- one of the three LEDs is used for com-status info494 ------------------------------------------------------------------------------495 socks_waiting : OUT std_logic ;496 socks_connected : OUT std_logic497 ------------------------------------------------------------------------------498 );499 END COMPONENT;500 501 -- Optional embedded configurations502 -- pragma synthesis_off503 FOR ALL : REFCLK_counter USE ENTITY FACT_FAD_lib.REFCLK_counter;504 FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer;505 FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps;506 FOR ALL : continous_pulser USE ENTITY FACT_FAD_lib.continous_pulser;507 FOR ALL : control_unit USE ENTITY FACT_FAD_lib.control_unit;508 FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5;509 FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator;510 FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser;511 FOR ALL : led_controller USE ENTITY FACT_FAD_lib.led_controller;512 FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager;513 FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface;514 FOR ALL : trigger_counter USE ENTITY FACT_FAD_lib.trigger_counter;515 FOR ALL : trigger_manager USE ENTITY FACT_FAD_lib.trigger_manager;516 FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul;517 -- pragma synthesis_on518 519 520 BEGIN521 522 -- ModuleWare code(v1.9) for instance 'I5' of 'and'523 drs_dwrite <= dwrite AND dwrite_enable;524 525 -- ModuleWare code(v1.9) for instance 'I6' of 'and'526 SRCLK <= SRCLK1 AND srclk_enable;527 528 -- ModuleWare code(v1.9) for instance 'U_1' of 'and'529 sclk <= sclk_enable AND sclk1;530 531 -- ModuleWare code(v1.9) for instance 'U_5' of 'and'532 denable <= denable_prim AND din1;533 534 -- ModuleWare code(v1.9) for instance 'U_11' of 'and'535 dout1 <= dout AND trigger_enable;536 537 -- ModuleWare code(v1.9) for instance 'U_7' of 'inv'538 din1 <= NOT(denable_inhibit);539 540 -- ModuleWare code(v1.9) for instance 'U_6' of 'or'541 denable_inhibit <= alarm_refclk_too_low_internal542 OR alarm_refclk_too_high_internal;543 544 -- ModuleWare code(v1.9) for instance 'U_9' of 'or'545 dout <= s_trigger OR trigger;546 547 -- ModuleWare code(v1.9) for instance 'U_13' of 'or'548 s_trigger <= s_trigger_0 OR trigger1;549 550 -- Instance port mappings.551 REFCLK_counter_main : REFCLK_counter552 PORT MAP (553 clk => CLK_50_internal,554 refclk_in => drs_refclk_in,555 counter_result => counter_result,556 alarm_refclk_too_high => alarm_refclk_too_high_internal,557 alarm_refclk_too_low => alarm_refclk_too_low_internal558 );559 I_main_adc_buffer : adc_buffer560 PORT MAP (561 clk_ps => CLK_25_PS_internal,562 adc_data_array => adc_data_array,563 adc_otr_array => adc_otr_array,564 adc_data_array_int => adc_data_array_int,565 adc_otr => adc_otr566 );567 U_2 : clock_generator_var_ps568 PORT MAP (569 CLK => CLK,570 RST_IN => ps_reset,571 direction => ps_direction,572 do_shift => ps_do_phase_shift,573 CLK_25 => CLK_25,574 CLK_25_PS => CLK_25_PS_internal,575 CLK_50 => CLK_50_internal,576 offset => OPEN577 );578 U_3 : continous_pulser579 GENERIC MAP (580 MINIMAL_TRIGGER_WAIT_TIME => 250000581 )582 PORT MAP (583 CLK => CLK_25,584 enable => c_trigger_enable,585 multiplier => c_trigger_mult,586 trigger => trigger1587 );588 I_main_control_unit : control_unit589 PORT MAP (590 clk => CLK_50_internal,591 config_addr => config_addr,592 config_rd_en => config_rd_en,593 config_start => config_start_cm,594 config_wr_en => config_wr_en,595 config_busy => config_busy,596 config_data_valid => config_data_valid,597 config_ready => config_ready_cm,598 config_rw_ack => config_rw_ack,599 config_rw_ready => config_rw_ready,600 config_started => config_started_cu,601 dac_array => dac_array,602 roi_array => roi_array,603 config_data => config_data604 );605 U_4 : dataRAM_64b_16b_width14_5606 PORT MAP (607 clka => CLK_25,608 dina => data_out,609 addra => addr_out,610 wea => write_ea,611 clkb => CLK_50_internal,612 addrb => ram_addr,613 doutb => ram_data614 );615 I_main_data_generator : data_generator616 GENERIC MAP (617 RAM_ADDR_WIDTH => RAMADDRWIDTH64b618 )619 PORT MAP (620 clk => CLK_25,621 data_out => data_out,622 addr_out => addr_out,623 write_ea => write_ea,624 ram_start_addr => ram_start_addr,625 ram_write_ea => ram_write_ea,626 ram_write_ready => ram_write_ready,627 ram_write_ready_ack => ram_write_ready_ack,628 config_start_mm => config_start,629 config_start_cm => config_start_cm,630 config_start_spi => config_start_spi,631 config_ready_mm => config_ready,632 config_ready_cm => config_ready_cm,633 config_ready_spi => config_ready_spi,634 config_started_mm => config_started_mm,635 config_started_cm => config_started_cu,636 config_started_spi => config_started_spi,637 roi_array => roi_array,638 roi_max => roi_max,639 sensor_array => sensor_array,640 sensor_ready => sensor_ready,641 dac_array => dac_array,642 package_length => package_length,643 board_id => board_id,644 crate_id => crate_id,645 trigger_id => trigger_id,646 trigger => trigger_out,647 new_config => new_config,648 config_started => config_started,649 adc_data_array => adc_data_array_int,650 adc_oeb => adc_oeb,651 adc_clk_en => adc_clk_en,652 adc_otr => adc_otr,653 drs_channel_id => drs_channel_id,654 drs_readout_ready => drs_readout_ready,655 drs_readout_ready_ack => drs_readout_ready_ack,656 drs_clk_en => drs_clk_en,657 drs_read_s_cell => drs_read_s_cell,658 drs_srin_write_8b => start_srin_write_8b,659 drs_srin_write_ack => srin_write_ack,660 drs_srin_data => drs_srin_data,661 drs_srin_write_ready => srin_write_ready,662 drs_read_s_cell_ready => drs_read_s_cell_ready,663 drs_s_cell_array => drs_s_cell_array,664 drs_readout_started => drs_readout_started665 );666 I_main_drs_pulser : drs_pulser667 PORT MAP (668 CLK => CLK_25,669 start_endless_mode => drs_clk_en,670 start_read_stop_pos_mode => drs_read_s_cell,671 SROUT_in_0 => SROUT_in_0,672 SROUT_in_1 => SROUT_in_1,673 SROUT_in_2 => SROUT_in_2,674 SROUT_in_3 => SROUT_in_3,675 stop_pos => drs_s_cell_array,676 stop_pos_valid => drs_read_s_cell_ready,677 start_srin_write_8b => start_srin_write_8b,678 srin_write_ready => srin_write_ready,679 srin_write_ack => srin_write_ack,680 srin_data => drs_srin_data,681 SRIN_out => SRIN_out,682 RSRLOAD => RSRLOAD,683 SRCLK => SRCLK1684 );685 U_10 : led_controller686 GENERIC MAP (687 HEARTBEAT_PWM_DIVIDER => 50000, -- 10kHz @ 50 MHz688 MAX_DELAY => 100,689 WAITING_DIVIDER => 50000000 -- 1Hz @ 50 MHz690 )691 PORT MAP (692 CLK => CLK_50_internal,693 green => green,694 amber => amber,695 red => red,696 additional_flasher_out => additional_flasher_out,697 trigger => drs_readout_started,698 socks_waiting => socks_waiting,699 socks_connected => socks_connected700 );701 I_main_memory_manager : memory_manager702 GENERIC MAP (703 RAM_ADDR_WIDTH_64B => RAMADDRWIDTH64b,704 RAM_ADDR_WIDTH_16B => RAMADDRWIDTH64b+2705 )706 PORT MAP (707 clk => CLK_25,708 config_start => config_start,709 ram_write_ready => ram_write_ready,710 ram_write_ready_ack => ram_write_ready_ack,711 roi_array => roi_array,712 ram_write_ea => ram_write_ea,713 config_ready => config_ready,714 config_started => config_started_mm,715 roi_max => roi_max,716 package_length => package_length,717 wiz_ram_start_addr => wiz_ram_start_addr,718 wiz_write_length => wiz_write_length,719 wiz_number_of_channels => wiz_number_of_channels,720 wiz_write_ea => wiz_write_ea,721 wiz_write_header => wiz_write_header,722 wiz_write_end => wiz_write_end,723 wiz_busy => wiz_busy,724 wiz_ack => wiz_ack,725 ram_start_addr => ram_start_addr726 );727 I_main_SPI_interface : spi_interface728 PORT MAP (729 clk_50MHz => CLK_50_internal,730 config_start => config_start_spi,731 dac_array => dac_array,732 config_ready => config_ready_spi,733 config_started => config_started_spi,734 dac_cs => dac_cs,735 mosi => mosi,736 sclk => sclk1,737 sensor_array => sensor_array,738 sensor_cs => sensor_cs,739 sensor_ready => sensor_ready,740 miso => sio741 );742 I_main_ext_trigger : trigger_counter743 PORT MAP (744 trigger_id => trigger_id,745 trigger => trigger_out,746 clk => CLK_25_PS_internal747 );748 U_12 : trigger_manager749 PORT MAP (750 clk => CLK_25,751 trigger_in => dout1,752 trigger_out => trigger_out,753 drs_write => dwrite,754 drs_readout_ready => drs_readout_ready,755 drs_readout_ready_ack => drs_readout_ready_ack756 );757 I_main_ethernet : w5300_modul758 GENERIC MAP (759 RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2760 )761 PORT MAP (762 clk => CLK_50_internal,763 wiz_reset => wiz_reset,764 addr => wiz_addr,765 data => wiz_data,766 cs => wiz_cs,767 wr => wiz_wr,768 led => led,769 rd => wiz_rd,770 int => wiz_int,771 write_length => wiz_write_length,772 ram_start_addr => wiz_ram_start_addr,773 ram_data => ram_data,774 ram_addr => ram_addr,775 data_valid => wiz_write_ea,776 data_valid_ack => wiz_ack,777 busy => wiz_busy,778 write_header_flag => wiz_write_header,779 write_end_flag => wiz_write_end,780 fifo_channels => wiz_number_of_channels,781 s_trigger => s_trigger_0,782 c_trigger_enable => c_trigger_enable,783 c_trigger_mult => c_trigger_mult,784 new_config => new_config,785 config_started => config_started,786 config_addr => config_addr,787 config_data => config_data,788 config_wr_en => config_wr_en,789 config_rd_en => config_rd_en,790 config_rw_ack => config_rw_ack,791 config_rw_ready => config_rw_ready,792 config_busy => config_busy,793 MAC_jumper => D_T_in,794 BoardID => board_id,795 CrateID => crate_id,796 denable => denable_prim,797 dwrite_enable => dwrite_enable,798 sclk_enable => sclk_enable,799 ps_direction => ps_direction,800 ps_do_phase_shift => ps_do_phase_shift,801 ps_reset => ps_reset,802 srclk_enable => srclk_enable,803 trigger_enable => trigger_enable,804 socks_waiting => socks_waiting,805 socks_connected => socks_connected806 );807 808 -- Implicit buffered output assignments809 CLK_25_PS <= CLK_25_PS_internal;810 CLK_50 <= CLK_50_internal;811 alarm_refclk_too_high <= alarm_refclk_too_high_internal;812 alarm_refclk_too_low <= alarm_refclk_too_low_internal;813 814 END struct; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10138 r10170 89 89 INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 90 90 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA); 91 type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, 91 type state_write_type is ( 92 WR_START, 93 WR_GET_EVT_ID_WAIT1, WR_GET_EVT_ID1, WR_GET_EVT_ID_WAIT2, WR_GET_EVT_ID2, 94 WR_MOD7_STARTED, WR_WAIT_FOR_MOD7, 95 WR_CHECK_FOR_FIFO_SPACE_01, WR_CHECK_FOR_FIFO_SPACE_02, WR_CHECK_FOR_FIFO_SPACE_03, WR_CHECK_FOR_FIFO_SPACE_04, 96 97 WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, 92 98 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3); 93 99 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); … … 178 184 signal socket_nr_counter : integer range 1 to 7 :=1; --used to determine which socket is used for data sending 179 185 signal socket_send_mode : std_logic := '0'; -- if 0 data is send via socket 0; if 1 data is send via the other sockets. 186 -- signals for Sockek Number calculation 187 signal event_number : std_logic_vector(31 downto 0); 188 signal mod7_start : std_logic := '0'; 189 signal mod7_started : std_logic; 190 signal mod7_valid : std_logic; 191 signal mod7_result : std_logic_vector(2 downto 0); 192 193 COMPONENT mod7 194 PORT ( 195 clk : IN std_logic; 196 number : IN std_logic_vector (31 DOWNTO 0); 197 start : IN std_logic; 198 remainder : OUT std_logic_vector (2 DOWNTO 0) := (others => '0'); 199 started : OUT std_logic := '0'; 200 valid : OUT std_logic := '0' 201 ); 202 END COMPONENT; 203 204 180 205 181 206 begin 207 208 mod7_calculator : mod7 209 PORT MAP ( 210 --locals => actuals 211 clk =>clk , 212 number =>event_number , 213 start =>mod7_start , 214 remainder =>mod7_result , 215 started =>mod7_started , 216 valid =>mod7_valid 217 ); 218 182 219 183 220 --synthesis translate_off … … 613 650 when MAIN3 => 614 651 -- led <= local_ram_start_addr (7 downto 0); 652 653 -- needed for the check: if there is enough space in W5300 FIFO 654 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2) 655 615 656 data_valid_ack <= '1'; 616 657 next_state <= MAIN; … … 780 821 when WRITE_DATA => 781 822 case state_write is 823 782 824 when WR_START => 783 825 if (local_write_header_flag = '1') then 784 ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ???? 826 ram_addr <= local_ram_start_addr + 6; -- Address of HIGH word of Event ID 827 state_write <= WR_GET_EVT_ID_WAIT1; 828 else 829 state_write <= WR_CHECK_FOR_FIFO_SPACE_01; 785 830 end if; 786 state_write <= WR_WAIT1; 787 when WR_WAIT1 => 788 state_write <= WR_LENGTH; 789 when WR_LENGTH => 790 if (local_write_header_flag = '1') then 791 if (socket_send_mode = '1') then -- send via all sockets 792 local_socket_nr <= conv_std_logic_vector(socket_nr_counter, 3); 793 if (socket_nr_counter < 7) then 794 socket_nr_counter <= socket_nr_counter + 1; 795 else 796 socket_nr_counter <= 1; 797 end if; 798 else -- only send via socket 0\ 799 local_socket_nr <= "000"; 800 end if; 801 end if; 802 next_state_tmp <= next_state; 803 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2) 804 data_cnt <= 0; 805 state_write <= WR_01; 831 832 when WR_GET_EVT_ID_WAIT1 => 833 state_write <= WR_GET_EVT_ID1; 834 when WR_GET_EVT_ID1 => 835 event_number(31 downto 16) <= ram_data; 836 ram_addr <= local_ram_start_addr + 7; -- Address of LOW word of Event ID 837 state_write <= WR_GET_EVT_ID_WAIT2; 838 when WR_GET_EVT_ID_WAIT2 => 839 state_write <= WR_GET_EVT_ID2; 840 when WR_GET_EVT_ID2 => 841 event_number(15 downto 0) <= ram_data; 842 if (mod7_valid = '1') then 843 mod7_start <= '1'; 844 state_write <= WR_MOD7_STARTED; 845 else 846 state_write <= WR_GET_EVT_ID2; 847 end if; 848 849 when WR_MOD7_STARTED => 850 if (mod7_started = '1') then 851 mod7_start <= '0'; 852 state_write <= WR_WAIT_FOR_MOD7; 853 end if; 854 855 when WR_WAIT_FOR_MOD7 => 856 if (mod7_valid = '1') then 857 if (socket_send_mode = '1') then -- send via all sockets 858 local_socket_nr <= mod7_result; 859 else -- only send via socket 0\ 860 local_socket_nr <= "000"; 861 end if; 862 next_state_tmp <= next_state; 863 data_cnt <= 0; 864 state_write <= WR_CHECK_FOR_FIFO_SPACE_01; 865 else 866 state_write <= WR_WAIT_FOR_MOD7; 867 end if; 868 806 869 -- Check FIFO Size 807 when WR_ 01 =>870 when WR_CHECK_FOR_FIFO_SPACE_01 => 808 871 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC; 809 872 state_init <= READ_REG; 810 873 next_state <= WRITE_DATA; 811 state_write <= WR_ 02;812 when WR_ 02 =>874 state_write <= WR_CHECK_FOR_FIFO_SPACE_02; 875 when WR_CHECK_FOR_FIFO_SPACE_02 => 813 876 socket_tx_free (31 downto 16) <= data_read; 814 877 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2"; 815 878 state_init <= READ_REG; 816 879 next_state <= WRITE_DATA; 817 state_write <= WR_ 03;818 when WR_ 03 =>880 state_write <= WR_CHECK_FOR_FIFO_SPACE_03; 881 when WR_CHECK_FOR_FIFO_SPACE_03 => 819 882 socket_tx_free (15 downto 0) <= data_read; 820 state_write <= WR_04; 821 when WR_04 => 822 823 -- led <= socket_tx_free (15 downto 8); 824 883 state_write <= WR_CHECK_FOR_FIFO_SPACE_04; 884 when WR_CHECK_FOR_FIFO_SPACE_04 => 825 885 -- if (socket_tx_free (16 downto 0) < write_length_bytes) then 826 886 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then 827 887 state_write <= WR_01; 828 888 else 829 830 889 if (local_write_header_flag = '1') then 890 state_write <= WR_FIFO; 831 891 else 832 892 state_write <= WR_ADC; 833 893 end if; 834 894 end if; … … 838 898 -- Write Header 839 899 when WR_FIFO => 840 841 900 ram_addr <= local_ram_start_addr + local_ram_addr; 901 state_write <= WR_FIFO1; 842 902 when WR_FIFO1 => 843 903 data_cnt <= data_cnt + 1; 844 904 if (data_cnt < PACKAGE_HEADER_LENGTH) then --??? 845 905 local_ram_addr <= local_ram_addr + 1; 846 if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words847 local_ram_addr <= local_ram_addr + 2;848 end if;849 if (data_cnt = 9) then -- skip empty words850 local_ram_addr <= local_ram_addr + 4;851 end if;906 -- if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words 907 -- local_ram_addr <= local_ram_addr + 2; 908 -- end if; 909 -- if (data_cnt = 9) then -- skip empty words 910 -- local_ram_addr <= local_ram_addr + 4; 911 -- end if; 852 912 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 853 913 ram_access <= '1';
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