 Timestamp:
 Feb 24, 2011, 2:58:42 PM (9 years ago)
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firmware/FTM/ftm_definitions.vhd
r10162 r10177 18 18  19 19  modified: Patrick Vogler, February 17 2011 20  merged with library file from Dortmund, Q. Weitzel, February 24, 2011 20 21  21 22 … … 29 30 package ftm_array_types is 30 31 32  !!! some arrays are also defined in the ftm_constants package !!! 33 31 34  data arrays for a single FTU 32 35 type FTU_enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0); … … 38 41  data array for clock conditioner interface 39 42 type clk_cond_array_type is array (0 to 8) of std_logic_vector (31 downto 0); 43 44  network array types 45 type ip_type is array (0 to 3) of integer; 46 type mac_type is array (0 to 2) of std_logic_vector (15 downto 0); 40 47 41 48 end ftm_array_types; … … 46 53 use IEEE.STD_LOGIC_ARITH.ALL; 47 54 use IEEE.STD_LOGIC_UNSIGNED.ALL; 55 use ftm_definitions.ftm_array_types.all; 48 56  use IEEE.NUMERIC_STD.ALL; 49 57 50 58 package ftm_constants is 51 59 60  !!! many constants depend on each other or are defined 2x with different types !!! 61 52 62 constant NO_OF_CRATES : integer := 4; 53 63 constant NO_OF_FTUS_PER_CRATE : integer := 10; 54 64 constant NO_OF_FTU_ENABLE_REG : integer := 4; 55 65 constant NO_OF_FTU_DAC_REG : integer := 5; 56 constant NO_OF_FTU_LIST_REG : integer := 6;57 66 58 67 internal FPGA clock frequencies … … 78 87 constant DNA_FOR_SIM : bit_vector := X"01710000E0000501"; 79 88 80 RAM address offsets and widths 81 constant STATIC_RAM_ACT_FTU_OFFSET : integer := 16#1B0#; 89  Clock conditioner (LMK03000, National semiconductor) interface 90 constant MICROWIRE_CLK_FREQUENCY : integer := 2000000;  2 MHz 91  value to be written to R0 of the LMK03000 to perform a reset, see LMK03000 datasheet 92 constant LMK03000_Reset : std_logic_vector (31 downto 0) := x"80000000"; 93 constant LMK03000_REGISTER_WIDTH : integer := 32; 94 constant LMK03000_REGISTER_COUNT : integer := 9;  number of registers to be programmed in the LMK03000 including reset 95 96  network settings Dortmund 97  constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"95A0"); 98  constant NETMASK : ip_type := (255, 255, 255, 0); 99  constant IP_ADDRESS : ip_type := (129, 217, 160, 118); 100  constant GATEWAY : ip_type := (129, 217, 160, 1); 101  constant FIRST_PORT : integer := 5000; 102 103  network settings Zuerich 104 constant MAC_ADDRESS : mac_type := (X"FAC7", X"0FAD", X"1101"); 105 constant NETMASK : ip_type := (255, 255, 248, 0); 106 constant IP_ADDRESS : ip_type := (192, 33, 99, 246); 107 constant GATEWAY : ip_type := (192, 33, 96, 1); 108 constant FIRST_PORT : integer := 5000; 109 110  W5300 settings 111 constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000";  socket address offset 112  W5300 Registers 113 constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0'); 114 constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0"; 115 constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2"; 116 constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4"; 117 constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8"; 118 constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10"; 119 constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14"; 120 constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18"; 121 constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C"; 122 constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E"; 123 constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20"; 124 constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22"; 125 constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24"; 126 constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26"; 127 constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28"; 128 constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A"; 129 constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C"; 130 constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E"; 131 constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30"; 132 constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0"; 133 constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2"; 134 constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4"; 135 constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6"; 136 constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8"; 137 constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A"; 138 constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12"; 139 constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14"; 140 constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20"; 141 constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24"; 142 constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28"; 143 constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E"; 144 constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30"; 145  End W5300 registers 146 constant W5300_TX_FIFO_SIZE_8B : integer := 65536;  Socket TX FIFOSize in Bytes 147 constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2);  Socket TX FIFOSize in 16 Bit Words 148 constant W5300_LAST_SOCKET : integer := 0; 149 150  Commands 151 constant CMD_START_DELIMITER : std_logic_vector := X"0040";  "@" 152 constant CMD_TLED : std_logic_vector := X"C000";  only a test 153 constant CMD_READ : std_logic_vector := X"0001"; 154 constant PAR_READ_SD : std_logic_vector := X"0001";  read static data block 155 constant PAR_READ_DD : std_logic_vector := X"0002";  read dynamic data block 156  only for debugging: data_block (0) = ADDR 157 constant PAR_READ_SD_ADDR : std_logic_vector := X"0004";  read from address in static data block 158 constant PAR_READ_DD_ADDR : std_logic_vector := X"0008";  read from address in dynamic data block 159 constant CMD_WRITE : std_logic_vector := X"0002"; 160 constant PAR_WRITE_SD : std_logic_vector := X"0001";  write static data block 161  only for debugging: data_block (0) = ADDR, data_block (1) = DATA 162 constant PAR_WRITE_SD_ADDR : std_logic_vector := X"0002";  write to address in static data ram 163  ping all FTUs 164 constant CMD_PING : std_logic_vector := X"0010";  ping all FTUs 165 166  FTUlist parameters 167 constant FL_BLOCK_SIZE : std_logic_vector := X"0F9";  FTUlist size  9 + (40 * 6) =249 168 constant NO_OF_FTU_LIST_REG : integer := 6; 169 constant FTU_LIST_RAM_OFFSET : integer := 16#009#; 170 constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12; 171 172  Static data block 173 constant SD_BLOCK_SIZE_GENERAL : integer := 32;  X"20"  static data block size without FTU data 174 constant SD_FTU_BASE_ADDR : std_logic_vector := X"020";  beginning of FTU data 82 175 constant STATIC_RAM_CFG_FTU_OFFSET : integer := 16#020#; 83 176 constant STATIC_RAM_ADDR_WIDTH : integer := 12; 84 constant FTU_LIST_RAM_OFFSET : integer := 16#009#; 85 constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12; 86 87 88 89  Clock conditioner (LMK03000, National semiconductor) interface 90 constant MICROWIRE_CLK_FREQUENCY : integer := 2000000;  2 MHz 91 constant LMK03000_Reset : std_logic_vector (31 downto 0) := x"80000000"; 92  value to be written to R0 of the LMK03000 to perform a reset 93  see LMK03000 datasheet 94 constant LMK03000_REGISTER_WIDTH : integer := 32; 95 constant LMK03000_REGISTER_COUNT : integer := 9;  number of registers to 96  be programmed in the 97  LMK03000 including reset 98 99 100 101 177 constant SD_FTU_DATA_SIZE : integer := 10;  X"00A"  size of one FTU data block 178 constant SD_FTU_NUM : integer := 40;  number of FTUs 179 constant SD_FTU_ACTIVE_BASE_ADDR : std_logic_vector := X"1B0";  beginning of active FTU lists 180 constant SD_FTU_ACTIVE_NUM : integer := 4;  number of active FTU lists (cr0 to cr3) 181 constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4";  total size of static data block 182 183  addresses in static data block 184 constant SD_ADDR_general_settings : std_logic_vector := X"000"; 185 constant SD_ADDR_led : std_logic_vector := X"001"; 186 constant SD_ADDR_lp_pt_freq : std_logic_vector := X"002"; 187 constant SD_ADDR_lp_pt_ratio : std_logic_vector := X"003"; 188 constant SD_ADDR_lp1_amplitude : std_logic_vector := X"004"; 189 constant SD_ADDR_lp2_amplitude : std_logic_vector := X"005"; 190 constant SD_ADDR_lp1_delay : std_logic_vector := X"006"; 191 constant SD_ADDR_lp2_delay : std_logic_vector := X"007"; 192 constant SD_ADDR_coin_n_p : std_logic_vector := X"008"; 193 constant SD_ADDR_coin_n_c : std_logic_vector := X"009"; 194 constant SD_ADDR_trigger_delay : std_logic_vector := X"00A"; 195 constant SD_ADDR_timemarker_delay : std_logic_vector := X"00B"; 196 constant SD_ADDR_dead_time : std_logic_vector := X"00C"; 197 constant SD_ADDR_cc_R0_HI : std_logic_vector := X"00D"; 198 constant SD_ADDR_cc_R0_LO : std_logic_vector := X"00E"; 199 constant SD_ADDR_cc_R1_HI : std_logic_vector := X"00F"; 200 constant SD_ADDR_cc_R1_LO : std_logic_vector := X"010"; 201 constant SD_ADDR_cc_R8_HI : std_logic_vector := X"011"; 202 constant SD_ADDR_cc_R8_LO : std_logic_vector := X"012"; 203 constant SD_ADDR_cc_R9_HI : std_logic_vector := X"013"; 204 constant SD_ADDR_cc_R9_LO : std_logic_vector := X"014"; 205 constant SD_ADDR_cc_R11_HI : std_logic_vector := X"015"; 206 constant SD_ADDR_cc_R11_LO : std_logic_vector := X"016"; 207 constant SD_ADDR_cc_R13_HI : std_logic_vector := X"017"; 208 constant SD_ADDR_cc_R13_LO : std_logic_vector := X"018"; 209 constant SD_ADDR_cc_R14_HI : std_logic_vector := X"019"; 210 constant SD_ADDR_cc_R14_LO : std_logic_vector := X"01A"; 211 constant SD_ADDR_cc_R15_HI : std_logic_vector := X"01B"; 212 constant SD_ADDR_cc_R15_LO : std_logic_vector := X"01C"; 213 constant SD_ADDR_ftu_active_cr0 : std_logic_vector := X"1B0"; 214 constant SD_ADDR_ftu_active_cr1 : std_logic_vector := X"1B1"; 215 constant SD_ADDR_ftu_active_cr2 : std_logic_vector := X"1B2"; 216 constant SD_ADDR_ftu_active_cr3 : std_logic_vector := X"1B3"; 217 constant STATIC_RAM_ACT_FTU_OFFSET : integer := 16#1B0#; 218 219  arrays for default values 220 type sd_block_default_array_type is array (0 to (SD_BLOCK_SIZE_GENERAL  1)) of std_logic_vector (15 downto 0); 221 type sd_block_ftu_default_array_type is array (0 to (SD_FTU_DATA_SIZE  1)) of std_logic_vector (15 downto 0); 222 223  general default values 224  !!! to be defined !!! 225 constant sd_block_default_array : sd_block_default_array_type := ( 226 X"0000",  SD_ADDR_general_settings  general settings 227 X"0000",  SD_ADDR_led  onboard status LEDs 228 X"0002",  SD_ADDR_lp_pt_freq  light pulser and pedestal trigger frequency 229 X"0003",  SD_ADDR_lp_pt_ratio...  ratio between LP1, LP2 and pedestal triggers 230 X"0004",  SD_ADDR_lp1_amplitude  light pulser 1 amplitude 231 X"0005",  SD_ADDR_lp2_amplitude  light pulser 2 amplitude 232 X"0006",  SD_ADDR_lp1_delay  light pulser 1 delay 233 X"0007",  SD_ADDR_lp2_delay  light pulser 2 delay 234 X"0008",  SD_ADDR_coin_n_p  majority coincidence n (for physics) 235 X"0009",  SD_ADDR_coin_n_c  majority coincidence n (for calibration) 236 X"000A",  SD_ADDR_trigger_delay  trigger delay 237 X"000B",  SD_ADDR_timemarker_delay  timemarker delay 238 X"000C",  SD_ADDR_dead_time  dead time 239 X"000D",  SD_ADDR_cc_R0_HI  clock conditioner R0 bits 31...16 240 X"000E",  SD_ADDR_cc_R0_LO  clock conditioner R0 bits 15...0 241 X"000F",  SD_ADDR_cc_R1_HI  clock conditioner R1 bits 31...16 242 X"0010",  SD_ADDR_cc_R1_LO  clock conditioner R1 bits 15...0 243 X"0011",  SD_ADDR_cc_R8_HI  clock conditioner R8 bits 31...16 244 X"0012",  SD_ADDR_cc_R8_LO  clock conditioner R8 bits 15...0 245 X"0013",  SD_ADDR_cc_R9_HI  clock conditioner R9 bits 31...16 246 X"0014",  SD_ADDR_cc_R9_LO  clock conditioner R9 bits 15...0 247 X"0015",  SD_ADDR_cc_R11_HI  clock conditioner R11 bits 31...16 248 X"0016",  SD_ADDR_cc_R11_LO  clock conditioner R11 bits 15...0 249 X"0017",  SD_ADDR_cc_R13_HI  clock conditioner R13 bits 31...16 250 X"0018",  SD_ADDR_cc_R13_LO  clock conditioner R13 bits 15...0 251 X"0019",  SD_ADDR_cc_R14_HI  clock conditioner R14 bits 31...16 252 X"001A",  SD_ADDR_cc_R14_LO  clock conditioner R14 bits 15...0 253 X"001B",  SD_ADDR_cc_R15_HI  clock conditioner R15 bits 31...16 254 X"001C",  SD_ADDR_cc_R15_LO  clock conditioner R15 bits 15...0 255 X"001D",  SD_ADDR_coin_win_p  majority coincidence window (for physics) 256 X"001E",  SD_ADDR_coin_win_c  majority coincidence window (for calibration) 257 X"001F"   Spare 258 ); 259 260  default values for all FTUs 261 constant sd_block_ftu_default_array : sd_block_ftu_default_array_type := ( 262 X"01FF",  enables patch 0 board x crate y 263 X"01FF",  enables patch 1 board x crate y 264 X"01FF",  enables patch 2 board x crate y 265 X"01FF",  enables patch 3 board x crate y 266 X"01F4",  DAC_A board x crate y 267 X"01F4",  DAC_B board x crate y 268 X"01F4",  DAC_C board x crate y 269 X"01F4",  DAC_D board x crate y 270 X"0010",  DAC_H board x crate y 271 X"0001"  Prescaling board x crate y 272 ); 102 273 103 274 end ftm_constants;
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