Changeset 10256 for firmware/FTM/ethernet
- Timestamp:
- 03/24/11 14:42:34 (14 years ago)
- Location:
- firmware/FTM/ethernet
- Files:
-
- 2 added
- 5 edited
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cram_control_beha.vhd (modified) (4 diffs)
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dd_write_general_modul_beha.vhd (added)
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dram_control_beha.vhd (modified) (6 diffs)
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ethernet_modul_beha.vhd (modified) (12 diffs)
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fram_control_beha.vhd (modified) (3 diffs)
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header_modul_beha.vhd (added)
-
w5300_modul.vhd (modified) (20 diffs)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FTM/ethernet/cram_control_beha.vhd
r10227 r10256 8 8 -- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) 9 9 -- 10 -- updated by Q. Weitzel, March 14, 2011 11 -- 12 10 13 LIBRARY ieee; 11 14 USE ieee.std_logic_1164.all; … … 20 23 21 24 ENTITY cram_control IS 22 23 clk : INstd_logic;24 led: OUT std_logic_vector (7 downto 0) := X"00";25 cram_data_in : OUT std_logic_vector (15 downto 0);26 cram_data_out : INstd_logic_vector (15 downto 0);27 cram_addr_in, cram_addr_out : OUT std_logic_vector (11 downto 0);28 cram_we: OUT std_logic_vector (0 downto 0) := "0";29 sd_write, sd_read, sd_read_ftu : INstd_logic;30 sd_busy: OUT std_logic := '1';31 sd_started, sd_started_ftu: OUT std_logic := '0';32 sd_ready: OUT std_logic := '0';33 sd_data_in : INstd_logic_vector (15 downto 0);34 sd_data_out, sd_data_out_ftu: OUT std_logic_vector (15 downto 0) := (others => '0');35 sd_addr, sd_addr_ftu : INstd_logic_vector (11 downto 0);25 PORT( 26 clk : IN std_logic; 27 led : OUT std_logic_vector (7 downto 0) := X"00"; 28 cram_data_in : OUT std_logic_vector (15 downto 0) := (others => '0'); 29 cram_data_out : IN std_logic_vector (15 downto 0); 30 cram_addr_in, cram_addr_out : OUT std_logic_vector (11 downto 0) := (others => '0'); 31 cram_we : OUT std_logic_vector (0 downto 0) := "0"; 32 sd_write, sd_read, sd_read_ftu : IN std_logic; 33 sd_busy : OUT std_logic := '1'; 34 sd_started, sd_started_ftu : OUT std_logic := '0'; 35 sd_ready : OUT std_logic := '0'; 36 sd_data_in : IN std_logic_vector (15 downto 0); 37 sd_data_out, sd_data_out_ftu : OUT std_logic_vector (15 downto 0) := (others => '0'); 38 sd_addr, sd_addr_ftu : IN std_logic_vector (11 downto 0); 36 39 37 config_start_cc : INstd_logic;38 39 config_ready_cc: OUT std_logic := '0';40 config_start_cc : IN std_logic; 41 config_started_cc : OUT std_logic := '0'; 42 config_ready_cc : OUT std_logic := '0'; 40 43 41 -- data from config ram 42 general_settings : OUT std_logic_vector (15 downto 0) := (others => '0'); 43 lp_pt_freq : OUT std_logic_vector (15 downto 0) := (others => '0'); 44 lp_pt_ratio : OUT std_logic_vector (15 downto 0) := (others => '0'); 45 lp1_amplitude : OUT std_logic_vector (15 downto 0) := (others => '0'); 46 lp2_amplitude : OUT std_logic_vector (15 downto 0) := (others => '0'); 47 lp1_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); 48 lp2_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); 49 coin_n_p : OUT std_logic_vector (15 downto 0) := (others => '0'); 50 coin_n_c : OUT std_logic_vector (15 downto 0) := (others => '0'); 51 trigger_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); 52 timemarker_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); 53 dead_time : OUT std_logic_vector (15 downto 0) := (others => '0'); 54 cc_R0 : OUT std_logic_vector (31 downto 0) := (others => '0'); 55 cc_R1 : OUT std_logic_vector (31 downto 0) := (others => '0'); 56 cc_R8 : OUT std_logic_vector (31 downto 0) := (others => '0'); 57 cc_R9 : OUT std_logic_vector (31 downto 0) := (others => '0'); 58 cc_R11 : OUT std_logic_vector (31 downto 0) := (others => '0'); 59 cc_R13 : OUT std_logic_vector (31 downto 0) := (others => '0'); 60 cc_R14 : OUT std_logic_vector (31 downto 0) := (others => '0'); 61 cc_R15 : OUT std_logic_vector (31 downto 0) := (others => '0'); 62 coin_win_p : OUT std_logic_vector (15 downto 0) := (others => '0'); 63 coin_win_c : OUT std_logic_vector (15 downto 0) := (others => '0'); 64 ftu_active_cr0 : OUT std_logic_vector (15 downto 0) := (others => '0'); 65 ftu_active_cr1 : OUT std_logic_vector (15 downto 0) := (others => '0'); 66 ftu_active_cr2 : OUT std_logic_vector (15 downto 0) := (others => '0'); 67 ftu_active_cr3 : OUT std_logic_vector (15 downto 0) := (others => '0') 68 ); 69 70 -- Declarations 71 44 -- data from config ram 45 general_settings : OUT std_logic_vector (15 downto 0) := (others => '0'); 46 lp_pt_freq : OUT std_logic_vector (15 downto 0) := (others => '0'); 47 lp_pt_ratio : OUT std_logic_vector (15 downto 0) := (others => '0'); 48 lp1_amplitude : OUT std_logic_vector (15 downto 0) := (others => '0'); 49 lp2_amplitude : OUT std_logic_vector (15 downto 0) := (others => '0'); 50 lp1_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); 51 lp2_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); 52 coin_n_p : OUT std_logic_vector (15 downto 0) := (others => '0'); 53 coin_n_c : OUT std_logic_vector (15 downto 0) := (others => '0'); 54 trigger_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); 55 timemarker_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); 56 dead_time : OUT std_logic_vector (15 downto 0) := (others => '0'); 57 cc_R0 : OUT std_logic_vector (31 downto 0) := (others => '0'); 58 cc_R1 : OUT std_logic_vector (31 downto 0) := (others => '0'); 59 cc_R8 : OUT std_logic_vector (31 downto 0) := (others => '0'); 60 cc_R9 : OUT std_logic_vector (31 downto 0) := (others => '0'); 61 cc_R11 : OUT std_logic_vector (31 downto 0) := (others => '0'); 62 cc_R13 : OUT std_logic_vector (31 downto 0) := (others => '0'); 63 cc_R14 : OUT std_logic_vector (31 downto 0) := (others => '0'); 64 cc_R15 : OUT std_logic_vector (31 downto 0) := (others => '0'); 65 coin_win_p : OUT std_logic_vector (15 downto 0) := (others => '0'); 66 coin_win_c : OUT std_logic_vector (15 downto 0) := (others => '0'); 67 ftu_active_cr0 : OUT std_logic_vector (15 downto 0) := (others => '0'); 68 ftu_active_cr1 : OUT std_logic_vector (15 downto 0) := (others => '0'); 69 ftu_active_cr2 : OUT std_logic_vector (15 downto 0) := (others => '0'); 70 ftu_active_cr3 : OUT std_logic_vector (15 downto 0) := (others => '0') 71 ); 72 72 END cram_control ; 73 73 74 --75 74 ARCHITECTURE beha OF cram_control IS 76 75 … … 143 142 -- local_sd_data <= conv_std_logic_vector (ftu_active_cnt, 16); 144 143 -- for FTM-Board 145 local_sd_data <= sd_block_activeFTUlist_default_array (ftu_active_cnt); 144 local_sd_data <= sd_block_default_ftu_active_list (ftu_active_cnt); 145 -- -- 146 146 ftu_active_cnt <= ftu_active_cnt + 1; 147 147 next_state <= CR_INIT_03; … … 322 322 when CR_WRITE_END => 323 323 cram_we <= "0"; 324 sd_started <= '0'; 325 sd_ready <= '1'; 326 state_cram_proc <= next_state; 327 324 if (sd_write = '0') then 325 sd_started <= '0'; 326 sd_ready <= '1'; 327 state_cram_proc <= next_state; 328 end if; 328 329 329 330 -- -- -
firmware/FTM/ethernet/dram_control_beha.vhd
r10227 r10256 21 21 22 22 ENTITY dram_control IS 23 PORT( 24 clk : IN std_logic; 25 dram_data_in : OUT std_logic_vector (15 DOWNTO 0); 26 dram_data_out : IN std_logic_vector (15 DOWNTO 0); 27 dram_addr_in : OUT std_logic_vector (11 DOWNTO 0); 28 dram_addr_out : OUT std_logic_vector (11 DOWNTO 0); 29 dram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; 30 dd_block_start : IN std_logic; 31 dd_block_start_ftu : IN std_logic; 32 dd_block_start_ack : OUT std_logic := '0'; 33 dd_block_start_ack_ftu : OUT std_logic := '0'; 34 dd_block_ready : IN std_logic; 35 dd_block_ready_ftu : IN std_logic; 36 dd_read : IN std_logic; 37 dd_write_ftu : IN std_logic; 38 dd_busy : OUT std_logic := '1'; 39 dd_started : OUT std_logic := '0'; 40 dd_started_ftu : OUT std_logic := '0'; 41 dd_ready : OUT std_logic := '0'; 42 dd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 43 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); 44 dd_addr : IN std_logic_vector (11 DOWNTO 0); 45 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0) 46 ); 23 PORT( 24 clk : IN std_logic; 25 dram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 26 dram_data_out : IN std_logic_vector (15 DOWNTO 0); 27 dram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); 28 dram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); 29 dram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; 30 dd_block_start : IN std_logic; 31 dd_block_start_ftu : IN std_logic; 32 dd_block_start_ack : OUT std_logic := '0'; 33 dd_block_start_ack_ftu : OUT std_logic := '0'; 34 dd_block_ready : IN std_logic; 35 dd_block_ready_ftu : IN std_logic; 36 dd_read : IN std_logic; 37 dd_write_ftu : IN std_logic; 38 dd_write_general : IN std_logic; 39 dd_busy : OUT std_logic := '1'; 40 dd_started : OUT std_logic := '0'; 41 dd_started_ftu : OUT std_logic := '0'; 42 dd_started_general : OUT std_logic := '0'; 43 dd_ready : OUT std_logic := '0'; 44 dd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 45 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); 46 dd_data_in_general : IN std_logic_vector (15 DOWNTO 0); 47 dd_addr : IN std_logic_vector (11 DOWNTO 0); 48 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); 49 dd_addr_general : IN std_logic_vector (11 DOWNTO 0) 50 ); 47 51 48 52 -- Declarations … … 53 57 ARCHITECTURE beha OF dram_control IS 54 58 55 type state_dram_proc_type is (DR_INIT, DR_CONFIG, DR_IDLE, DR_DOUT_WIZ_START, DR_DOUT_WIZ_END, DR_WRITE_START, DR_WRITE_END ,59 type state_dram_proc_type is (DR_INIT, DR_CONFIG, DR_IDLE, DR_DOUT_WIZ_START, DR_DOUT_WIZ_END, DR_WRITE_START, DR_WRITE_END_FTU, DR_WRITE_END_GENERAL, 56 60 DR_READ_START, DR_READ_WAIT, DR_READ_END); 57 61 type state_dd_block_proc_type is (DD_BLOCK_IDLE, DD_BLOCK_WAIT_WIZ, DD_BLOCK_WAIT_FTU); … … 60 64 signal state_dram_proc : state_dram_proc_type := DR_INIT; 61 65 signal next_state : state_dram_proc_type := DR_IDLE; 66 signal write_end_state : state_dram_proc_type := DR_WRITE_END_FTU; 62 67 63 68 signal state_dd_block_proc : state_dd_block_proc_type := DD_BLOCK_IDLE; … … 70 75 dd_block_proc : process (clk) 71 76 begin 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 77 if rising_edge (clk) then 78 case state_dd_block_proc is 79 80 when DD_BLOCK_IDLE => 81 if (dd_block_start = '1') then 82 dd_block_start_ack <= '1'; 83 state_dd_block_proc <= DD_BLOCK_WAIT_WIZ; 84 elsif (dd_block_start_ftu = '1') then 85 dd_block_start_ack_ftu <= '1'; 86 state_dd_block_proc <= DD_BLOCK_WAIT_FTU; 87 end if; 88 89 when DD_BLOCK_WAIT_WIZ => 90 if (dd_block_ready = '1') then 91 dd_block_start_ack <= '0'; 92 state_dd_block_proc <= DD_BLOCK_IDLE; 93 end if; 94 95 when DD_BLOCK_WAIT_FTU => 96 if (dd_block_ready_ftu = '1') then 97 dd_block_start_ack_ftu <= '0'; 98 state_dd_block_proc <= DD_BLOCK_IDLE; 99 end if; 100 101 end case; 102 end if; 98 103 end process dd_block_proc; 99 104 … … 127 132 local_data <= dd_data_in_ftu; 128 133 next_state <= DR_IDLE; 134 write_end_state <= DR_WRITE_END_FTU; 129 135 state_dram_proc <= DR_WRITE_START; 130 end if; 131 136 137 elsif (dd_write_general = '1') then 138 dd_busy <= '1'; 139 dd_started_general <= '1'; 140 dd_ready <= '0'; 141 local_addr <= dd_addr_general; 142 local_data <= dd_data_in_general; 143 next_state <= DR_IDLE; 144 write_end_state <= DR_WRITE_END_GENERAL; 145 state_dram_proc <= DR_WRITE_START; 146 end if; 132 147 133 148 … … 150 165 dram_data_in <= local_data; 151 166 dram_we <= "1"; 152 state_dram_proc <= DR_WRITE_END;153 154 when DR_WRITE_END =>167 state_dram_proc <= write_end_state; 168 169 when DR_WRITE_END_FTU => 155 170 dram_we <= "0"; 156 dd_started_ftu <= '0'; 157 dd_ready <= '1'; 158 state_dram_proc <= next_state; 171 if (dd_write_ftu = '0') then 172 dd_started_ftu <= '0'; 173 dd_ready <= '1'; 174 state_dram_proc <= next_state; 175 end if; 176 177 when DR_WRITE_END_GENERAL => 178 dram_we <= "0"; 179 if (dd_write_general = '0') then 180 dd_started_general <= '0'; 181 dd_ready <= '1'; 182 state_dram_proc <= next_state; 183 end if; 159 184 160 185 -- -- -
firmware/FTM/ethernet/ethernet_modul_beha.vhd
r10227 r10256 3 3 -- Created: 4 4 -- by - kai.UNKNOWN (E5PCXX) 5 -- at - 11: 17:45 25.02.20115 -- at - 11:52:19 03.03.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 8 8 -- 9 9 10 LIBRARY ieee; 10 11 USE ieee.std_logic_1164.all; … … 16 17 17 18 ENTITY ethernet_modul IS 18 PORT( 19 wiz_reset : OUT std_logic := '1'; 20 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 21 wiz_data : INOUT std_logic_vector (15 DOWNTO 0); 22 wiz_cs : OUT std_logic := '1'; 23 wiz_wr : OUT std_logic := '1'; 24 wiz_rd : OUT std_logic := '1'; 25 wiz_int : IN std_logic; 26 clk : IN std_logic; 27 sd_ready : OUT std_logic; 28 sd_busy : OUT std_logic; 29 led : OUT std_logic_vector (7 DOWNTO 0); 30 sd_read_ftu : IN std_logic; 31 sd_started_ftu : OUT std_logic := '0'; 32 cc_R0 : OUT std_logic_vector (31 DOWNTO 0); 33 cc_R1 : OUT std_logic_vector (31 DOWNTO 0); 34 cc_R11 : OUT std_logic_vector (31 DOWNTO 0); 35 cc_R13 : OUT std_logic_vector (31 DOWNTO 0); 36 cc_R14 : OUT std_logic_vector (31 DOWNTO 0); 37 cc_R15 : OUT std_logic_vector (31 DOWNTO 0); 38 cc_R8 : OUT std_logic_vector (31 DOWNTO 0); 39 cc_R9 : OUT std_logic_vector (31 DOWNTO 0); 40 coin_n_c : OUT std_logic_vector (15 DOWNTO 0); 41 coin_n_p : OUT std_logic_vector (15 DOWNTO 0); 42 dead_time : OUT std_logic_vector (15 DOWNTO 0); 43 -- data from config ram 44 general_settings : OUT std_logic_vector (15 DOWNTO 0); 45 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0); 46 lp1_delay : OUT std_logic_vector (15 DOWNTO 0); 47 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0); 48 lp2_delay : OUT std_logic_vector (15 DOWNTO 0); 49 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0); 50 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0); 51 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0); 52 trigger_delay : OUT std_logic_vector (15 DOWNTO 0); 53 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); 54 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 55 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0); 56 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0); 57 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0); 58 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0); 59 new_config : OUT std_logic := '0'; 60 config_started : IN std_logic; 61 config_start_eth : IN std_logic; 62 config_started_eth : OUT std_logic := '0'; 63 config_ready_eth : OUT std_logic := '0'; 64 config_started_ack : OUT std_logic := '0'; 65 fl_busy : OUT std_logic; 66 fl_ready : OUT std_logic; 67 fl_write_ftu : IN std_logic; 68 fl_started_ftu : OUT std_logic := '0'; 69 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0); 70 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); 71 -- 72 ping_ftu_start : OUT std_logic := '0'; 73 ping_ftu_started : IN std_logic; 74 ping_ftu_ready : IN std_logic; 75 dd_write_ftu : IN std_logic; 76 dd_started_ftu : OUT std_logic := '0'; 77 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); 78 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); 79 dd_busy : OUT std_logic; 80 dd_ready : OUT std_logic; 81 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 82 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') 83 ); 84 85 -- Declarations 86 19 PORT( 20 wiz_reset : OUT std_logic := '1'; 21 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 22 wiz_data : INOUT std_logic_vector (15 DOWNTO 0); 23 wiz_cs : OUT std_logic := '1'; 24 wiz_wr : OUT std_logic := '1'; 25 wiz_rd : OUT std_logic := '1'; 26 wiz_int : IN std_logic; 27 clk : IN std_logic; 28 sd_ready : OUT std_logic; 29 sd_busy : OUT std_logic; 30 led : OUT std_logic_vector (7 DOWNTO 0); 31 sd_read_ftu : IN std_logic; 32 sd_started_ftu : OUT std_logic := '0'; 33 cc_R0 : OUT std_logic_vector (31 DOWNTO 0); 34 cc_R1 : OUT std_logic_vector (31 DOWNTO 0); 35 cc_R11 : OUT std_logic_vector (31 DOWNTO 0); 36 cc_R13 : OUT std_logic_vector (31 DOWNTO 0); 37 cc_R14 : OUT std_logic_vector (31 DOWNTO 0); 38 cc_R15 : OUT std_logic_vector (31 DOWNTO 0); 39 cc_R8 : OUT std_logic_vector (31 DOWNTO 0); 40 cc_R9 : OUT std_logic_vector (31 DOWNTO 0); 41 coin_n_c : OUT std_logic_vector (15 DOWNTO 0); 42 coin_n_p : OUT std_logic_vector (15 DOWNTO 0); 43 dead_time : OUT std_logic_vector (15 DOWNTO 0); 44 -- data from config ram 45 general_settings : OUT std_logic_vector (15 DOWNTO 0); 46 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0); 47 lp1_delay : OUT std_logic_vector (15 DOWNTO 0); 48 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0); 49 lp2_delay : OUT std_logic_vector (15 DOWNTO 0); 50 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0); 51 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0); 52 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0); 53 trigger_delay : OUT std_logic_vector (15 DOWNTO 0); 54 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); 55 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 56 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0); 57 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0); 58 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0); 59 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0); 60 new_config : OUT std_logic := '0'; 61 config_started : IN std_logic; 62 config_start_eth : IN std_logic; 63 config_started_eth : OUT std_logic := '0'; 64 config_ready_eth : OUT std_logic := '0'; 65 config_started_ack : OUT std_logic := '0'; 66 fl_busy : OUT std_logic; 67 fl_ready : OUT std_logic; 68 fl_write_ftu : IN std_logic; 69 fl_started_ftu : OUT std_logic := '0'; 70 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0); 71 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); 72 -- 73 ping_ftu_start : OUT std_logic := '0'; 74 ping_ftu_started : IN std_logic; 75 ping_ftu_ready : IN std_logic; 76 dd_write_ftu : IN std_logic; 77 dd_started_ftu : OUT std_logic := '0'; 78 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); 79 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); 80 dd_busy : OUT std_logic; 81 dd_ready : OUT std_logic; 82 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 83 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 84 dd_block_ready_ftu : IN std_logic; 85 dd_block_start_ack_ftu : OUT std_logic := '0'; 86 dd_block_start_ftu : IN std_logic; 87 dd_send : IN std_logic; 88 dd_send_ack : OUT std_logic := '1'; 89 dd_send_ready : OUT std_logic := '1' 90 ); 87 91 END ethernet_modul ; 88 92 89 --90 -- VHDL Architecture FACT_FTM_lib.ethernet_modul.beha91 --92 -- Created:93 -- by - kai.UNKNOWN (E5PCXX)94 -- at - 11:17:46 25.02.201195 --96 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)97 --98 --99 --100 --LIBRARY IEEE;101 --USE IEEE.STD_LOGIC_1164.all;102 --USE IEEE.STD_LOGIC_ARITH.all;103 --USE IEEE.STD_LOGIC_UNSIGNED.all;104 --LIBRARY FACT_FTM_lib;105 --USE FACT_FTM_lib.ftm_array_types.all;106 --USE FACT_FTM_lib.ftm_constants.all;107 108 --LIBRARY FACT_FTM_lib;109 110 93 ARCHITECTURE beha OF ethernet_modul IS 111 94 … … 113 96 114 97 -- Internal signal declarations 115 SIGNAL busy : std_logic := '1';116 SIGNAL cram_data_out : std_logic_vector(15 DOWNTO 0);117 SIGNAL cram_data_in : std_logic_vector(15 DOWNTO 0);118 SIGNAL cram_we : std_logic_vector(0 DOWNTO 0) := "0";119 SIGNAL sd_write : std_logic := '0';120 SIGNAL sd_read : std_logic;121 SIGNAL led1 : std_logic_vector(7 DOWNTO 0) := (others => '0');122 SIGNAL sd_started : std_logic;123 SIGNAL sd_addr : std_logic_vector(11 DOWNTO 0);124 SIGNAL cram_addr_out : std_logic_vector(11 DOWNTO 0);125 SIGNAL cram_addr_in : std_logic_vector(11 DOWNTO 0);126 SIGNAL sd_data_in : std_logic_vector(15 DOWNTO 0) := (others => '0');127 SIGNAL sd_data_out : std_logic_vector(15 DOWNTO 0);128 SIGNAL config_ready_cc : std_logic := '0';129 SIGNAL config_started_cc : std_logic := '0';130 SIGNAL config_start_cc : std_logic;131 SIGNAL fl_started : std_logic;132 SIGNAL fl_read : std_logic := '0';98 SIGNAL busy : std_logic := '1'; 99 SIGNAL cram_data_out : std_logic_vector(15 DOWNTO 0); 100 SIGNAL cram_data_in : std_logic_vector(15 DOWNTO 0); 101 SIGNAL cram_we : std_logic_vector(0 DOWNTO 0) := "0"; 102 SIGNAL sd_write : std_logic := '0'; 103 SIGNAL sd_read : std_logic; 104 SIGNAL led1 : std_logic_vector(7 DOWNTO 0) := (others => '0'); 105 SIGNAL sd_started : std_logic; 106 SIGNAL sd_addr : std_logic_vector(11 DOWNTO 0); 107 SIGNAL cram_addr_out : std_logic_vector(11 DOWNTO 0); 108 SIGNAL cram_addr_in : std_logic_vector(11 DOWNTO 0); 109 SIGNAL sd_data_in : std_logic_vector(15 DOWNTO 0) := (others => '0'); 110 SIGNAL sd_data_out : std_logic_vector(15 DOWNTO 0); 111 SIGNAL config_ready_cc : std_logic := '0'; 112 SIGNAL config_started_cc : std_logic := '0'; 113 SIGNAL config_start_cc : std_logic; 114 SIGNAL fl_started : std_logic; 115 SIGNAL fl_read : std_logic := '0'; 133 116 -- 134 SIGNAL fl_addr : std_logic_vector(11 DOWNTO 0); 135 SIGNAL fl_data_out : std_logic_vector(15 DOWNTO 0); 136 SIGNAL fram_addr_out : std_logic_vector(11 DOWNTO 0); 137 SIGNAL doutb : std_logic_VECTOR(15 DOWNTO 0); 138 SIGNAL fram_we : std_logic_vector(0 DOWNTO 0) := "0"; 139 SIGNAL fram_addr_in : std_logic_vector(11 DOWNTO 0); 140 SIGNAL fram_data_in : std_logic_vector(15 DOWNTO 0); 141 SIGNAL led2 : std_logic_vector(7 DOWNTO 0) := X"00"; 142 SIGNAL dram_addr_out : std_logic_vector(11 DOWNTO 0); 143 SIGNAL doutb1 : std_logic_VECTOR(15 DOWNTO 0); 144 SIGNAL dram_we : std_logic_vector(0 DOWNTO 0) := "0"; 145 SIGNAL dram_addr_in : std_logic_vector(11 DOWNTO 0); 146 SIGNAL dram_data_in : std_logic_vector(15 DOWNTO 0); 147 SIGNAL dd_read : std_logic; 148 SIGNAL dd_started : std_logic := '0'; 149 SIGNAL dd_data_out : std_logic_vector(15 DOWNTO 0) := (others => '0'); 150 SIGNAL dd_addr : std_logic_vector(11 DOWNTO 0); 151 SIGNAL dd_block_ready : std_logic := '0'; 117 SIGNAL fl_addr : std_logic_vector(11 DOWNTO 0); 118 SIGNAL fl_data_out : std_logic_vector(15 DOWNTO 0); 119 SIGNAL fram_addr_out : std_logic_vector(11 DOWNTO 0); 120 SIGNAL doutb : std_logic_VECTOR(15 DOWNTO 0); 121 SIGNAL fram_we : std_logic_vector(0 DOWNTO 0) := "0"; 122 SIGNAL fram_addr_in : std_logic_vector(11 DOWNTO 0); 123 SIGNAL fram_data_in : std_logic_vector(15 DOWNTO 0); 124 SIGNAL dram_addr_out : std_logic_vector(11 DOWNTO 0); 125 SIGNAL doutb1 : std_logic_VECTOR(15 DOWNTO 0); 126 SIGNAL dram_we : std_logic_vector(0 DOWNTO 0) := "0"; 127 SIGNAL dram_addr_in : std_logic_vector(11 DOWNTO 0); 128 SIGNAL dram_data_in : std_logic_vector(15 DOWNTO 0); 129 SIGNAL dd_read : std_logic; 130 SIGNAL dd_started : std_logic := '0'; 131 SIGNAL dd_data_out : std_logic_vector(15 DOWNTO 0) := (others => '0'); 132 SIGNAL dd_addr : std_logic_vector(11 DOWNTO 0); 133 SIGNAL dd_block_ready : std_logic := '0'; 152 134 -- 153 SIGNAL dd_block_start : std_logic := '0'; 154 SIGNAL dd_block_start_ack : std_logic; 155 SIGNAL dd_block_ready_ftu : std_logic; 156 SIGNAL dd_block_start_ack_ftu : std_logic := '0'; 157 SIGNAL dd_block_start_ftu : std_logic; 135 SIGNAL dd_block_start : std_logic := '0'; 136 SIGNAL dd_block_start_ack : std_logic; 137 SIGNAL dd_write_general : std_logic := '0'; 138 SIGNAL dd_write_general_ready : std_logic; 139 SIGNAL dd_write_general_started : std_logic; 140 SIGNAL dd_write : std_logic := '0'; 141 SIGNAL dd_started_general : std_logic := '0'; 142 SIGNAL dd_addr1 : std_logic_vector(11 DOWNTO 0) := (others => '0'); 143 SIGNAL dd_data : std_logic_vector(15 DOWNTO 0) := (others => '0'); 144 SIGNAL get_header : std_logic; 145 SIGNAL get_header_started : std_logic := '0'; 146 SIGNAL get_header_ready : std_logic := '0'; 147 SIGNAL led2 : std_logic_vector(7 DOWNTO 0); 148 SIGNAL header_board_id : std_logic_vector(63 DOWNTO 0); 149 SIGNAL header_firmware_id : std_logic_vector(15 DOWNTO 0); 150 SIGNAL header_timestamp_counter : std_logic_vector(47 DOWNTO 0); 151 SIGNAL header_trigger_counter : std_logic_vector(31 DOWNTO 0); 158 152 159 153 -- Implicit buffer signal declarations … … 204 198 clk : IN std_logic ; 205 199 led : OUT std_logic_vector (7 DOWNTO 0) := X"00"; 206 cram_data_in : OUT std_logic_vector (15 DOWNTO 0) ;200 cram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 207 201 cram_data_out : IN std_logic_vector (15 DOWNTO 0); 208 cram_addr_in : OUT std_logic_vector (11 DOWNTO 0) ;209 cram_addr_out : OUT std_logic_vector (11 DOWNTO 0) ;202 cram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); 203 cram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); 210 204 cram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; 211 205 sd_write : IN std_logic ; … … 253 247 ); 254 248 END COMPONENT; 249 COMPONENT dd_write_general_modul 250 PORT ( 251 clk : IN std_logic ; 252 dd_write_general : IN std_logic ; 253 dd_write_general_started : OUT std_logic := '0'; 254 dd_write_general_ready : OUT std_logic := '0'; 255 dd_busy : IN std_logic ; 256 dd_write : OUT std_logic := '0'; 257 dd_started : IN std_logic ; 258 dd_ready : IN std_logic ; 259 dd_addr : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); 260 dd_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') 261 ); 262 END COMPONENT; 255 263 COMPONENT dram_control 256 264 PORT ( 257 265 clk : IN std_logic ; 258 dram_data_in : OUT std_logic_vector (15 DOWNTO 0) ;266 dram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 259 267 dram_data_out : IN std_logic_vector (15 DOWNTO 0); 260 dram_addr_in : OUT std_logic_vector (11 DOWNTO 0) ;261 dram_addr_out : OUT std_logic_vector (11 DOWNTO 0) ;268 dram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); 269 dram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); 262 270 dram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; 263 271 dd_block_start : IN std_logic ; … … 269 277 dd_read : IN std_logic ; 270 278 dd_write_ftu : IN std_logic ; 279 dd_write_general : IN std_logic ; 271 280 dd_busy : OUT std_logic := '1'; 272 281 dd_started : OUT std_logic := '0'; 273 282 dd_started_ftu : OUT std_logic := '0'; 283 dd_started_general : OUT std_logic := '0'; 274 284 dd_ready : OUT std_logic := '0'; 275 285 dd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 276 286 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); 287 dd_data_in_general : IN std_logic_vector (15 DOWNTO 0); 277 288 dd_addr : IN std_logic_vector (11 DOWNTO 0); 278 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0) 289 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); 290 dd_addr_general : IN std_logic_vector (11 DOWNTO 0) 279 291 ); 280 292 END COMPONENT; … … 293 305 PORT ( 294 306 clk : IN std_logic ; 295 fram_data_in : OUT std_logic_vector (15 DOWNTO 0) ;307 fram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 296 308 fram_data_out : IN std_logic_vector (15 DOWNTO 0); 297 fram_addr_in : OUT std_logic_vector (11 DOWNTO 0) ;298 fram_addr_out : OUT std_logic_vector (11 DOWNTO 0) ;309 fram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); 310 fram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); 299 311 fram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; 300 312 fl_read : IN std_logic ; … … 310 322 ); 311 323 END COMPONENT; 324 COMPONENT header_modul 325 PORT ( 326 clk : IN std_logic ; 327 get_header : IN std_logic ; 328 get_header_started : OUT std_logic := '0'; 329 get_header_ready : OUT std_logic := '0'; 330 header_board_id : OUT std_logic_vector (63 DOWNTO 0) := (others => '0'); 331 header_firmware_id : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 332 header_trigger_counter : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); 333 header_timestamp_counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0') 334 ); 335 END COMPONENT; 312 336 COMPONENT w5300_modul 313 337 PORT ( 314 clk : IN std_logic ;315 wiz_reset : OUT std_logic := '1';316 addr : OUT std_logic_vector (9 DOWNTO 0);317 data : INOUT std_logic_vector (15 DOWNTO 0);318 cs : OUT std_logic := '1';319 wr : OUT std_logic := '1';320 led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');321 rd : OUT std_logic := '1';322 int : IN std_logic ;323 busy : OUT std_logic := '1';324 new_config : OUT std_logic := '0';325 config_started : IN std_logic ;326 config_started_ack : OUT std_logic := '0';338 clk : IN std_logic ; 339 wiz_reset : OUT std_logic := '1'; 340 addr : OUT std_logic_vector (9 DOWNTO 0); 341 data : INOUT std_logic_vector (15 DOWNTO 0); 342 cs : OUT std_logic := '1'; 343 wr : OUT std_logic := '1'; 344 led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); 345 rd : OUT std_logic := '1'; 346 int : IN std_logic ; 347 busy : OUT std_logic := '1'; 348 new_config : OUT std_logic := '0'; 349 config_started : IN std_logic ; 350 config_started_ack : OUT std_logic := '0'; 327 351 -- 328 ping_ftu_start : OUT std_logic := '0';329 ping_ftu_started : IN std_logic ;330 ping_ftu_ready : IN std_logic ;352 ping_ftu_start : OUT std_logic := '0'; 353 ping_ftu_started : IN std_logic ; 354 ping_ftu_ready : IN std_logic ; 331 355 -- 332 sd_addr : OUT std_logic_vector (11 DOWNTO 0);333 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');334 sd_data_in : IN std_logic_vector (15 DOWNTO 0);335 sd_write : OUT std_logic := '0';336 sd_read : OUT std_logic := '0';337 sd_started : IN std_logic ;338 sd_ready : IN std_logic ;339 sd_busy : IN std_logic ;356 sd_addr : OUT std_logic_vector (11 DOWNTO 0); 357 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 358 sd_data_in : IN std_logic_vector (15 DOWNTO 0); 359 sd_write : OUT std_logic := '0'; 360 sd_read : OUT std_logic := '0'; 361 sd_started : IN std_logic ; 362 sd_ready : IN std_logic ; 363 sd_busy : IN std_logic ; 340 364 -- 341 dd_block_start : OUT std_logic := '0'; 342 dd_block_start_ack : IN std_logic ; 343 dd_block_ready : OUT std_logic := '0'; 344 dd_addr : OUT std_logic_vector (11 DOWNTO 0); 345 dd_data_in : IN std_logic_vector (15 DOWNTO 0); 346 dd_read : OUT std_logic := '0'; 347 dd_started : IN std_logic ; 348 dd_ready : IN std_logic ; 349 dd_busy : IN std_logic ; 365 dd_block_start : OUT std_logic := '0'; 366 dd_block_start_ack : IN std_logic ; 367 dd_block_ready : OUT std_logic := '1'; 368 dd_send : IN std_logic ; 369 dd_send_ack : OUT std_logic := '1'; 370 dd_send_ready : OUT std_logic := '1'; 371 dd_addr : OUT std_logic_vector (11 DOWNTO 0); 372 dd_data_in : IN std_logic_vector (15 DOWNTO 0); 373 dd_read : OUT std_logic := '0'; 374 dd_started : IN std_logic ; 375 dd_ready : IN std_logic ; 376 dd_busy : IN std_logic ; 377 dd_write_general : OUT std_logic := '0'; 378 dd_write_general_started : IN std_logic ; 379 dd_write_general_ready : IN std_logic ; 350 380 -- 351 fl_addr : OUT std_logic_vector (11 DOWNTO 0); 352 fl_data_in : IN std_logic_vector (15 DOWNTO 0); 353 fl_read : OUT std_logic := '0'; 354 fl_started : IN std_logic ; 355 fl_ready : IN std_logic ; 356 fl_busy : IN std_logic 381 fl_addr : OUT std_logic_vector (11 DOWNTO 0); 382 fl_data_in : IN std_logic_vector (15 DOWNTO 0); 383 fl_read : OUT std_logic := '0'; 384 fl_started : IN std_logic ; 385 fl_ready : IN std_logic ; 386 fl_busy : IN std_logic ; 387 -- 388 get_header : OUT std_logic := '0'; 389 get_header_started : IN std_logic ; 390 get_header_ready : IN std_logic ; 391 header_board_id : IN std_logic_vector (63 DOWNTO 0); 392 header_firmware_id : IN std_logic_vector (15 DOWNTO 0); 393 header_trigger_counter : IN std_logic_vector (31 DOWNTO 0); 394 header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0) 357 395 ); 358 396 END COMPONENT; … … 364 402 -- FOR ALL : FRAM_4096_16b USE ENTITY FACT_FTM_lib.FRAM_4096_16b; 365 403 -- FOR ALL : cram_control USE ENTITY FACT_FTM_lib.cram_control; 404 -- FOR ALL : dd_write_general_modul USE ENTITY FACT_FTM_lib.dd_write_general_modul; 366 405 -- FOR ALL : dram_control USE ENTITY FACT_FTM_lib.dram_control; 367 406 -- FOR ALL : eth_config_modul USE ENTITY FACT_FTM_lib.eth_config_modul; 368 407 -- FOR ALL : fram_control USE ENTITY FACT_FTM_lib.fram_control; 408 -- FOR ALL : header_modul USE ENTITY FACT_FTM_lib.header_modul; 369 409 -- FOR ALL : w5300_modul USE ENTITY FACT_FTM_lib.w5300_modul; 370 410 -- pragma synthesis_on 371 372 411 373 412 BEGIN … … 458 497 ftu_active_cr3 => ftu_active_cr3 459 498 ); 499 U_9 : dd_write_general_modul 500 PORT MAP ( 501 clk => clk, 502 dd_write_general => dd_write_general, 503 dd_write_general_started => dd_write_general_started, 504 dd_write_general_ready => dd_write_general_ready, 505 dd_busy => dd_busy_internal, 506 dd_write => dd_write, 507 dd_started => dd_started_general, 508 dd_ready => dd_ready_internal, 509 dd_addr => dd_addr1, 510 dd_data => dd_data 511 ); 460 512 U_8 : dram_control 461 513 PORT MAP ( … … 474 526 dd_read => dd_read, 475 527 dd_write_ftu => dd_write_ftu, 528 dd_write_general => dd_write, 476 529 dd_busy => dd_busy_internal, 477 530 dd_started => dd_started, 478 531 dd_started_ftu => dd_started_ftu, 532 dd_started_general => dd_started_general, 479 533 dd_ready => dd_ready_internal, 480 534 dd_data_out => dd_data_out, 481 535 dd_data_in_ftu => dd_data_in_ftu, 536 dd_data_in_general => dd_data, 482 537 dd_addr => dd_addr, 483 dd_addr_ftu => dd_addr_ftu 538 dd_addr_ftu => dd_addr_ftu, 539 dd_addr_general => dd_addr1 484 540 ); 485 541 U_4 : eth_config_modul … … 512 568 fl_addr_ftu => fl_addr_ftu 513 569 ); 570 U_10 : header_modul 571 PORT MAP ( 572 clk => clk, 573 get_header => get_header, 574 get_header_started => get_header_started, 575 get_header_ready => get_header_ready, 576 header_board_id => header_board_id, 577 header_firmware_id => header_firmware_id, 578 header_trigger_counter => header_trigger_counter, 579 header_timestamp_counter => header_timestamp_counter 580 ); 514 581 U_0 : w5300_modul 515 582 PORT MAP ( 516 clk => clk, 517 wiz_reset => wiz_reset, 518 addr => wiz_addr, 519 data => wiz_data, 520 cs => wiz_cs, 521 wr => wiz_wr, 522 led => led1, 523 rd => wiz_rd, 524 int => wiz_int, 525 busy => busy, 526 new_config => new_config, 527 config_started => config_started, 528 config_started_ack => config_started_ack, 529 ping_ftu_start => ping_ftu_start, 530 ping_ftu_started => ping_ftu_started, 531 ping_ftu_ready => ping_ftu_ready, 532 sd_addr => sd_addr, 533 sd_data_out => sd_data_in, 534 sd_data_in => sd_data_out, 535 sd_write => sd_write, 536 sd_read => sd_read, 537 sd_started => sd_started, 538 sd_ready => sd_ready_internal, 539 sd_busy => sd_busy_internal, 540 dd_block_start => dd_block_start, 541 dd_block_start_ack => dd_block_start_ack, 542 dd_block_ready => dd_block_ready, 543 dd_addr => dd_addr, 544 dd_data_in => dd_data_out, 545 dd_read => dd_read, 546 dd_started => dd_started, 547 dd_ready => dd_ready_internal, 548 dd_busy => dd_busy_internal, 549 fl_addr => fl_addr, 550 fl_data_in => fl_data_out, 551 fl_read => fl_read, 552 fl_started => fl_started, 553 fl_ready => fl_ready_internal, 554 fl_busy => fl_busy_internal 583 clk => clk, 584 wiz_reset => wiz_reset, 585 addr => wiz_addr, 586 data => wiz_data, 587 cs => wiz_cs, 588 wr => wiz_wr, 589 led => led1, 590 rd => wiz_rd, 591 int => wiz_int, 592 busy => busy, 593 new_config => new_config, 594 config_started => config_started, 595 config_started_ack => config_started_ack, 596 ping_ftu_start => ping_ftu_start, 597 ping_ftu_started => ping_ftu_started, 598 ping_ftu_ready => ping_ftu_ready, 599 sd_addr => sd_addr, 600 sd_data_out => sd_data_in, 601 sd_data_in => sd_data_out, 602 sd_write => sd_write, 603 sd_read => sd_read, 604 sd_started => sd_started, 605 sd_ready => sd_ready_internal, 606 sd_busy => sd_busy_internal, 607 dd_block_start => dd_block_start, 608 dd_block_start_ack => dd_block_start_ack, 609 dd_block_ready => dd_block_ready, 610 dd_send => dd_send, 611 dd_send_ack => dd_send_ack, 612 dd_send_ready => dd_send_ready, 613 dd_addr => dd_addr, 614 dd_data_in => dd_data_out, 615 dd_read => dd_read, 616 dd_started => dd_started, 617 dd_ready => dd_ready_internal, 618 dd_busy => dd_busy_internal, 619 dd_write_general => dd_write_general, 620 dd_write_general_started => dd_write_general_started, 621 dd_write_general_ready => dd_write_general_ready, 622 fl_addr => fl_addr, 623 fl_data_in => fl_data_out, 624 fl_read => fl_read, 625 fl_started => fl_started, 626 fl_ready => fl_ready_internal, 627 fl_busy => fl_busy_internal, 628 get_header => get_header, 629 get_header_started => get_header_started, 630 get_header_ready => get_header_ready, 631 header_board_id => header_board_id, 632 header_firmware_id => header_firmware_id, 633 header_trigger_counter => header_trigger_counter, 634 header_timestamp_counter => header_timestamp_counter 555 635 ); 556 636 -
firmware/FTM/ethernet/fram_control_beha.vhd
r10227 r10256 8 8 -- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) 9 9 -- 10 10 11 LIBRARY ieee; 11 12 USE ieee.std_logic_1164.all; … … 20 21 21 22 ENTITY fram_control IS 22 23 24 fram_data_in : OUT std_logic_vector (15 DOWNTO 0);25 26 fram_addr_in : OUT std_logic_vector (11 DOWNTO 0);27 fram_addr_out : OUT std_logic_vector (11 DOWNTO 0);28 29 30 31 32 33 34 35 36 37 38 39 23 PORT( 24 clk : IN std_logic; 25 fram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 26 fram_data_out : IN std_logic_vector (15 DOWNTO 0); 27 fram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); 28 fram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); 29 fram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; 30 fl_read : IN std_logic; 31 fl_write_ftu : IN std_logic; 32 fl_busy : OUT std_logic := '1'; 33 fl_started : OUT std_logic := '0'; 34 fl_started_ftu : OUT std_logic := '0'; 35 fl_ready : OUT std_logic := '0'; 36 fl_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 37 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); 38 fl_addr : IN std_logic_vector (11 DOWNTO 0); 39 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0) 40 ); 40 41 41 42 -- Declarations … … 113 114 when FR_WRITE_END => 114 115 fram_we <= "0"; 115 fl_started_ftu <= '0'; 116 fl_ready <= '1'; 117 state_fram_proc <= next_state; 116 if (fl_write_ftu = '0') then 117 fl_started_ftu <= '0'; 118 fl_ready <= '1'; 119 state_fram_proc <= next_state; 120 end if; 118 121 119 122 -- -- -
firmware/FTM/ethernet/w5300_modul.vhd
r10227 r10256 18 18 -- 19 19 ---------------------------------------------------------------------------------- 20 -- hds interface_start 20 21 21 LIBRARY IEEE; 22 22 USE IEEE.STD_LOGIC_1164.all; … … 30 30 USE ftm_definitions.ftm_constants.all; 31 31 32 -- --Uncomment the following library declaration if instantiating33 -- --any Xilinx primitives in this code.34 35 36 37 -- 32 -- Uncomment the following library declaration if instantiating 33 -- any Xilinx primitives in this code. 34 library UNISIM; 35 use UNISIM.VComponents.all; 36 37 38 38 ENTITY w5300_modul IS 39 PORT( 40 clk : IN std_logic; 41 wiz_reset : OUT std_logic := '1'; 42 addr : OUT std_logic_vector (9 DOWNTO 0); 43 data : INOUT std_logic_vector (15 DOWNTO 0); 44 cs : OUT std_logic := '1'; 45 wr : OUT std_logic := '1'; 46 led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); 47 rd : OUT std_logic := '1'; 48 int : IN std_logic; 49 busy : OUT std_logic := '1'; 50 new_config : OUT std_logic := '0'; 51 config_started : IN std_logic; 52 config_started_ack : OUT std_logic := '0'; 53 -- 54 ping_ftu_start : OUT std_logic := '0'; 55 ping_ftu_started : IN std_logic; 56 ping_ftu_ready : IN std_logic; 57 -- 58 sd_addr : OUT std_logic_vector (11 DOWNTO 0); 59 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 60 sd_data_in : IN std_logic_vector (15 DOWNTO 0); 61 sd_write : OUT std_logic := '0'; 62 sd_read : OUT std_logic := '0'; 63 sd_started : IN std_logic; 64 sd_ready : IN std_logic; 65 sd_busy : IN std_logic; 66 -- 67 dd_block_start : OUT std_logic := '0'; 68 dd_block_start_ack : IN std_logic; 69 dd_block_ready : OUT std_logic := '0'; 70 dd_addr : OUT std_logic_vector (11 DOWNTO 0); 71 dd_data_in : IN std_logic_vector (15 DOWNTO 0); 72 dd_read : OUT std_logic := '0'; 73 dd_started : IN std_logic; 74 dd_ready : IN std_logic; 75 dd_busy : IN std_logic; 76 -- 77 fl_addr : OUT std_logic_vector (11 DOWNTO 0); 78 fl_data_in : IN std_logic_vector (15 DOWNTO 0); 79 fl_read : OUT std_logic := '0'; 80 fl_started : IN std_logic; 81 fl_ready : IN std_logic; 82 fl_busy : IN std_logic 83 ); 84 85 -- Declarations 39 PORT( 40 clk : IN std_logic; 41 wiz_reset : OUT std_logic := '1'; 42 addr : OUT std_logic_vector (9 DOWNTO 0); 43 data : INOUT std_logic_vector (15 DOWNTO 0); 44 cs : OUT std_logic := '1'; 45 wr : OUT std_logic := '1'; 46 led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); 47 rd : OUT std_logic := '1'; 48 int : IN std_logic; 49 busy : OUT std_logic := '1'; 50 new_config : OUT std_logic := '0'; 51 config_started : IN std_logic; 52 config_started_ack : OUT std_logic := '0'; 53 -- 54 ping_ftu_start : OUT std_logic := '0'; 55 ping_ftu_started : IN std_logic; 56 ping_ftu_ready : IN std_logic; 57 -- 58 sd_addr : OUT std_logic_vector (11 DOWNTO 0); 59 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 60 sd_data_in : IN std_logic_vector (15 DOWNTO 0); 61 sd_write : OUT std_logic := '0'; 62 sd_read : OUT std_logic := '0'; 63 sd_started : IN std_logic; 64 sd_ready : IN std_logic; 65 sd_busy : IN std_logic; 66 -- 67 dd_block_start : OUT std_logic := '0'; 68 dd_block_start_ack : IN std_logic; 69 dd_block_ready : OUT std_logic := '1'; 70 dd_send : IN std_logic; 71 dd_send_ack : OUT std_logic := '1'; 72 dd_send_ready : OUT std_logic := '1'; 73 dd_addr : OUT std_logic_vector (11 DOWNTO 0); 74 dd_data_in : IN std_logic_vector (15 DOWNTO 0); 75 dd_read : OUT std_logic := '0'; 76 dd_started : IN std_logic; 77 dd_ready : IN std_logic; 78 dd_busy : IN std_logic; 79 dd_write_general : OUT std_logic := '0'; 80 dd_write_general_started : IN std_logic; 81 dd_write_general_ready : IN std_logic; 82 -- 83 fl_addr : OUT std_logic_vector (11 DOWNTO 0); 84 fl_data_in : IN std_logic_vector (15 DOWNTO 0); 85 fl_read : OUT std_logic := '0'; 86 fl_started : IN std_logic; 87 fl_ready : IN std_logic; 88 fl_busy : IN std_logic; 89 -- 90 get_header : OUT std_logic := '0'; 91 get_header_started : IN std_logic; 92 get_header_ready : IN std_logic; 93 header_board_id : IN std_logic_vector (63 DOWNTO 0); 94 header_firmware_id : IN std_logic_vector (15 DOWNTO 0); 95 header_trigger_counter : IN std_logic_vector (31 DOWNTO 0); 96 header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0) 97 ); 86 98 87 99 END w5300_modul ; 88 -- hds interface_end89 100 90 101 architecture Behavioral of w5300_modul is … … 93 104 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 94 105 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, 95 READ_DATA, WRITE_TO_SD_ADDR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR); 96 type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO_01); 106 READ_DATA, WRITE_TO_SD_ADDR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL); 107 type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, 108 WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01); 97 109 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); 98 110 type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); … … 103 115 type state_ping_type is (PING_START, PING_WAIT, PING_WRITE_LIST); 104 116 type state_read_dd_type is (READ_DD_START, READ_DD_WAIT, READ_DD_END); 105 type state_read_dd_block_type is (READ_DD_BLOCK_START, READ_DD_BLOCK_WRITE , READ_DD_BLOCK_END);117 type state_read_dd_block_type is (READ_DD_BLOCK_START, READ_DD_BLOCK_WRITE_GENERAL, READ_DD_BLOCK_WRITE, READ_DD_BLOCK_END, READ_DD_BLOCK_INTERN); 106 118 107 119 signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; … … 132 144 signal zaehler : std_logic_vector (19 downto 0) := (others => '0'); 133 145 signal data_cnt : integer := 0; 146 signal header_cnt : integer := 0; 134 147 signal socket_cnt : std_logic_vector (2 downto 0) := "000"; 135 148 … … 149 162 type cmd_array_type is array (0 to 4) of std_logic_vector (15 downto 0); 150 163 signal cmd_array : cmd_array_type; 164 signal internal_cmd : std_logic := '0'; 151 165 152 166 -- -- -- … … 199 213 if int_flag = '0' then 200 214 case state_init is 201 215 -- Interrupt 202 216 when INTERRUPT => 203 217 case state_interrupt_2 is … … 248 262 end case; 249 263 250 264 -- reset W5300 251 265 when RESET => 252 266 busy <= '1'; … … 264 278 wr <= '1'; 265 279 cs <= '1'; 266 state_write <= WR_START; 267 state_init <= INIT; 280 -- reset states 281 state_write <= WR_START; 282 state_init <= INIT; 283 state_read_data <= RD_1; 284 next_state_read_data <= RD_CMD; 285 state_write_sd <= WRITE_SD_START; 286 state_read_sd <= READ_SD_START; 287 state_read_fl <= READ_FL_START; 288 state_ping <= PING_START; 289 state_read_dd <= READ_DD_START; 290 state_read_dd_block <= READ_DD_BLOCK_START; 291 -- reset output signals 292 new_config <= '0'; 293 config_started_ack <= '1'; 294 ping_ftu_start <= '0'; 295 sd_write <= '0'; 296 sd_read <= '0'; 297 dd_block_start <= '0'; 298 dd_block_ready <= '1'; 299 dd_send_ack <= '1'; 300 dd_send_ready <= '1'; 301 dd_read <= '0'; 302 dd_write_general <= '0'; 303 fl_read <= '0'; 304 -- set internal signals 305 new_config_flag <= '0'; 306 chk_recv_cntr <= 0; 307 next_packet_data_cnt <= 0; 308 internal_cmd <= '0'; 268 309 -- -- -- 269 310 led_int <= X"00"; … … 448 489 state_init <= MAIN; 449 490 -- -- -- 491 config_started_ack <= '0'; 492 dd_block_ready <= '0'; 493 dd_send_ack <= '0'; 494 dd_send_ready <= '0'; 450 495 led_int <= X"00"; 451 496 -- -- -- … … 481 526 end if; 482 527 483 528 -- main "loop" 484 529 when MAIN => 530 chk_recv_cntr <= chk_recv_cntr + 1; 485 531 if (chk_recv_cntr = 1000) then 486 532 chk_recv_cntr <= 0; … … 488 534 state_init <= READ_DATA; 489 535 busy <= '1'; 490 else 491 chk_recv_cntr <= chk_recv_cntr + 1; 536 elsif (dd_send = '1') then 537 internal_cmd <= '1'; 538 dd_send_ack <= '1'; 539 dd_send_ready <= '0'; 540 -- "simulate" command read dynamic data block 541 cmd_array (0) <= CMD_START_DELIMITER; 542 cmd_array (1) <= CMD_READ; 543 cmd_array (2) <= PAR_READ_DD; 544 state_read_data <= RD_CMD_PARSE; 545 state_init <= READ_DATA; 492 546 end if; 493 547 494 548 495 549 -- read data from socket 0 496 550 when READ_DATA => 497 551 case state_read_data is … … 529 583 end if; 530 584 585 when RD_END => 586 if (internal_cmd = '0') then 587 par_addr <= W5300_S0_CR; 588 par_data <= X"0040"; -- RECV 589 state_init <= WRITE_REG; 590 else 591 internal_cmd <= '0'; 592 end if; 593 if (new_config_flag = '1') then 594 new_config_flag <= '0'; 595 next_state <= CONFIG; 596 else 597 next_state <= MAIN; 598 end if; 599 531 600 532 601 ------------------------- … … 585 654 when PAR_READ_SD => 586 655 state_read_data <= RD_READ_SD_BLOCK; 587 when PAR_READ_DD => 588 state_read_data <= RD_READ_DD_BLOCK; 656 -- read dynamic data block 657 when PAR_READ_DD => 658 state_read_data <= RD_READ_DD_BLOCK; 589 659 when others => 590 660 state_read_data <= RD_5; … … 626 696 -- read dynamic data block and write it to ethernet 627 697 when RD_READ_DD_BLOCK => 628 case state_read_dd_block is 629 when READ_DD_BLOCK_START => 630 dd_block_start <= '1'; 631 dd_block_ready <= '0'; 632 if (dd_block_start_ack = '1') then 633 dd_block_start <= '0'; 634 state_read_dd_block <= READ_DD_BLOCK_WRITE; 635 end if; 636 when READ_DD_BLOCK_WRITE => 637 read_addr_state <= READ_FROM_DD_ADDR; 638 local_sd_addr <= X"000"; -- start at address 0x000 639 local_write_length <= "00000" & DD_BLOCK_SIZE; 640 state_read_dd_block <= READ_DD_BLOCK_END; 641 next_state <= READ_DATA; 642 state_init <= WRITE_DATA; 643 when READ_DD_BLOCK_END => 644 dd_block_ready <= '1'; 645 state_read_dd_block <= READ_DD_BLOCK_START; 646 state_read_data <= RD_5; 647 next_state_read_data <= RD_CMD; 648 end case; 649 650 -- read static data block and write it to ethernet 698 case state_read_dd_block is 699 when READ_DD_BLOCK_START => 700 dd_block_start <= '1'; 701 dd_block_ready <= '0'; 702 if (dd_block_start_ack = '1') then 703 dd_block_start <= '0'; 704 state_read_dd_block <= READ_DD_BLOCK_WRITE_GENERAL; 705 end if; 706 -- write on-time counter and tempertures to dd-block 707 when READ_DD_BLOCK_WRITE_GENERAL => 708 dd_write_general <= '1'; 709 if (dd_write_general_started = '1') then 710 dd_write_general <= '0'; 711 state_read_dd_block <= READ_DD_BLOCK_WRITE; 712 end if; 713 -- write dd-block to ethernet when on-time counter and temperatures are ready 714 when READ_DD_BLOCK_WRITE => 715 if (dd_write_general_ready = '1') then 716 read_addr_state <= READ_FROM_DD_ADDR; 717 local_sd_addr <= X"000"; -- start at address 0x000 718 local_write_length <= "00000" & DD_BLOCK_SIZE; 719 state_read_dd_block <= READ_DD_BLOCK_END; 720 next_state <= READ_DATA; 721 state_init <= WRITE_DATA; 722 end if; 723 when READ_DD_BLOCK_END => 724 dd_block_ready <= '1'; 725 next_state_read_data <= RD_CMD; 726 -- 727 if (internal_cmd = '1') then 728 state_read_dd_block <= READ_DD_BLOCK_INTERN; 729 else 730 state_read_dd_block <= READ_DD_BLOCK_START; 731 state_read_data <= RD_5; 732 end if; 733 when READ_DD_BLOCK_INTERN => 734 if (dd_send = '0') then 735 dd_send_ready <= '1'; 736 dd_send_ack <= '0'; 737 state_read_dd_block <= READ_DD_BLOCK_START; 738 state_read_data <= RD_5; 739 end if; 740 741 end case; 742 743 -- read static data block and write it to ethernet 651 744 when RD_READ_SD_BLOCK => 652 745 state_read_data <= RD_5; … … 695 788 state_init <= WRITE_TO_SD_ADDR; 696 789 end if; 697 698 699 -------------------------700 -------------------------701 702 703 when RD_END =>704 par_addr <= W5300_S0_CR;705 par_data <= X"0040"; -- RECV706 state_init <= WRITE_REG;707 if (new_config_flag = '1') then708 new_config_flag <= '0';709 next_state <= CONFIG;710 else711 next_state <= MAIN;712 end if;713 790 714 791 end case; -- state_read_data 715 792 716 793 794 -- read from header modul 795 when READ_FROM_HEADER_MODUL => 796 state_init <= next_state; 797 case header_cnt is 798 when 0 => 799 local_sd_data <= header_board_id (63 DOWNTO 48); 800 when 1 => 801 local_sd_data <= header_board_id (47 DOWNTO 32); 802 when 2 => 803 local_sd_data <= header_board_id (31 DOWNTO 16); 804 when 3 => 805 local_sd_data <= header_board_id (15 DOWNTO 0); 806 when 4 => 807 local_sd_data <= header_firmware_id; 808 when 5 => 809 local_sd_data <= header_trigger_counter (31 DOWNTO 16); 810 when 6 => 811 local_sd_data <= header_trigger_counter (15 DOWNTO 0); 812 when 7 => 813 local_sd_data <= header_timestamp_counter (47 DOWNTO 32); 814 when 8 => 815 local_sd_data <= header_timestamp_counter (31 DOWNTO 16); 816 when 9 => 817 local_sd_data <= header_timestamp_counter (15 DOWNTO 0); 818 when 10 => 819 local_sd_data <= X"FFFF"; -- spare 820 when others => 821 null; 822 end case; 823 717 824 -- read from ftu list ram 718 825 when READ_FROM_FL_ADDR => … … 803 910 end case; 804 911 805 806 912 -- write to ethernet interface 807 913 when WRITE_DATA => 808 914 case state_write is … … 812 918 local_socket_nr <= "000"; 813 919 next_state_tmp <= next_state; 814 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2)920 write_length_bytes <= (FTM_HEADER_LENGTH + local_write_length (15 downto 0)) & '0'; -- shift left (*2) 815 921 data_cnt <= 0; 922 header_cnt <= 0; 816 923 state_write <= WR_01; 817 924 -- Check FIFO Size 818 925 when WR_01 => 819 926 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC; … … 834 941 state_write <= WR_01; 835 942 else 836 state_write <= WR_FIFO; 837 end if; 838 839 -- Fill FIFO 840 when WR_FIFO => 943 state_write <= WR_GET_HEADER; 944 end if; 945 946 -- get header data 947 when WR_GET_HEADER => 948 get_header <= '1'; 949 if (get_header_started = '1') then 950 get_header <= '0'; 951 state_write <= WR_GET_HEADER_WAIT; 952 end if; 953 954 when WR_GET_HEADER_WAIT => 955 if (get_header_ready = '1') then 956 state_write <= WR_FIFO_HEADER; 957 end if; 958 959 -- Fill FIFO 960 when WR_FIFO_HEADER => 961 state_init <= READ_FROM_HEADER_MODUL; 962 next_state <= WRITE_DATA; 963 state_write <= WR_FIFO_HEADER_01; 964 965 when WR_FIFO_HEADER_01 => 966 header_cnt <= header_cnt + 1; 967 if (header_cnt < FTM_HEADER_LENGTH) then 968 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 969 par_data <= local_sd_data; 970 state_init <= WRITE_REG; 971 next_state <= WRITE_DATA; 972 state_write <= WR_FIFO_HEADER; 973 else 974 state_write <= WR_FIFO_DATA; 975 end if; 976 977 when WR_FIFO_DATA => 841 978 state_init <= read_addr_state; 842 979 next_state <= WRITE_DATA; 843 state_write <= WR_FIFO_ 01;844 845 when WR_FIFO_ 01 =>980 state_write <= WR_FIFO_DATA_01; 981 982 when WR_FIFO_DATA_01 => 846 983 data_cnt <= data_cnt + 1; 847 984 if (data_cnt < local_write_length) then … … 851 988 state_init <= WRITE_REG; 852 989 next_state <= WRITE_DATA; 853 state_write <= WR_FIFO ;990 state_write <= WR_FIFO_DATA; 854 991 else 855 992 state_write <= WR_05; 856 993 end if; 857 994 858 --Send FIFO995 -- Send FIFO 859 996 when WR_05 => 860 997 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
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