Changeset 10462
- Timestamp:
- 04/26/11 16:40:29 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 3 added
- 5 edited
-
FAD_rs485_interface.vhd (added)
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FAD_rs485_receiver.vhd (added)
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data_generator.vhd (modified) (9 diffs)
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fad_board_struct.vhd (modified) (11 diffs)
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fad_definitions.vhd (modified) (1 diff)
-
fad_main_struct.vhd (modified) (19 diffs)
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fad_rs485_definitions.vhd (added)
-
w5300_modul.vhd (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10225 r10462 54 54 FTM_RS485_ready : in std_logic; 55 55 FTM_trigger_info : in std_logic_vector (55 downto 0); --7 byte 56 FTM_receiver_status : in std_logic; 56 57 57 58 -- EVT HEADER - part 3 … … 98 99 drs_s_cell_array : in drs_s_cell_array_type; 99 100 100 drs_readout_started : out std_logic := '0' 101 drs_readout_started : out std_logic := '0'; 102 trigger_veto : out std_logic := '1' 101 103 ); 102 104 end data_generator ; … … 119 121 WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_FILLING, 120 122 WAIT_FOR_ADC, WRITE_ADC_DATA, 121 W RITE_EXTERNAL_TRIGGER,123 WAIT_FOR_EXTERNAL_TRIGGER_READY, WRITE_EXTERNAL_TRIGGER, 122 124 WRITE_END_FLAG, 123 125 WRITE_DATA_END, WRITE_DATA_END_WAIT, … … 148 150 signal sig_drs_readout_started : std_logic := '0'; 149 151 150 152 signal FTM_trigger_info_local_copy : std_logic_vector (55 downto 0) := (others => '0'); --7 byte 151 153 152 154 -- self configuration signals: … … 213 215 when IDLE => 214 216 state_generate <= IDLE; 215 217 trigger_veto <= '0'; 216 218 if (config_start_sig = '1') then 217 219 config_start_sig <= '0'; … … 221 223 if (ram_write_ea = '1' and trigger_sr = "01") then 222 224 sig_drs_readout_started <= '1'; -- is set to '0' in next state ... just a pulse. 225 trigger_veto <= '1'; 223 226 start_read_drs_stop_cell <= '1'; 224 227 adc_output_enable_inverted <= '0'; … … 385 388 when WRITE_ADC_DATA => 386 389 if (data_cntr < roi_max_int (channel_id)) then 387 data_out <= "000" & adc_otr(3) & adc_data_array(3) & --exchange ... with data_cntr when testbenching. 388 "000" & adc_otr(2) & adc_data_array(2) & 389 "000" & adc_otr(1) & adc_data_array(1) & 390 "000" & adc_otr(0) & adc_data_array(0); 390 data_out <= adc_data_array(3)(7 downto 0) & "000" & adc_otr(3) & adc_data_array(3)(11 downto 8) & 391 adc_data_array(2)(7 downto 0) & "000" & adc_otr(2) & adc_data_array(2)(11 downto 8) & 392 adc_data_array(1)(7 downto 0) & "000" & adc_otr(1) & adc_data_array(1)(11 downto 8) & 393 adc_data_array(0)(7 downto 0) & "000" & adc_otr(0) & adc_data_array(0)(11 downto 8) ; 394 391 395 addr_cntr <= addr_cntr + 1; 392 396 state_generate <= WRITE_ADC_DATA; … … 396 400 --adc_output_enable_inverted <= '1'; -- nur für Emulator 397 401 if (channel_id = 8) then 398 state_generate <= W RITE_EXTERNAL_TRIGGER;402 state_generate <= WAIT_FOR_EXTERNAL_TRIGGER_READY; 399 403 adc_output_enable_inverted <= '1'; 400 404 -- switch off ADC_CLK … … 406 410 end if; 407 411 end if; 408 412 413 when WAIT_FOR_EXTERNAL_TRIGGER_READY => 414 state_generate <= WAIT_FOR_EXTERNAL_TRIGGER_READY; 415 if (FTM_RS485_ready = '1') then 416 --make local copy and proceed 417 FTM_trigger_info_local_copy <= FTM_trigger_info; 418 state_generate <= WRITE_EXTERNAL_TRIGGER; 419 end if; 420 421 409 422 when WRITE_EXTERNAL_TRIGGER => -- external trigger ID 410 423 addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH); 411 data_out <= FTM_trigger_info (15 downto 0) &412 FTM_trigger_info (31 downto 16) &413 FTM_trigger_info (47 downto 32) &414 X"00" & FTM_trigger_info(55 downto 48);424 data_out <= FTM_trigger_info_local_copy(15 downto 0) & 425 FTM_trigger_info_local_copy(31 downto 16) & 426 FTM_trigger_info_local_copy(47 downto 32) & 427 "0000000"& FTM_receiver_status & FTM_trigger_info_local_copy(55 downto 48); 415 428 state_generate <= WRITE_END_FLAG; 416 429 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10225 r10462 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 08:30:59 04.03.20115 -- at - 17:31:46 26.04.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 76 76 -- Created: 77 77 -- by - daqct3.UNKNOWN (IHP110) 78 -- at - 08:30:59 04.03.201178 -- at - 17:31:46 26.04.2011 79 79 -- 80 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 116 116 CLK : IN std_logic ; 117 117 D_T_in : IN std_logic_vector (1 DOWNTO 0); 118 FTM_RS485_rx_d : IN std_logic ; 118 119 SROUT_in_0 : IN std_logic ; 119 120 SROUT_in_1 : IN std_logic ; … … 131 132 CLK_25_PS : OUT std_logic ; 132 133 CLK_50 : OUT std_logic ; 134 FTM_RS485_rx_en : OUT std_logic ; 135 FTM_RS485_tx_d : OUT std_logic ; 136 FTM_RS485_tx_en : OUT std_logic ; 133 137 RSRLOAD : OUT std_logic := '0'; 134 138 SRCLK : OUT std_logic := '0'; … … 149 153 sclk : OUT std_logic ; 150 154 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 155 trigger_veto : OUT std_logic := '1'; 151 156 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 152 157 wiz_cs : OUT std_logic := '1'; … … 191 196 --D_T <= (others => '0'); 192 197 --D_T2 <= ( others => '0' ); 198 D_T2(1) <= '0'; 193 199 -- A0_T(7 downto 0) <= (others => '0'); 194 200 --A1_T(7 downto 0) <= (others => '0'); … … 205 211 A0_T <= led; 206 212 207 -- MAX3485 for FTM trigger ID is switched into receive mode208 RS485_E_RE <= '0';209 RS485_E_DE <= '0';210 -- in receive mode, the DI input of this MAX is in 'don't care' state211 RS485_E_DO <= '0';212 -- the receive pin is fed out as well213 D_T2(1) <= RS485_E_DI;214 215 213 -- additional MAX3485 is switched to shutdown mode 216 214 RS485_C_RE <= '1'; --inverted logic … … 223 221 EE_CS <= '1'; 224 222 225 226 -- ModuleWare code(v1.9) for instance 'I0' of 'gnd'227 TRG_V <= '0';228 223 229 224 -- Instance port mappings. … … 235 230 CLK => X_50M, 236 231 D_T_in => D_T_in, 232 FTM_RS485_rx_d => RS485_E_DI, 237 233 SROUT_in_0 => D0_SROUT, 238 234 SROUT_in_1 => D1_SROUT, … … 250 246 CLK_25_PS => OPEN, 251 247 CLK_50 => CLK_50, 248 FTM_RS485_rx_en => RS485_E_RE, 249 FTM_RS485_tx_d => RS485_E_DO, 250 FTM_RS485_tx_en => RS485_E_DE, 252 251 RSRLOAD => RSRLOAD, 253 252 SRCLK => SRCLK, … … 268 267 sclk => S_CLK, 269 268 sensor_cs => TCS, 269 trigger_veto => TRG_V, 270 270 wiz_addr => W_A, 271 271 wiz_cs => W_CS, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10225 r10462 179 179 180 180 end fad_definitions; 181 182 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10225 r10462 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 08:30:56 04.03.20115 -- at - 17:31:44 26.04.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 20 20 CLK : IN std_logic; 21 21 D_T_in : IN std_logic_vector (1 DOWNTO 0); 22 FTM_RS485_rx_d : IN std_logic; 22 23 SROUT_in_0 : IN std_logic; 23 24 SROUT_in_1 : IN std_logic; … … 35 36 CLK_25_PS : OUT std_logic; 36 37 CLK_50 : OUT std_logic; 38 FTM_RS485_rx_en : OUT std_logic; 39 FTM_RS485_tx_d : OUT std_logic; 40 FTM_RS485_tx_en : OUT std_logic; 37 41 RSRLOAD : OUT std_logic := '0'; 38 42 SRCLK : OUT std_logic := '0'; … … 53 57 sclk : OUT std_logic; 54 58 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 59 trigger_veto : OUT std_logic := '1'; 55 60 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 56 61 wiz_cs : OUT std_logic := '1'; … … 71 76 -- Created: 72 77 -- by - daqct3.UNKNOWN (IHP110) 73 -- at - 08:30:58 04.03.201178 -- at - 17:31:45 26.04.2011 74 79 -- 75 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 87 92 USE IEEE.NUMERIC_STD.all; 88 93 USE IEEE.std_logic_signed.all; 94 USE fact_fad_lib.fad_rs485_constants.all; 89 95 90 96 LIBRARY FACT_FAD_lib; … … 114 120 SIGNAL c_trigger_mult : std_logic_vector(15 DOWNTO 0); 115 121 SIGNAL cont_trigger : std_logic; 116 SIGNAL crc : std_logic_vector(7 DOWNTO 0);117 122 SIGNAL current_dac_array : dac_array_type := ( others => 0); 118 123 SIGNAL dac_setting : dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd … … 161 166 SIGNAL ram_write_ready_ack : std_logic := '0'; 162 167 SIGNAL ready : STD_LOGIC := '0'; 168 SIGNAL rec_timeout_occured : std_logic := '0'; 163 169 SIGNAL reset : std_logic; 164 170 SIGNAL reset_synch_i : std_logic; … … 184 190 SIGNAL trigger_or_s_trigger : std_logic; 185 191 SIGNAL trigger_out : std_logic; 186 SIGNAL trigger_type1 : std_logic_vector(7 DOWNTO 0);187 SIGNAL trigger_type2 : std_logic_vector(7 DOWNTO 0);188 192 SIGNAL wiz_ack : std_logic; 189 193 SIGNAL wiz_busy : std_logic; … … 208 212 209 213 -- Component Declarations 214 COMPONENT FAD_rs485_receiver 215 GENERIC ( 216 -- defined in fad_rs485_definitions.fad_rs485_constants 217 RX_BYTES : integer := RS485_MESSAGE_LEN_BYTES; -- no. of bytes to receive 218 RX_WIDTH : integer := RS485_MESSAGE_LEN_BYTES * 8 -- no. of bits to receive 219 ); 220 PORT ( 221 rec_clk : IN std_logic; 222 rec_start : IN std_logic; 223 rx_d : IN std_logic; 224 rec_dout : OUT std_logic_vector (RX_WIDTH - 1 DOWNTO 0) := (others => '0'); 225 rec_timeout_occured : OUT std_logic := '0'; 226 rec_valid : OUT std_logic := '0'; 227 rx_en : OUT std_logic; 228 tx_d : OUT std_logic; 229 tx_en : OUT std_logic 230 ); 231 END COMPONENT; 210 232 COMPONENT REFCLK_counter 211 233 PORT ( … … 215 237 alarm_refclk_too_low : OUT std_logic := '0'; 216 238 counter_result : OUT std_logic_vector (11 DOWNTO 0) := (others => '0') 217 );218 END COMPONENT;219 COMPONENT RS485_receiver_fake220 PORT (221 crc : IN std_logic_vector (7 DOWNTO 0);222 trigger_no : IN std_logic_vector (31 DOWNTO 0);223 trigger_type1 : IN std_logic_vector (7 DOWNTO 0);224 trigger_type2 : IN std_logic_vector (7 DOWNTO 0);225 rs465_data : OUT std_logic_vector (55 DOWNTO 0);226 rs485_ready : OUT std_logic227 239 ); 228 240 END COMPONENT; … … 303 315 FTM_RS485_ready : IN std_logic ; 304 316 FTM_trigger_info : IN std_logic_vector (55 DOWNTO 0); --7 byte 317 FTM_receiver_status : IN std_logic ; 305 318 -- EVT HEADER - part 3 306 319 fad_event_counter : IN std_logic_vector (31 DOWNTO 0); … … 337 350 drs_read_s_cell_ready : IN std_logic ; 338 351 drs_s_cell_array : IN drs_s_cell_array_type ; 339 drs_readout_started : OUT std_logic := '0' 352 drs_readout_started : OUT std_logic := '0'; 353 trigger_veto : OUT std_logic := '1' 340 354 ); 341 355 END COMPONENT; 342 356 COMPONENT dna_gen 343 357 PORT ( 344 clk : IN STD_LOGIC ;358 clk : IN STD_LOGIC ; 345 359 dna : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) := (others => '0'); 346 360 ready : OUT STD_LOGIC := '0' … … 540 554 -- Optional embedded configurations 541 555 -- pragma synthesis_off 556 FOR ALL : FAD_rs485_receiver USE ENTITY FACT_FAD_lib.FAD_rs485_receiver; 542 557 FOR ALL : REFCLK_counter USE ENTITY FACT_FAD_lib.REFCLK_counter; 543 FOR ALL : RS485_receiver_fake USE ENTITY FACT_FAD_lib.RS485_receiver_fake;544 558 FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer; 545 559 FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps; … … 560 574 561 575 BEGIN 562 -- Architecture concurrent statements563 -- HDL Embedded Text Block 1 eb1564 trigger_type1 <= "00000010";565 trigger_type2 <= "00000000";566 crc <= X"5A";567 568 576 569 577 -- ModuleWare code(v1.9) for instance 'I6' of 'and' … … 633 641 634 642 -- Instance port mappings. 643 U_7 : FAD_rs485_receiver 644 GENERIC MAP ( 645 RX_BYTES => RS485_MESSAGE_LEN_BYTES, -- no. of bytes to receive 646 RX_WIDTH => RS485_MESSAGE_LEN_BYTES * 8 -- no. of bits to receive 647 ) 648 PORT MAP ( 649 rec_clk => CLK_50_internal, 650 rx_d => FTM_RS485_rx_d, 651 rx_en => FTM_RS485_rx_en, 652 tx_d => FTM_RS485_tx_d, 653 tx_en => FTM_RS485_tx_en, 654 rec_start => drs_readout_started, 655 rec_timeout_occured => rec_timeout_occured, 656 rec_dout => rs465_data, 657 rec_valid => FTM_RS485_ready 658 ); 635 659 REFCLK_counter_main : REFCLK_counter 636 660 PORT MAP ( … … 640 664 alarm_refclk_too_high => alarm_refclk_too_high_internal, 641 665 alarm_refclk_too_low => alarm_refclk_too_low_internal 642 );643 RS485_receiver_fake_instance : RS485_receiver_fake644 PORT MAP (645 trigger_no => trigger_id,646 trigger_type1 => trigger_type1,647 trigger_type2 => trigger_type2,648 crc => crc,649 rs465_data => rs465_data,650 rs485_ready => FTM_RS485_ready651 666 ); 652 667 I_main_adc_buffer : adc_buffer … … 718 733 FTM_RS485_ready => FTM_RS485_ready, 719 734 FTM_trigger_info => rs465_data, 735 FTM_receiver_status => rec_timeout_occured, 720 736 fad_event_counter => trigger_id, 721 737 refclk_counter => counter_result_internal, … … 747 763 drs_read_s_cell_ready => drs_read_s_cell_ready, 748 764 drs_s_cell_array => drs_s_cell_array, 749 drs_readout_started => drs_readout_started 765 drs_readout_started => drs_readout_started, 766 trigger_veto => trigger_veto 750 767 ); 751 768 dna_gen_instance : dna_gen -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10225 r10462 939 939 when WR_GET_EVT_ID1 => 940 940 event_number(31 downto 16) <= ram_data; 941 ram_addr <= local_ram_start_addr + 7; -- Address of LOW word of Event ID941 ram_addr <= local_ram_start_addr + 9; -- Address of LOW word of Event ID 942 942 state_write <= WR_GET_EVT_ID_WAIT2; 943 943 when WR_GET_EVT_ID_WAIT2 =>
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