Changeset 10502
- Timestamp:
- 05/02/11 10:11:44 (14 years ago)
- File:
-
- 1 edited
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10500 r10502 78 78 timer_value : in std_logic_vector (31 downto 0); -- time in units of 100us 79 79 80 trigger : in std_logic; 80 hardware_trigger_in : in std_logic; 81 software_trigger_in : in std_logic; 81 82 82 83 adc_data_array : in adc_data_array_type; … … 142 143 signal adc_wait_cnt : integer range 0 to 7 := 0; 143 144 144 signal trigger_sr :std_logic_vector(1 downto 0) := "00"; 145 signal hardware_trigger_sr :std_logic_vector(1 downto 0) := "00"; 146 signal software_trigger_sr :std_logic_vector(1 downto 0) := "00"; 147 145 148 signal ram_write_ea_flag : std_logic := '0'; 146 149 signal new_config_int : std_logic := '0'; … … 168 171 config_done <= '0'; 169 172 end if; 170 trigger_sr <= trigger_sr(0) & trigger; --synching in of asynchrounous trigger signal. 173 hardware_trigger_sr <= hardware_trigger_sr(0) & hardware_trigger_in; --synching in of asynchrounous trigger signal. 174 software_trigger_sr <= software_trigger_sr(0) & software_trigger_in; --synching in of asynchrounous trigger signal. 171 175 addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH); 172 176 … … 223 227 end if; 224 228 225 if (ram_write_ea = '1' and trigger_sr = "01") then229 if (ram_write_ea = '1' and ( hardware_trigger_sr = "01" or software_trigger_sr = "01") ) then 226 230 sig_drs_readout_started <= '1'; -- is set to '0' in next state ... just a pulse. 227 231 runnumber_local_copy <= runnumber;
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