Changeset 10639 for firmware


Ignore:
Timestamp:
May 10, 2011, 8:52:40 AM (9 years ago)
Author:
weitzel
Message:
FTM: keep-alive of Wiznet actiated, clock conditioner interface updated, trigger ID sending updated
Location:
firmware/FTM
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd

    r10260 r10639  
    2020-- modifications:  February 21  2011 by Patrick Vogler
    2121--                 March    23  2011 by Patrick Vogler
     22--                 May      03  2011 by Patrick Vogler and Quirin Weitzel
    2223----------------------------------------------------------------------------------
    2324
     
    3738
    3839
    39 
    4040entity Clock_cond_interface is
    4141  port(
    42 
    4342   
    44 -- Clock
    45 -------------------------------------------------------------------------------
    46    clk   : IN  STD_LOGIC;               -- 50 MHz system clock
    47 
    48    
    49 -- Clock conditioner LMK03000
    50 -------------------------------------------------------------------------------
    51    CLK_Clk_Cond  : out STD_LOGIC;  -- clock conditioner MICROWIRE interface clock
    52    LE_Clk_Cond   : out STD_LOGIC;  -- clock conditioner MICROWIRE interface latch enable   
    53    DATA_Clk_Cond : out STD_LOGIC;  -- clock conditioner MICROWIRE interface data
    54    
    55    SYNC_Clk_Cond : out STD_LOGIC;  -- clock conditioner global clock synchronization
    56    LD_Clk_Cond   : in STD_LOGIC;   -- clock conditioner lock detect                 
    57 
    58    
    59 -- Time Marker
    60 -------------------------------------------------------------------------------
    61    TIM_Sel    : out STD_LOGIC;   -- Time Marker selector
     43    -- Clock
     44    -------------------------------------------------------------------------------
     45    clk   : IN  STD_LOGIC;               -- 50 MHz system clock
     46
     47   
     48    -- Clock conditioner LMK03000
     49    -------------------------------------------------------------------------------
     50    CLK_Clk_Cond  : out STD_LOGIC;  -- clock conditioner MICROWIRE interface clock
     51    LE_Clk_Cond   : out STD_LOGIC;  -- clock conditioner MICROWIRE interface latch enable   
     52    DATA_Clk_Cond : out STD_LOGIC;  -- clock conditioner MICROWIRE interface data
     53   
     54    SYNC_Clk_Cond : out STD_LOGIC;  -- clock conditioner global clock synchronization
     55    LD_Clk_Cond   : in STD_LOGIC;   -- clock conditioner lock detect                 
     56
     57   
     58    -- Time Marker
     59    -------------------------------------------------------------------------------
     60    TIM_Sel    : out STD_LOGIC;  -- Time Marker selector
    6261                                 -- 1 = time marker from Clock conditioner
    6362                                 --     for DRS timing calibration
     
    6766
    6867   
    69    
    70 -- FPGA intern clock conditioner configuration data
    71 -------------------------------------------------------------------------------
    72    cc_R0             : in std_logic_vector (31 downto 0) := (others => '0');
    73    cc_R1             : in std_logic_vector (31 downto 0) := (others => '0');
    74    cc_R8             : in std_logic_vector (31 downto 0) := (others => '0');
    75    cc_R9             : in std_logic_vector (31 downto 0) := (others => '0');
    76    cc_R11            : in std_logic_vector (31 downto 0) := (others => '0');
    77    cc_R13            : in std_logic_vector (31 downto 0) := (others => '0');
    78    cc_R14            : in std_logic_vector (31 downto 0) := (others => '0');
    79    cc_R15            : in std_logic_vector (31 downto 0) := (others => '0');
    80 
    81  
    82  
    83    
    84 -- FPGA intern control signals
    85 -------------------------------------------------------------------------------
    86    start_config : in STD_LOGIC;        -- load new configuration into the clock
     68    -- FPGA intern clock conditioner configuration data
     69    -------------------------------------------------------------------------------
     70    cc_R0             : in std_logic_vector (31 downto 0) := (others => '0');
     71    cc_R1             : in std_logic_vector (31 downto 0) := (others => '0');
     72    cc_R8             : in std_logic_vector (31 downto 0) := (others => '0');
     73    cc_R9             : in std_logic_vector (31 downto 0) := (others => '0');
     74    cc_R11            : in std_logic_vector (31 downto 0) := (others => '0');
     75    cc_R13            : in std_logic_vector (31 downto 0) := (others => '0');
     76    cc_R14            : in std_logic_vector (31 downto 0) := (others => '0');
     77    cc_R15            : in std_logic_vector (31 downto 0) := (others => '0');
     78
     79   
     80    -- FPGA intern control signals
     81    -------------------------------------------------------------------------------
     82    start_config : in STD_LOGIC;       -- load new configuration into the clock
    8783                                       -- conditioner
    8884   
    89    config_started : out STD_LOGIC;     -- indicates that the new configuration
     85    config_started : out STD_LOGIC;    -- indicates that the new configuration
    9086                                       -- is currently loaded into the clock conditioner
    9187
    92    config_done : out STD_LOGIC;        -- indicates that the configuration has
     88    config_done : out STD_LOGIC;       -- indicates that the configuration has
    9389                                       -- been loaded and the clock conditioners
    9490                                       -- PLL is locked
    9591
    96    timemarker_select: in STD_LOGIC     -- selects time marker source
     92    timemarker_select: in STD_LOGIC    -- selects time marker source
    9793                                       --
    9894                                       -- 1 = time marker from Clock conditioner
     
    106102
    107103
    108 
    109 
    110104architecture Behavioral of Clock_cond_interface is
    111105 
    112106 
    113 component microwire_interface IS
    114    PORT(
     107  component microwire_interface IS
     108    PORT(
    115109      clk               : IN     std_logic;
    116110      clk_uwire         : OUT    std_logic;  --- IN or OUT ?         
     
    121115      config_ready      : OUT    std_logic;
    122116      config_started    : OUT    std_logic     
    123    );
    124 end component;
    125 
    126 
     117    );
     118  end component;
    127119
    128120 
    129121  signal clk_50M_sig : STD_LOGIC;       -- system clock
    130 --  signal start_config_sig : STD_LOGIC; 
     122  --signal start_config_sig : STD_LOGIC; 
    131123
    132124  signal config_ready_sig : STD_LOGIC;
     
    154146  signal cc_R15_sig            : std_logic_vector (31 downto 0);
    155147
    156 
     148  signal timemarker_select_sig : std_logic := '0';
     149
     150  type TIM_SEL_STATE_TYPE is (IDLE, CONFIG);
     151  signal tim_sel_state : TIM_SEL_STATE_TYPE := IDLE;
    157152
    158153
     
    173168        config_ready        => config_ready_sig,
    174169        config_started      => config_started_sig
    175        );
     170    );
    176171
    177172 
    178173       
    179   config_done <= config_ready_sig;  -- indicates that the configuration
     174  --config_done <= config_ready_sig;  -- indicates that the configuration
    180175                                    -- has been loaded
    181176
    182177
    183178 
    184  -- config_done <= (config_ready_sig AND LD_Clk_Cond);  -- indicates that the configuration
     179  config_done <= (config_ready_sig AND LD_Clk_Cond);  -- indicates that the configuration
    185180                                                      -- has been loaded and
    186181                                                      -- the PLL is locked again
     
    188183
    189184 
    190   TIM_Sel <= timemarker_select;                                   
     185  --TIM_Sel <= timemarker_select;                                   
     186
     187  TIM_Sel <= timemarker_select_sig;
     188
     189  tim_sel_proc : process (clk_uwire_sig)
     190  begin
     191    if rising_edge(clk_uwire_sig) then
     192      case tim_sel_state is
     193        when IDLE =>
     194          if start_config = '1' then
     195            timemarker_select_sig <= '0';
     196            tim_sel_state <= CONFIG;
     197          end if;
     198        when CONFIG =>
     199          if config_ready_sig = '1' then
     200            timemarker_select_sig <= timemarker_select;
     201            tim_sel_state <= IDLE;
     202          end if;
     203       end case;
     204     end if;
     205  end process tim_sel_proc;
     206     
     207           
    191208  CLK_Clk_Cond <= clk_uwire_sig;
    192209
    193210  clk_50M_sig <= clk;
    194  -- start_config_sig <= start_config;
    195 
    196  --  start_config <= start_config_sig;     
    197 
    198 
     211 
     212  -- start_config_sig <= start_config;
     213  --  start_config <= start_config_sig;     
    199214  config_started <= config_started_sig;
    200215
     
    233248  clk_cond_array_sig(14) <= cc_R15_sig;
    234249
    235 
    236250end Behavioral;
    237 
    238 
  • firmware/FTM/FTM_central_control.vhd

    r10441 r10639  
    8080    start_run_num_events : IN  std_logic_vector (31 DOWNTO 0);
    8181    trigger_start : out std_logic := '0';
    82     trigger_stop : out std_logic := '1'
     82    trigger_stop : out std_logic := '1';
     83    enable_ID_sending : out std_logic := '0'
    8384  );
    8485end FTM_central_control;
     
    248249          trigger_start <= '1';
    249250          trigger_stop <= '0';
     251          enable_Id_sending <= '1';
    250252          if (new_config = '1') then
    251253            config_started <= '1';
     
    270272            trigger_start <= '0';
    271273            trigger_stop <= '1';
     274            enable_Id_sending <= '0';
    272275            state_central_proc <= CP_RUNNING_02;
    273276          end if;
  • firmware/FTM/FTM_top.vhd

    r10441 r10639  
    122122   
    123123    SYNC_Clk_Cond : out STD_LOGIC;  -- global clock synchronization
    124     LD_Clk_Cond   : in STD_LOGIC;   -- lock detect, should be checked for                 
     124    LD_Clk_Cond   : in STD_LOGIC;   -- lock detect                 
    125125
    126126   
     
    400400  signal trigger_start_sig : std_logic;
    401401  signal trigger_stop_sig : std_logic;
     402
     403  signal enable_ID_sending_sig : std_logic;
    402404 
    403405--  component FTM_clk_gen
     
    561563      start_run_num_events   : IN  std_logic_vector (31 DOWNTO 0);
    562564      trigger_start : out std_logic;
    563       trigger_stop : out std_logic
     565      trigger_stop : out std_logic;
     566      enable_ID_sending : out std_logic
    564567    );
    565568  end component;
     
    942945      start_run_num_events   => start_run_num_events_sig,
    943946      trigger_start => trigger_start_sig,
    944       trigger_stop  => trigger_stop_sig
     947      trigger_stop  => trigger_stop_sig,
     948      enable_ID_sending => enable_ID_sending_sig
    945949    );
    946950 
     
    10091013      rx_d_3            => Bus2_RxD_3,
    10101014      tx_d_3            => Bus2_TxD_3,
    1011       enable_ID_sending => '1',
     1015      --enable_ID_sending => trigger_start_sig,
     1016      enable_ID_sending => enable_ID_sending_sig,
     1017      --enable_ID_sending => '1',
    10121018      TIM_source        => general_settings_sig(0),
    10131019      LP_settings       => "0000",
  • firmware/FTM/ethernet/w5300_modul.vhd

    r10441 r10639  
    1818--
    1919----------------------------------------------------------------------------------
    20 -- hds interface_start
     20
    2121LIBRARY IEEE;
    2222USE IEEE.STD_LOGIC_1164.all;
     
    117117  type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
    118118                           INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
    119                            SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR,
     119                           SI, SI0, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR,
    120120                           READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL);
    121121  type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08,
    122                             WR_WRITE_START_DEL, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01, WR_WRITE_END_DEL);
     122                            WR_WRITE_START_DEL, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_SD_ADDR, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01, WR_WRITE_END_DEL);
    123123  type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
    124124  type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
     
    179179  signal cmd_array : cmd_array_type;
    180180  signal internal_cmd : std_logic := '0';
     181  signal wait_for_data_flag : std_logic := '0';
    181182
    182183  signal autosend_flag : std_logic := '1';
     
    461462            par_data   <= X"0101";                    -- ALIGN, TCP
    462463            state_init <= WRITE_REG;
     464            next_state <= SI0;
     465          -- keep alive
     466          when SI0 =>
     467            par_addr   <= W5300_S0_KPALVTR + socket_cnt * W5300_S_INC;
     468            par_data   <= X"0C00";                    -- 12 * 5s = 60s
     469            state_init <= WRITE_REG;
    463470            next_state <= SI1;
    464471          -- Sx Interrupt Mask
     
    520527                  ftu_error_send_ready <= '0';
    521528                  led_int <= X"00";
     529                  wait_for_data_flag <= '0';
    522530                  -- -- --
    523531                else
     
    560568              state_init      <= READ_DATA;
    561569              busy            <= '1';
    562             elsif (dd_send = '1') then
     570            elsif ((dd_send = '1') and (wait_for_data_flag = '0')) then
    563571              internal_cmd <= '1';
    564572              dd_send_ack <= '1';
     
    569577              state_read_data <= RD_READ_DD_BLOCK;
    570578              state_init <= READ_DATA;
    571             elsif (ftu_error_send = '1') then
     579            elsif ((ftu_error_send = '1') and (wait_for_data_flag = '0')) then
    572580              ftu_error_send_ack <= '1';
    573581              ftu_error_send_ready <= '0';
     
    697705                      when PAR_START_X_EVNTS =>
    698706                        next_state_read_data <= RD_X_EVNTS;
     707                        wait_for_data_flag <= '1';
    699708                        state_read_data <= RD_5;
    700709                      when others =>
     
    721730                      -- write to address in static data block
    722731                      when PAR_WRITE_SD_ADDR =>
    723                         new_config_flag <= '1';
     732                        wait_for_data_flag <= '1';
    724733                        next_state_read_data <= RD_WRITE_SD_ADDR;
    725734                        state_read_data <= RD_5;
    726735                      -- write static data block
    727736                      when PAR_WRITE_SD =>
    728                         new_config_flag <= '1';
     737                        wait_for_data_flag <= '1';
    729738                        next_state_read_data <= RD_WRITE_SD_BLOCK;
    730739                        state_read_data <= RD_5;
     
    737746                      -- read from address in static data block
    738747                      when PAR_READ_SD_ADDR =>
     748                        wait_for_data_flag <= '1';
    739749                        next_state_read_data <= RD_READ_SD_ADDR;
    740750                        state_read_data <= RD_5;
     
    865875                local_write_length <= '0' & X"0001"; -- one word will be written to ethernet
    866876                next_state_read_data <= RD_CMD;
     877                wait_for_data_flag <= '0';
    867878                next_state <= READ_DATA;
    868879                state_init <= WRITE_DATA;
     
    879890                if (next_packet_data_cnt = (SD_BLOCK_SIZE - 1)) then
    880891                  next_packet_data_cnt <= 0;
     892                  wait_for_data_flag <= '0';
     893                  new_config_flag <= '1';
    881894                  next_state_read_data <= RD_CMD;
    882895                end if;
     
    891904                  local_sd_data <= data_read;
    892905                  next_packet_data_cnt <= 0;
     906                  wait_for_data_flag <= '0';
     907                  new_config_flag <= '1';
    893908                  next_state_read_data <= RD_CMD;
    894909                  next_state <= READ_DATA;
     
    907922                    start_run <= '0';
    908923                    next_packet_data_cnt <= 0;
     924                    wait_for_data_flag <= '0';
    909925                    next_state_read_data <= RD_CMD;
    910926                    state_read_data <= RD_5;
     
    11061122               
    11071123              -- Fill FIFO
     1124              -- write header
    11081125              when WR_FIFO_HEADER =>
    11091126                state_init <= READ_FROM_HEADER_MODUL;
     
    11201137                  state_write    <= WR_FIFO_HEADER;
    11211138                else
    1122                   state_write <= WR_FIFO_DATA;
    1123                 end if;
    1124                
     1139                  if (data_package_type = FTM_PACKAGE_TYPE_SD_WORD) then
     1140                    state_write <= WR_SD_ADDR;
     1141                  else
     1142                    state_write <= WR_FIFO_DATA;
     1143                  end if;
     1144                end if;
     1145             
     1146              -- write static data ram address (only for single address request)
     1147              when WR_SD_ADDR =>
     1148                write_length_bytes <= write_length_bytes + 2; -- one extra word to write
     1149                par_addr       <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
     1150                par_data       <= "0000" & local_sd_addr;
     1151                state_init     <= WRITE_REG;
     1152                next_state     <= WRITE_DATA;
     1153                state_write    <= WR_FIFO_DATA;
     1154             
     1155              -- write data
    11251156              when WR_FIFO_DATA =>
    11261157                state_init <= read_addr_state;
  • firmware/FTM/ftm_definitions.vhd

    r10441 r10639  
    4646--            changed FTM_HEADER_LENGTH to 0x0E
    4747-- kw 20.04.: added "package types", SD_SINGLE_WORD_SIZE
     48--
     49-- kw 28.04.: changed SD_SINGLE_WORD_SIZE to X"002", added W5300_S0_KPALVTR (keep alive)
    4850--
    4951----------------------------------------------------------------------------------
     
    189191  constant W5300_S0_DPORTR   : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12";
    190192  constant W5300_S0_DIPR     : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14";
     193  constant W5300_S0_KPALVTR  : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"1A";
    191194  constant W5300_S0_TX_WRSR  : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20";
    192195  constant W5300_S0_TX_FSR   : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24";
     
    270273  constant SD_FTU_ACTIVE_NUM         : integer := 4;                -- number of active FTU lists (cr0 to cr3)
    271274  constant SD_BLOCK_SIZE             : std_logic_vector (11 downto 0) := X"1B4";  -- total size of static data block
    272   constant SD_SINGLE_WORD_SIZE       : std_logic_vector := X"001";
     275  constant SD_SINGLE_WORD_SIZE       : std_logic_vector := X"002";
    273276 
    274277  -- dynamic data block
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