Changeset 10667 for firmware


Ignore:
Timestamp:
May 11, 2011, 6:33:23 PM (8 years ago)
Author:
neise
Message:
 
Location:
firmware/FSC/src
Files:
6 added
11 edited

Legend:

Unmodified
Added
Removed
  • firmware/FSC/src/application.c

    r10236 r10667  
    22
    33#include "application.h"
     4#include "usart.h"
    45#include <avr/wdt.h>
    56
     
    1011//-----------------------------------------------------------------------------
    1112
    12 void app_init(void)
    13 {
     13void app_init(void) {
    1414  app_reset_source = MCUSR; // Save last reset source
    1515  MCUSR = 0x00; // Clear reset source for next reset cycle
     
    3434        DDRA &= ~(1<<PA7);                              // set In1_spare as input
    3535        DDRC &= ~(1<<PC7);                              // set In2_spare as input
    36         PORTA |= (1<<PA7);                              // swtich on pullup on In1_spare
    37         PORTC |= (1<<PC7);                              // swtich on pullup on In2_spare
     36        //PORTA |= (1<<PA7);                            // swtich on pullup on In1_spare
     37        //PORTC |= (1<<PC7);                            // swtich on pullup on In2_spare
    3838
    3939        // ATmega internal ADC input
     
    9191  SREG = sreg_backup; // Restore status register
    9292}
     93
     94void set_ad7719_enable_register() {
     95
     96        usart_write_str((pU08)"\n set enable bits of AD7719 Port ");
     97        if ((usart_received_chars>=5) &&
     98        (usart_rx_buffer[2] >= 'A' && usart_rx_buffer[2] <= 'H'))
     99        {
     100        usart_write_char(usart_rx_buffer[2]);
     101        usart_write_str((pU08)" to ");
     102        usart_write_U08_hex(usart_rx_buffer[4]);
     103        usart_write_char('\n');
     104                ad7719_enables[usart_rx_buffer[2]-'A']=usart_rx_buffer[4];
     105                ad7719_channels_ready[usart_rx_buffer[2]-'A']=0x00;
     106        }
     107        else if  ((usart_received_chars=3) &&
     108        (usart_rx_buffer[1] >= 'A' && usart_rx_buffer[1] <= 'H'))
     109        {
     110                usart_write_char(usart_rx_buffer[1]);
     111                if (usart_rx_buffer[2]!='0') {
     112                        usart_write_str((pU08)" to 0xFF\n");
     113                        ad7719_enables[usart_rx_buffer[1]-'A']=0xFF;
     114                } else
     115                {
     116                        usart_write_str((pU08)" to 0x00\n");
     117                        ad7719_enables[usart_rx_buffer[1]-'A']=0x00;
     118                }
     119                ad7719_channels_ready[usart_rx_buffer[1]-'A']=0x00;     
     120        }
     121        else
     122        {
     123                usart_write_str((pU08)"\n something wrong\n");
     124                usart_write_str((pU08)"usart_rx_buffer_index: ");
     125                usart_write_U08(usart_received_chars, 3);
     126                usart_write_str((pU08)"\n usart_rx_buffer[2]: ");
     127                usart_write_char(usart_rx_buffer[2]);
     128                usart_write_str((pU08)"\n usart_rx_buffer[4]: ");
     129                usart_write_U08_hex(usart_rx_buffer[4]);
     130                usart_write_char('\n');
     131        }
     132}
     133
     134void set_adc_enable_register() {
     135        // TODO
     136        usart_write_str((pU08)"setting of ATmega internal ADC enable registers is not supported. yet.\n");
     137}
     138
     139U08     increase_adc (U08 channel){
     140U08 effective_channel;
     141        for ( U08 increase = 1 ; increase <= V_CHANNELS + I_CHANNELS + H_CHANNELS; increase++)
     142        {
     143                effective_channel = (channel + increase) % (V_CHANNELS + I_CHANNELS + H_CHANNELS);
     144                if (adc_enables[effective_channel/8] & (1<<effective_channel%8))
     145                        return effective_channel;
     146        }
     147        return channel;
     148} // end if increase_adc;
     149
     150U08     increase_ad7719 (U08 channel){
     151U08 effective_channel;
     152        for ( U08 increase = 1 ; increase <= TEMP_CHANNELS; increase++)
     153        {
     154                effective_channel = (channel + increase) % (TEMP_CHANNELS);
     155                if (ad7719_enables[effective_channel/8] & (1<<effective_channel%8))
     156                        return effective_channel;
     157        }
     158        return channel;
     159} // end if increase_adc;
     160
     161void check_if_measured_all() {
     162        adc_measured_all = true;
     163        for ( U08 i=0; i<V_BITMAP + I_BITMAP + H_BITMAP; ++i ) {
     164                if ((adc_enables[i] ^ adc_channels_ready[i]) != 0x00) {
     165                        adc_measured_all = false;
     166                        break;
     167                }
     168        }
     169        ad7719_measured_all = true;
     170        for ( U08 i=0; i<CHANNEL_BITMAP; ++i ) {
     171                if ((ad7719_enables[i] ^ ad7719_channels_ready[i]) != 0x00) {
     172                        ad7719_measured_all = false;
     173                        break;
     174                }
     175        }
     176
     177
     178}
  • firmware/FSC/src/application.h

    r10237 r10667  
    66//-----------------------------------------------------------------------------
    77
    8 #define USART_RX_BUFFER_SIZE 32 // Receive buffer size
    9 #define USART_TX_BUFFER_SIZE 5 // Receive buffer size. MUST not be larger 255
    108
    11 #define USART_BAUDRATE 9600 // USART baudrate original
    12 #define USART_USE_TX // Transmitter used?
    13 #define USART_USE_RX // Receiver used?
    14 //#define USART_USE_RX_IRQ // RX interrupt used?
    15 #define USART_USE_UPPERCASE // Convert received chars to uppercase?
    169//-----------------------------------------------------------------------------
    1710
     
    3124#define SPI_A_CS PD5           
    3225
     26//#ifdef ____WENNICHSWIRKLICHWILL
     27#ifndef ___MAIN_WORKFLOW_GLOBAL_VARS
     28#define ___MAIN_WORKFLOW_GLOBAL_VARS
     29        #define TEMP_CHANNELS 64
     30        #define CHANNEL_BITMAP 8
     31        #define AD7719_READINGS_UNTIL_SETTLED 3 // bei3:480ms
     32       
     33        #define V_CHANNELS 40
     34        #define I_CHANNELS 40
     35        #define H_CHANNELS 4
     36        #define V_BITMAP 5
     37        #define I_BITMAP 5
     38        #define H_BITMAP 1
     39        #define ADC_READINGS_UNTIL_SETTLED 1
     40#endif
     41
     42// MAIN WORKFLOW GLOBAL VARIABLES
     43
     44        extern bool heartbeat_enable;
     45
     46
     47       
     48// TIMER global variable
     49        extern volatile U32 local_ms;
     50
     51// AD7719 global variables
     52        extern U32 ad7719_values[TEMP_CHANNELS];
     53        extern U08 ad7719_enables[CHANNEL_BITMAP];
     54        extern U08 ad7719_channels_ready[CHANNEL_BITMAP];
     55        extern U08 ad7719_readings_since_last_muxing;
     56        extern U08 ad7719_current_channel;
     57        extern U32 ad7719_current_reading;
     58        extern bool ad7719_measured_all;
     59// ATMEGA ADC global variables
     60        extern U08 adc_values[V_CHANNELS + I_CHANNELS + H_CHANNELS]; // stores measured voltage in steps of 16mV
     61        extern U08 adc_enables[V_BITMAP + I_BITMAP + H_BITMAP];
     62        extern U08 adc_channels_ready[V_BITMAP + I_BITMAP + H_BITMAP];
     63        extern U08 adc_readings_since_last_muxing;
     64        extern U08 adc_current_channel;
     65        extern U08 adc_current_reading;
     66        extern bool adc_measured_all;
     67
     68        extern bool once_told_you;
     69        extern bool debug_mode;
    3370
    3471
     
    4077void app_init(void); // Initialize application
    4178void app_set_watchdog_prescaler(tWDT_PRESCALE wdt_prescale); // Set watchdog prescale
     79
     80//methods in main ... declared here ... don't ask why ...
     81// definition of some functions:
     82// these function are implemented in this file, this is not doog coding style.
     83// sooner or later, they will be moved into more apropriate files.
     84void set_adc_enable_register();
     85void set_ad7719_enable_register();
     86U08     increase_adc (U08 channel);
     87U08     increase_ad7719 (U08 channel);
     88void check_what_measurement_was_finished() ;
     89void check_if_measured_all() ;
     90// end of function definition:
     91//-----------------------------------------------------------------------------
     92
     93
     94
    4295//-----------------------------------------------------------------------------
    4396
  • firmware/FSC/src/output.c

    r10244 r10667  
    11#include "output.h"
    22#include "usart.h"
     3#include "application.h"
    34
    45void print_status() {
  • firmware/FSC/src/output.h

    r10244 r10667  
    99void print_ad7719_nicely();
    1010void print_adc_nicely();
    11 
     11void print_status() ;
    1212
    1313#endif
  • firmware/FSC/src/parser.c

    r10244 r10667  
    11#include "parser.h"
    22#include "output.h"
     3#include "application.h"
     4#include "usart.h"
    35// this method parses the data,
    46// which came in via USART
     
    7274                usart_rx_buffer[i] = 0;
    7375}
     76
     77void parse_non_human_readable_input() {
     78
     79
     80}
     81
     82// this guy checks, if an incoming byte is:
     83// to be stored, because it belongs to a command
     84// to be discarded, because something went wrong, and the bytemade no sense...
     85// the end of a commmand, and so the 'real parser' may do his work.
     86
     87void incoming_byte_parser() {
     88        static bool receiving_command = false;
     89        U08 current_byte = UDR;
     90       
     91        if (!receiving_command) {
     92                switch (current_byte) {
     93                        case 0x01:
     94                                receiving_command = true;
     95                                break;
     96                }
     97        }
     98       
     99        if (receiving_command)
     100        {
     101                usart_rx_buffer[usart_received_chars] = usart_last_char;
     102                usart_received_chars++;
     103        }
     104       
     105       
     106}
  • firmware/FSC/src/parser.h

    r10244 r10667  
    44void parse_ascii();
    55
     6
     7// all allowed non readable commands are listed here
     8#define SET_ENABLES 0x01 // sets all enables -- needs 8 + 11 bytes of data
     9#define SW_TO_HUMAN 0xFF // SWITCH_TO_HUMAN_READABLE_INTERFACE
     10
    611#endif
  • firmware/FSC/src/spi_master.c

    r10236 r10667  
    5656
    5757  spi_dord = 0;                                 // Data Order MSB first dord = 0  --> good for all devices
    58   spi_cpol = 1; spi_cpha = 1;                                   // SPI mode=3                   --> good for all devices
     58  spi_cpol = 0; spi_cpha = 0;                                   // SPI mode=0 good for ethernet.
    5959  spi_setup();                                  // Setup SPI bits and clock speed
    6060
  • firmware/FSC/src/usart.c

    r10236 r10667  
    22
    33#include "usart.h"
     4#include "num_conversion.h"
    45#include <avr/interrupt.h>
    56//-----------------------------------------------------------------------------
     7#ifdef USART_USE_TX_IRQ
     8
     9#endif
    610
    711#ifdef USART_USE_RX_IRQ
     
    1317  static U08 usart_receive_char;
    1418  static BOOL usart_receive_suspended = false;
    15   volatile BOOL ISR_toggle_out = false;
    1619#endif
    1720//-----------------------------------------------------------------------------
     
    172175ISR(SIG_USART_RECV)
    173176{
    174   if (ISR_toggle_out) PORTB ^= (1<<PB3); // toggle Out2_spare when starting ISR
    175 
    176   usart_receive_char = UDR;
     177        usart_receive_char = UDR;
    177178
    178179  if (usart_rx_ready) // Exit if ready flag is still set
     
    230231  {
    231232    usart_rx_buffer[usart_rx_buffer_index++] = usart_receive_char;
    232     usart_writeln_str(usart_rx_buffer);
     233    //usart_writeln_str(usart_rx_buffer);
    233234  }
    234235
     
    241242
    242243#endif
    243 /*
    244 #define uart_maxstrlen 64
    245  
    246 volatile U8 uart_str_complete=0;
    247 volatile U8 uart_str_count=0;
    248 volatile U8 uart_string[uart_maxstrlen+1]="";
    249 
    250 ISR(USART_RXC_vect)
    251 {
    252     unsigned char buffer = 64;
    253     // Daten aus dem Puffer lesen
    254     buffer = UDR;
    255         UDR = buffer;
    256         if ( uart_str_complete==0 ){    // wenn uart_string gerade in Verwendung, neues Zeichen verwerfen
    257                 // Daten werden erst in string geschrieben, wenn nicht String-Ende/max Zeichenlänge erreicht ist/string gerade verarbeitet wird
    258                 if (buffer!='\n' && buffer!='\r' && uart_str_count<uart_maxstrlen-1){
    259                         uart_string[uart_str_count]=buffer;
    260                         uart_str_count++;
    261                 } else {
    262                         uart_string[uart_str_count]='\0';
    263                         uart_str_count=0;
    264                         uart_str_complete=1;
    265                 }
     244
     245
     246#ifdef USART_USE_TX_IRQ
     247
     248ISR(TRALA_vect)
     249{
     250
     251        // if it is necessary to write something via USART ... then send
     252        // if not ... disable this interrupt.
     253        if (usart_write_start_index < usart_write_stop_index) // some bytes in the usart_tx_buffer should be send away.
     254        {
     255                UDR = usart_tx_buffer[usart_write_start_index%USART_TX_BUFFER_SIZE];
    266256        }
    267 }
    268 
    269 */
     257        else
     258        {
     259                // disable this interrupt source
     260                UCSRB &= ~(1<<UDRIE);
     261        }
     262
     263#endif
  • firmware/FSC/src/usart.h

    r10236 r10667  
    66#include "application.h"
    77#include "num_conversion.h"
     8
     9//-----------------------------------------------------------------------------
     10#define USART_RX_BUFFER_SIZE 32 // Receive buffer size
     11#define USART_TX_BUFFER_SIZE 5 // Receive buffer size. MUST not be larger 255
     12
     13#define USART_BAUDRATE 9600 // USART baudrate original
     14#define USART_USE_TX // Transmitter used?
     15#define USART_USE_RX // Receiver used?
     16#define USART_USE_RX_IRQ // RX interrupt used?
     17//#define USART_USE_UPPERCASE // Convert received chars to uppercase?
    818//-----------------------------------------------------------------------------
    919
     
    2030                                ((U32)br * 16) - 1))
    2131//-----------------------------------------------------------------------------
    22 /*
    23 extern U08 usart_rx_buffer[];
    24 extern volatile BOOL usart_rx_ready;
    25 extern volatile BOOL ISR_toggle_out;
    26 extern U08 usart_received_chars;
    27 */
     32
     33// USART global variables
     34        extern U08 usart_rx_buffer[USART_RX_BUFFER_SIZE];
     35        extern U08 usart_tx_buffer[USART_TX_BUFFER_SIZE];
     36        extern U08 usart_received_chars;
     37
     38        extern U08 usart_tx_buffer_index;
     39        extern U08 usart_last_char;                                     // last received char
     40
     41// USART FLAGS
     42        extern bool usart_tx_buffer_overflow;   // true if usart_tx_buffer was full.
     43
     44
     45
    2846extern bool usart_tx_buffer_overflow;
    2947extern U08 usart_tx_buffer_index;
    3048extern U08 usart_tx_buffer[USART_TX_BUFFER_SIZE];
    31 extern U08 usart_received_chars;
     49
     50#ifdef USART_USE_RX_IRQ
     51  extern U08 usart_rx_buffer[];
     52  //U08 *usart_rx_buffer_ptr = &usart_rx_buffer[0];
     53  extern U08 usart_received_chars;
     54  extern volatile BOOL usart_rx_ready;
     55#endif
     56
    3257//-----------------------------------------------------------------------------
    3358
  • firmware/FSC/src/w5100_spi_interface.c

    r10236 r10667  
    33#include "w5100_spi_interface.h"       
    44#include "spi_master.h"   
     5#include "usart.h"
    56volatile BOOL sock0_connection_established = false;
    67volatile U08 eth_read_buffer[ETH_READ_BUFFER_SIZE];
     
    3435U08 w5100_init (void)
    3536{
    36 U08 sock0_status;
     37U08 sock0_status = 0x00;
    3738
    3839        // set FSCs MAC Address to value defined in w5100_spi_interface.h
     
    7071        w5100_write ( S0_PORT0, 0x13 );         // Port 5000 -> 0x1388
    7172        w5100_write ( S0_PORT1, 0x88 );
     73        usart_write_str((pU08)"Issuing Socket open command. NOW\n");
    7274        w5100_write ( S0_CR, CR_OPEN );         // issue Socket open command
    73         sock0_status = w5100_read(S0_SR); // request socket 0 status
    74         if ( sock0_status != SR_SOCK_INIT)
    75         {
    76                 return sock0_status;
    77         }
    78 
     75        while (sock0_status != SR_SOCK_INIT) {
     76                sock0_status = w5100_read(S0_SR); // request socket 0 status
     77                usart_write_str((pU08)"Socket 0 status is:");
     78                usart_write_U08_hex(sock0_status);
     79                usart_write_char('\n');
     80        }
     81
     82        usart_write_str((pU08)"Issuing Socket LISTEN command. NOW\n");
    7983        w5100_write ( S0_CR, CR_LISTEN );               // issue Socket listen command
    80         sock0_status = w5100_read(S0_SR); // request socket 0 status
    81         if ( sock0_status != SR_SOCK_LISTEN)
    82         {
    83                 return sock0_status;
    84         }
    85 
     84       
     85        while (sock0_status != SR_SOCK_LISTEN) {
     86                sock0_status = w5100_read(S0_SR); // request socket 0 status
     87                usart_write_str((pU08)"Socket 0 status is:");
     88                usart_write_U08_hex(sock0_status);
     89                usart_write_char('\n');
     90        }
    8691        return sock0_status;
    8792}
     
    113118{
    114119U16 freesize;
    115 freesize=w5100_read(S0_TX_FSR1);
     120freesize=w5100_read(S0_TX_FSR0);
    116121freesize = freesize << 8;
    117 freesize += w5100_read(S0_TX_FSR0);
     122freesize += w5100_read(S0_TX_FSR1);
    118123return freesize;
    119124}
     
    123128{
    124129U16 readpointer;
    125 readpointer=w5100_read(S0_TX_RD1);
     130readpointer=w5100_read(S0_TX_RD0);
    126131readpointer = readpointer << 8;
    127 readpointer += w5100_read(S0_TX_RD0);
     132readpointer += w5100_read(S0_TX_RD1);
    128133return readpointer;
    129134}
     
    133138{
    134139U16 writepointer;
    135 writepointer=w5100_read(S0_TX_WR1);
     140writepointer=w5100_read(S0_TX_WR0);
    136141writepointer = writepointer << 8;
    137 writepointer += w5100_read(S0_TX_WR0);
     142writepointer += w5100_read(S0_TX_WR1);
    138143return writepointer;
    139144}
     
    143148{
    144149U16 received_size;
    145 received_size=w5100_read(S0_RX_RSR1);
     150received_size=w5100_read(S0_RX_RSR0);
    146151received_size = received_size << 8;
    147 received_size += w5100_read(S0_RX_RSR0);
     152received_size += w5100_read(S0_RX_RSR1);   // S0_RX_RSR1 is the least significant byte ...
    148153return received_size;
    149154}
     
    153158{
    154159U16 readpointer;
    155 readpointer=w5100_read(S0_RX_RD1);
     160readpointer=w5100_read(S0_RX_RD0);
    156161readpointer = readpointer << 8;
    157 readpointer += w5100_read(S0_RX_RD0);
     162readpointer += w5100_read(S0_RX_RD1);
    158163return readpointer;
    159164}
     
    164169{
    165170U08 high_byte = (value>>8);
    166 U08 low_byte = (value<<8)>>8;
    167 w5100_write(S0_TX_WR1, high_byte);
    168 w5100_write(S0_TX_WR0, low_byte);
     171U08 low_byte = value&0x00FF;
     172w5100_write(S0_TX_WR0, high_byte);
     173w5100_write(S0_TX_WR1, low_byte);
    169174}
    170175
     
    173178{
    174179U08 high_byte = (value>>8);
    175 U08 low_byte = (value<<8)>>8;
    176 w5100_write(S0_TX_RD1, high_byte);
    177 w5100_write(S0_TX_RD0, low_byte);
     180U08 low_byte = value&0x00FF;
     181
     182w5100_write(S0_RX_RD0, high_byte);
     183w5100_write(S0_RX_RD1, low_byte);
    178184}
    179185
     
    200206        U16 offset = last_RX_read_pointer & S0_RX_MASK;
    201207        U16 start_address =  S0_RX_BASE + offset;
     208       
     209        usart_write_str("last_read_pointer:");
     210        usart_write_U16_hex(last_RX_read_pointer);
     211        usart_write_str("\noffset:");
     212        usart_write_U16_hex(offset);
     213        usart_write_str("\nstart_address:");
     214        usart_write_U16_hex(start_address);
     215        usart_write_char('\n');
    202216
    203217        if ((offset + NumBytes) > (S0_RX_MASK + 1) )  // if data is turned over in RX-mem
     
    224238        // inform W5100 about how much data was read out.
    225239        set_S0_RX_RD(last_RX_read_pointer + NumBytes);
     240        w5100_write ( S0_CR, CR_RECV );
     241       
     242        usart_write_U16_hex(get_S0_TX_FSR()); usart_write_char('\t'); usart_write_char('|');
     243        usart_write_U16_hex(get_S0_TX_RD()); usart_write_char('\t'); usart_write_char('|');
     244        usart_write_U16_hex(get_S0_TX_WR()); usart_write_char('\t'); usart_write_char('|');
     245        usart_write_U16_hex(get_S0_RX_RSR()); usart_write_char('\t'); usart_write_char('|');
     246        usart_write_U16_hex(get_S0_RX_RD()); usart_write_char('\t'); usart_write_char('|');
    226247
    227248        // if user wishes, W5100 may inform peer about receiption.
     
    233254        if (send_ACK)
    234255        {
    235                 w5100_write ( S0_CR, CR_RECV );
     256                //w5100_write ( S0_CR, CR_RECV );
    236257        }
    237258
     
    240261
    241262// returns number of words, transmitted into TX - buffer.
    242 U08 w5100_set_TX(U08 NumBytes)
    243 {
     263U08 w5100_set_TX(U08 NumBytes) {
    244264        U16 freesize = get_S0_TX_FSR();
    245265        if (freesize == 0)
    246266        {
    247267                return 0;
    248         }
    249         if (freesize < NumBytes)
    250         {
    251                 NumBytes = freesize;
    252268        }
    253269       
     
    258274
    259275        U16 upper_size, lower_size;
    260         if (NumBytes > ETH_READ_BUFFER_SIZE)
    261         {
    262                 NumBytes = ETH_READ_BUFFER_SIZE;
     276        if (NumBytes > ETH_WRITE_BUFFER_SIZE)
     277        {
     278                NumBytes = ETH_WRITE_BUFFER_SIZE;
    263279        }
    264280        if (freesize == 0)
     
    272288
    273289        // now calculate the offset address
    274         // calculated according to W5100 datasheet page: 43
     290        // calculated according to W5100 datasheet page: 44
    275291
    276292        if ((offset + NumBytes) > (S0_RX_MASK + 1) )  // if data is turned over in RX-mem
     
    280296                for (U08 i = 0; i < upper_size; ++i)
    281297                {
    282                         eth_read_buffer[i] = w5100_read(start_address + i);
     298                        w5100_write(start_address + i, eth_write_buffer[i]);
    283299                }
    284300                for (U08 i = 0; i < lower_size; ++i)
    285301                {
    286                         eth_read_buffer[upper_size + i] = w5100_read(S0_RX_BASE + i);
     302                        w5100_write(S0_RX_BASE + i, eth_write_buffer[upper_size+i]);
    287303                }
    288304        }
     
    291307                for (U08 i = 0; i < NumBytes; ++i)
    292308                {
    293                         eth_read_buffer[i] = w5100_read(start_address + i);
     309                        w5100_write(start_address + i, eth_write_buffer[i]);
    294310                }
    295311        }
    296312
    297313        // inform W5100 about how much data was read out.
    298         set_S0_RX_RD(last_TX_write_pointer + NumBytes);
    299 
    300 
     314        set_S0_TX_WR(last_TX_write_pointer + NumBytes);
     315       
     316        // tell it to send now the data away
     317        w5100_write( S0_CR, CR_SEND);
     318       
    301319        return NumBytes;
    302320}
     321
  • firmware/FSC/src/w5100_spi_interface.h

    r10236 r10667  
    6969#define S0_IR           0x0402          // socket 0 interrupt           -- see bit description below
    7070#define S0_SR           0x0403          // socket 0 status                      -- see below
    71 #define S0_PORT0        0x0404          // socket 0 Port                        -- FSC might get port number 0x1F5C = 8028, since we have only one FSC in cam
    72 #define S0_PORT1        0x0405          // socket 0 Port                        -- 0xF5C1= 62913 is okay as well ...
     71#define S0_PORT0        0x0404          // socket 0 Port MSB                    -- FSC might get port number 0x1F5C = 8028, since we have only one FSC in cam
     72#define S0_PORT1        0x0405          // socket 0 Port LSB                    -- 0xF5C1= 62913 is okay as well ...
    7373#define S0_MSSR0        0x0412          // max segment size                     --
    7474#define S0_MSSR1        0x0413          // max segment size                     -- reset value is 0xFFFF; is set to other party value, if in TCP passive mode
     
    143143// NETWORK SETTING:
    144144// set GAR to FSC_GATEWAY_ADDRESS
    145 #define FSC_GATEWAY_ADDRESS0 0xC0               // 192.33.96.1
     145//#define FSC_GATEWAY_ADDRESS0 0xC0             // 192.33.96.1
     146//#define FSC_GATEWAY_ADDRESS1 0x21
     147//#define FSC_GATEWAY_ADDRESS2 0x60
     148//#define FSC_GATEWAY_ADDRESS3 0x01
     149
     150#define FSC_GATEWAY_ADDRESS0 0xC0               // 192.168.0.1
    146151#define FSC_GATEWAY_ADDRESS1 0x21
    147152#define FSC_GATEWAY_ADDRESS2 0x60
    148153#define FSC_GATEWAY_ADDRESS3 0x01
     154
     155
    149156// set SHAR to FSC_MAC_ADDRESS
    150157#define FSC_MAC_ADDRESS0 0xFA   //FA:C7:0F:AD:22:01
     
    155162#define FSC_MAC_ADDRESS5 0x01
    156163// set SUBR to FSC_SUBNET_MASK
    157 #define FSC_SUBNET_MASK0 0xFF   //255.255.248.0
    158 #define FSC_SUBNET_MASK1 0xFF
    159 #define FSC_SUBNET_MASK2 0xF8
    160 #define FSC_SUBNET_MASK3 0x00
     164#define FSC_SUBNET_MASK0 255    //255.255.248.0
     165#define FSC_SUBNET_MASK1 255
     166#define FSC_SUBNET_MASK2 255
     167#define FSC_SUBNET_MASK3 0
    161168// set SIPR to FSC_IP_ADDRESS
    162 #define FSC_IP_ADDRESS0 0xC0    // 192.33.99.247
    163 #define FSC_IP_ADDRESS1 0x21
    164 #define FSC_IP_ADDRESS2 0x63
    165 #define FSC_IP_ADDRESS3 0xF7
     169//#define FSC_IP_ADDRESS0 0xC0  // 192.33.99.247
     170//#define FSC_IP_ADDRESS1 0x21
     171//#define FSC_IP_ADDRESS2 0x63
     172//#define FSC_IP_ADDRESS3 0xF7
     173#define FSC_IP_ADDRESS0 192     // 192.168.0.2
     174#define FSC_IP_ADDRESS1 168
     175#define FSC_IP_ADDRESS2 0
     176#define FSC_IP_ADDRESS3 2
    166177//------------------------------------------------------------------------------
    167178// MEM SETTINGS:
     
    196207//-----------------------------------------------------------------------------
    197208#endif //__W5100_SPI_INTERFACE_H
     209
     210U16 get_S0_TX_FSR();
     211U16 get_S0_TX_RD();
     212U16 get_S0_TX_WR();
     213U16 get_S0_RX_RSR();
     214U16 get_S0_RX_RD();
     215U08 w5100_get_RX(U08 NumBytes, BOOL send_ACK);
     216void w5100_TX(U08 NumBytes, U08 *str);
     217U08 w5100_set_TX(U08 NumBytes);
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