Changeset 10639 for firmware/FTM
- Timestamp:
- 05/10/11 08:52:40 (14 years ago)
- Location:
- firmware/FTM
- Files:
-
- 5 edited
-
Clock_cond_interface/Clock_cond_interface.vhd (modified) (9 diffs)
-
FTM_central_control.vhd (modified) (3 diffs)
-
FTM_top.vhd (modified) (5 diffs)
-
ethernet/w5300_modul.vhd (modified) (16 diffs)
-
ftm_definitions.vhd (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd
r10260 r10639 20 20 -- modifications: February 21 2011 by Patrick Vogler 21 21 -- March 23 2011 by Patrick Vogler 22 -- May 03 2011 by Patrick Vogler and Quirin Weitzel 22 23 ---------------------------------------------------------------------------------- 23 24 … … 37 38 38 39 39 40 40 entity Clock_cond_interface is 41 41 port( 42 43 42 44 -- Clock45 -------------------------------------------------------------------------------46 clk : IN STD_LOGIC; -- 50 MHz system clock47 48 49 -- Clock conditioner LMK0300050 -------------------------------------------------------------------------------51 CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock52 LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable53 DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data54 55 SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization56 LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect57 58 59 -- Time Marker60 -------------------------------------------------------------------------------61 TIM_Sel : out STD_LOGIC;-- Time Marker selector43 -- Clock 44 ------------------------------------------------------------------------------- 45 clk : IN STD_LOGIC; -- 50 MHz system clock 46 47 48 -- Clock conditioner LMK03000 49 ------------------------------------------------------------------------------- 50 CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock 51 LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable 52 DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data 53 54 SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization 55 LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect 56 57 58 -- Time Marker 59 ------------------------------------------------------------------------------- 60 TIM_Sel : out STD_LOGIC; -- Time Marker selector 62 61 -- 1 = time marker from Clock conditioner 63 62 -- for DRS timing calibration … … 67 66 68 67 69 70 -- FPGA intern clock conditioner configuration data 71 ------------------------------------------------------------------------------- 72 cc_R0 : in std_logic_vector (31 downto 0) := (others => '0'); 73 cc_R1 : in std_logic_vector (31 downto 0) := (others => '0'); 74 cc_R8 : in std_logic_vector (31 downto 0) := (others => '0'); 75 cc_R9 : in std_logic_vector (31 downto 0) := (others => '0'); 76 cc_R11 : in std_logic_vector (31 downto 0) := (others => '0'); 77 cc_R13 : in std_logic_vector (31 downto 0) := (others => '0'); 78 cc_R14 : in std_logic_vector (31 downto 0) := (others => '0'); 79 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0'); 80 81 82 83 84 -- FPGA intern control signals 85 ------------------------------------------------------------------------------- 86 start_config : in STD_LOGIC; -- load new configuration into the clock 68 -- FPGA intern clock conditioner configuration data 69 ------------------------------------------------------------------------------- 70 cc_R0 : in std_logic_vector (31 downto 0) := (others => '0'); 71 cc_R1 : in std_logic_vector (31 downto 0) := (others => '0'); 72 cc_R8 : in std_logic_vector (31 downto 0) := (others => '0'); 73 cc_R9 : in std_logic_vector (31 downto 0) := (others => '0'); 74 cc_R11 : in std_logic_vector (31 downto 0) := (others => '0'); 75 cc_R13 : in std_logic_vector (31 downto 0) := (others => '0'); 76 cc_R14 : in std_logic_vector (31 downto 0) := (others => '0'); 77 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0'); 78 79 80 -- FPGA intern control signals 81 ------------------------------------------------------------------------------- 82 start_config : in STD_LOGIC; -- load new configuration into the clock 87 83 -- conditioner 88 84 89 config_started : out STD_LOGIC;-- indicates that the new configuration85 config_started : out STD_LOGIC; -- indicates that the new configuration 90 86 -- is currently loaded into the clock conditioner 91 87 92 config_done : out STD_LOGIC;-- indicates that the configuration has88 config_done : out STD_LOGIC; -- indicates that the configuration has 93 89 -- been loaded and the clock conditioners 94 90 -- PLL is locked 95 91 96 timemarker_select: in STD_LOGIC-- selects time marker source92 timemarker_select: in STD_LOGIC -- selects time marker source 97 93 -- 98 94 -- 1 = time marker from Clock conditioner … … 106 102 107 103 108 109 110 104 architecture Behavioral of Clock_cond_interface is 111 105 112 106 113 component microwire_interface IS114 PORT(107 component microwire_interface IS 108 PORT( 115 109 clk : IN std_logic; 116 110 clk_uwire : OUT std_logic; --- IN or OUT ? … … 121 115 config_ready : OUT std_logic; 122 116 config_started : OUT std_logic 123 ); 124 end component; 125 126 117 ); 118 end component; 127 119 128 120 129 121 signal clk_50M_sig : STD_LOGIC; -- system clock 130 --signal start_config_sig : STD_LOGIC;122 --signal start_config_sig : STD_LOGIC; 131 123 132 124 signal config_ready_sig : STD_LOGIC; … … 154 146 signal cc_R15_sig : std_logic_vector (31 downto 0); 155 147 156 148 signal timemarker_select_sig : std_logic := '0'; 149 150 type TIM_SEL_STATE_TYPE is (IDLE, CONFIG); 151 signal tim_sel_state : TIM_SEL_STATE_TYPE := IDLE; 157 152 158 153 … … 173 168 config_ready => config_ready_sig, 174 169 config_started => config_started_sig 175 170 ); 176 171 177 172 178 173 179 config_done <= config_ready_sig; -- indicates that the configuration174 --config_done <= config_ready_sig; -- indicates that the configuration 180 175 -- has been loaded 181 176 182 177 183 178 184 --config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration179 config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration 185 180 -- has been loaded and 186 181 -- the PLL is locked again … … 188 183 189 184 190 TIM_Sel <= timemarker_select; 185 --TIM_Sel <= timemarker_select; 186 187 TIM_Sel <= timemarker_select_sig; 188 189 tim_sel_proc : process (clk_uwire_sig) 190 begin 191 if rising_edge(clk_uwire_sig) then 192 case tim_sel_state is 193 when IDLE => 194 if start_config = '1' then 195 timemarker_select_sig <= '0'; 196 tim_sel_state <= CONFIG; 197 end if; 198 when CONFIG => 199 if config_ready_sig = '1' then 200 timemarker_select_sig <= timemarker_select; 201 tim_sel_state <= IDLE; 202 end if; 203 end case; 204 end if; 205 end process tim_sel_proc; 206 207 191 208 CLK_Clk_Cond <= clk_uwire_sig; 192 209 193 210 clk_50M_sig <= clk; 194 -- start_config_sig <= start_config; 195 196 -- start_config <= start_config_sig; 197 198 211 212 -- start_config_sig <= start_config; 213 -- start_config <= start_config_sig; 199 214 config_started <= config_started_sig; 200 215 … … 233 248 clk_cond_array_sig(14) <= cc_R15_sig; 234 249 235 236 250 end Behavioral; 237 238 -
firmware/FTM/FTM_central_control.vhd
r10441 r10639 80 80 start_run_num_events : IN std_logic_vector (31 DOWNTO 0); 81 81 trigger_start : out std_logic := '0'; 82 trigger_stop : out std_logic := '1' 82 trigger_stop : out std_logic := '1'; 83 enable_ID_sending : out std_logic := '0' 83 84 ); 84 85 end FTM_central_control; … … 248 249 trigger_start <= '1'; 249 250 trigger_stop <= '0'; 251 enable_Id_sending <= '1'; 250 252 if (new_config = '1') then 251 253 config_started <= '1'; … … 270 272 trigger_start <= '0'; 271 273 trigger_stop <= '1'; 274 enable_Id_sending <= '0'; 272 275 state_central_proc <= CP_RUNNING_02; 273 276 end if; -
firmware/FTM/FTM_top.vhd
r10441 r10639 122 122 123 123 SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization 124 LD_Clk_Cond : in STD_LOGIC; -- lock detect , should be checked for124 LD_Clk_Cond : in STD_LOGIC; -- lock detect 125 125 126 126 … … 400 400 signal trigger_start_sig : std_logic; 401 401 signal trigger_stop_sig : std_logic; 402 403 signal enable_ID_sending_sig : std_logic; 402 404 403 405 -- component FTM_clk_gen … … 561 563 start_run_num_events : IN std_logic_vector (31 DOWNTO 0); 562 564 trigger_start : out std_logic; 563 trigger_stop : out std_logic 565 trigger_stop : out std_logic; 566 enable_ID_sending : out std_logic 564 567 ); 565 568 end component; … … 942 945 start_run_num_events => start_run_num_events_sig, 943 946 trigger_start => trigger_start_sig, 944 trigger_stop => trigger_stop_sig 947 trigger_stop => trigger_stop_sig, 948 enable_ID_sending => enable_ID_sending_sig 945 949 ); 946 950 … … 1009 1013 rx_d_3 => Bus2_RxD_3, 1010 1014 tx_d_3 => Bus2_TxD_3, 1011 enable_ID_sending => '1', 1015 --enable_ID_sending => trigger_start_sig, 1016 enable_ID_sending => enable_ID_sending_sig, 1017 --enable_ID_sending => '1', 1012 1018 TIM_source => general_settings_sig(0), 1013 1019 LP_settings => "0000", -
firmware/FTM/ethernet/w5300_modul.vhd
r10441 r10639 18 18 -- 19 19 ---------------------------------------------------------------------------------- 20 -- hds interface_start 20 21 21 LIBRARY IEEE; 22 22 USE IEEE.STD_LOGIC_1164.all; … … 117 117 type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, 118 118 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 119 SI, SI 1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR,119 SI, SI0, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR, 120 120 READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL); 121 121 type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, 122 WR_WRITE_START_DEL, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_ FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01, WR_WRITE_END_DEL);122 WR_WRITE_START_DEL, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_SD_ADDR, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01, WR_WRITE_END_DEL); 123 123 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); 124 124 type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); … … 179 179 signal cmd_array : cmd_array_type; 180 180 signal internal_cmd : std_logic := '0'; 181 signal wait_for_data_flag : std_logic := '0'; 181 182 182 183 signal autosend_flag : std_logic := '1'; … … 461 462 par_data <= X"0101"; -- ALIGN, TCP 462 463 state_init <= WRITE_REG; 464 next_state <= SI0; 465 -- keep alive 466 when SI0 => 467 par_addr <= W5300_S0_KPALVTR + socket_cnt * W5300_S_INC; 468 par_data <= X"0C00"; -- 12 * 5s = 60s 469 state_init <= WRITE_REG; 463 470 next_state <= SI1; 464 471 -- Sx Interrupt Mask … … 520 527 ftu_error_send_ready <= '0'; 521 528 led_int <= X"00"; 529 wait_for_data_flag <= '0'; 522 530 -- -- -- 523 531 else … … 560 568 state_init <= READ_DATA; 561 569 busy <= '1'; 562 elsif ( dd_send = '1') then570 elsif ((dd_send = '1') and (wait_for_data_flag = '0')) then 563 571 internal_cmd <= '1'; 564 572 dd_send_ack <= '1'; … … 569 577 state_read_data <= RD_READ_DD_BLOCK; 570 578 state_init <= READ_DATA; 571 elsif ( ftu_error_send = '1') then579 elsif ((ftu_error_send = '1') and (wait_for_data_flag = '0')) then 572 580 ftu_error_send_ack <= '1'; 573 581 ftu_error_send_ready <= '0'; … … 697 705 when PAR_START_X_EVNTS => 698 706 next_state_read_data <= RD_X_EVNTS; 707 wait_for_data_flag <= '1'; 699 708 state_read_data <= RD_5; 700 709 when others => … … 721 730 -- write to address in static data block 722 731 when PAR_WRITE_SD_ADDR => 723 new_config_flag <= '1';732 wait_for_data_flag <= '1'; 724 733 next_state_read_data <= RD_WRITE_SD_ADDR; 725 734 state_read_data <= RD_5; 726 735 -- write static data block 727 736 when PAR_WRITE_SD => 728 new_config_flag <= '1';737 wait_for_data_flag <= '1'; 729 738 next_state_read_data <= RD_WRITE_SD_BLOCK; 730 739 state_read_data <= RD_5; … … 737 746 -- read from address in static data block 738 747 when PAR_READ_SD_ADDR => 748 wait_for_data_flag <= '1'; 739 749 next_state_read_data <= RD_READ_SD_ADDR; 740 750 state_read_data <= RD_5; … … 865 875 local_write_length <= '0' & X"0001"; -- one word will be written to ethernet 866 876 next_state_read_data <= RD_CMD; 877 wait_for_data_flag <= '0'; 867 878 next_state <= READ_DATA; 868 879 state_init <= WRITE_DATA; … … 879 890 if (next_packet_data_cnt = (SD_BLOCK_SIZE - 1)) then 880 891 next_packet_data_cnt <= 0; 892 wait_for_data_flag <= '0'; 893 new_config_flag <= '1'; 881 894 next_state_read_data <= RD_CMD; 882 895 end if; … … 891 904 local_sd_data <= data_read; 892 905 next_packet_data_cnt <= 0; 906 wait_for_data_flag <= '0'; 907 new_config_flag <= '1'; 893 908 next_state_read_data <= RD_CMD; 894 909 next_state <= READ_DATA; … … 907 922 start_run <= '0'; 908 923 next_packet_data_cnt <= 0; 924 wait_for_data_flag <= '0'; 909 925 next_state_read_data <= RD_CMD; 910 926 state_read_data <= RD_5; … … 1106 1122 1107 1123 -- Fill FIFO 1124 -- write header 1108 1125 when WR_FIFO_HEADER => 1109 1126 state_init <= READ_FROM_HEADER_MODUL; … … 1120 1137 state_write <= WR_FIFO_HEADER; 1121 1138 else 1122 state_write <= WR_FIFO_DATA; 1123 end if; 1124 1139 if (data_package_type = FTM_PACKAGE_TYPE_SD_WORD) then 1140 state_write <= WR_SD_ADDR; 1141 else 1142 state_write <= WR_FIFO_DATA; 1143 end if; 1144 end if; 1145 1146 -- write static data ram address (only for single address request) 1147 when WR_SD_ADDR => 1148 write_length_bytes <= write_length_bytes + 2; -- one extra word to write 1149 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 1150 par_data <= "0000" & local_sd_addr; 1151 state_init <= WRITE_REG; 1152 next_state <= WRITE_DATA; 1153 state_write <= WR_FIFO_DATA; 1154 1155 -- write data 1125 1156 when WR_FIFO_DATA => 1126 1157 state_init <= read_addr_state; -
firmware/FTM/ftm_definitions.vhd
r10441 r10639 46 46 -- changed FTM_HEADER_LENGTH to 0x0E 47 47 -- kw 20.04.: added "package types", SD_SINGLE_WORD_SIZE 48 -- 49 -- kw 28.04.: changed SD_SINGLE_WORD_SIZE to X"002", added W5300_S0_KPALVTR (keep alive) 48 50 -- 49 51 ---------------------------------------------------------------------------------- … … 189 191 constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12"; 190 192 constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14"; 193 constant W5300_S0_KPALVTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"1A"; 191 194 constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20"; 192 195 constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24"; … … 270 273 constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3) 271 274 constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block 272 constant SD_SINGLE_WORD_SIZE : std_logic_vector := X"00 1";275 constant SD_SINGLE_WORD_SIZE : std_logic_vector := X"002"; 273 276 274 277 -- dynamic data block
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