Changeset 10740 for firmware/FTM
- Timestamp:
- 05/18/11 13:59:12 (14 years ago)
- Location:
- firmware/FTM
- Files:
-
- 8 edited
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Clock_cond_interface/Clock_cond_interface.vhd (modified) (10 diffs)
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FTM_central_control.vhd (modified) (27 diffs)
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FTM_top.vhd (modified) (7 diffs)
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FTM_top_tb.vhd (modified) (7 diffs)
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ethernet/w5300_modul.vhd (modified) (18 diffs)
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ftm_board.ucf (modified) (2 diffs)
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ftm_definitions.vhd (modified) (2 diffs)
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ftu_control/FTM_ftu_control.vhd (modified) (7 diffs)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd
r10639 r10740 45 45 clk : IN STD_LOGIC; -- 50 MHz system clock 46 46 47 48 47 -- Clock conditioner LMK03000 49 48 ------------------------------------------------------------------------------- … … 55 54 LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect 56 55 57 58 56 -- Time Marker 59 57 ------------------------------------------------------------------------------- … … 65 63 -- operation / physics run 66 64 67 68 65 -- FPGA intern clock conditioner configuration data 69 66 ------------------------------------------------------------------------------- … … 77 74 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0'); 78 75 79 80 76 -- FPGA intern control signals 81 77 ------------------------------------------------------------------------------- … … 97 93 -- 0 = time marker from FPGA for normal 98 94 -- operation / physics run 99 95 100 96 ); 101 97 end Clock_cond_interface; … … 103 99 104 100 architecture Behavioral of Clock_cond_interface is 105 106 101 107 102 component microwire_interface IS 108 103 PORT( 109 104 clk : IN std_logic; 110 clk_uwire : OUT std_logic; --- IN or OUT ?105 clk_uwire : OUT std_logic; 111 106 data_uwire : OUT std_logic; 112 107 le_uwire : OUT std_logic; … … 118 113 end component; 119 114 120 121 signal clk_50M_sig : STD_LOGIC; -- system clock 122 --signal start_config_sig : STD_LOGIC; 123 115 signal clk_50M_sig : STD_LOGIC; -- system clock (50MHz) 116 signal clk_uwire_sig : STD_LOGIC; -- 2 MHz 117 124 118 signal config_ready_sig : STD_LOGIC; 125 signal clk_uwire_sig : STD_LOGIC;126 127 119 signal config_started_sig : STD_LOGIC; 128 120 … … 151 143 signal tim_sel_state : TIM_SEL_STATE_TYPE := IDLE; 152 144 145 signal load_detect_sr : std_logic_vector (1 downto 0) := "00"; 153 146 154 147 begin … … 162 155 clk_cond_array => clk_cond_array_sig, 163 156 config_start => start_config, 164 165 -- config_start => start_config_sig,166 -- config_start <= start_config_sig,167 168 157 config_ready => config_ready_sig, 169 158 config_started => config_started_sig 170 159 ); 171 160 172 173 161 sync_ld_proc : process (clk_uwire_sig) 162 begin 163 if rising_edge(clk_uwire_sig) then 164 load_detect_sr <= load_detect_sr(0) & LD_Clk_Cond; 165 end if; 166 end process sync_ld_proc; 167 174 168 --config_done <= config_ready_sig; -- indicates that the configuration 175 169 -- has been loaded 176 170 177 178 179 config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration 171 --config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration 180 172 -- has been loaded and 181 -- the PLL is locked again 182 183 184 185 --TIM_Sel <= timemarker_select; 186 173 -- the PLL has locked 174 175 config_done <= config_ready_sig and (load_detect_sr(1) and load_detect_sr(0)); 176 187 177 TIM_Sel <= timemarker_select_sig; 188 178 189 179 tim_sel_proc : process (clk_uwire_sig) 190 180 begin … … 205 195 end process tim_sel_proc; 206 196 207 208 197 CLK_Clk_Cond <= clk_uwire_sig; 209 198 210 199 clk_50M_sig <= clk; 211 200 212 -- start_config_sig <= start_config;213 -- start_config <= start_config_sig;214 201 config_started <= config_started_sig; 215 202 -
firmware/FTM/FTM_central_control.vhd
r10639 r10740 77 77 stop_run_ack : OUT std_logic := '0'; 78 78 current_cc_state : OUT std_logic_vector (15 DOWNTO 0) := X"FFFF"; 79 cc_state_test : OUT std_logic_vector ( 7 downto 0) := X"FF"; 79 80 start_run_param : IN std_logic_vector (15 DOWNTO 0); 80 81 start_run_num_events : IN std_logic_vector (31 DOWNTO 0); … … 87 88 architecture Behavioral of FTM_central_control is 88 89 89 signal reset_scaler_sig : std_logic := '0';90 signal reset_period_sig : std_logic := '0';91 signal scaler_counts_sig : integer := 0;92 signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);93 signal period_finished_sig : std_logic := '0';94 signal wait_cnt_sig : integer range 0 to 10 := 0;95 signal new_period_sr_sig : std_logic_vector(1 downto 0) := (others => '0');96 signal new_period_sig : std_logic := '0';97 signal new_period_ack_sig : std_logic := '0';98 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111";90 signal reset_scaler_sig : std_logic := '0'; 91 signal reset_period_sig : std_logic := '0'; 92 signal scaler_counts_sig : integer := 0; 93 signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER); 94 signal period_finished_sig : std_logic := '0'; 95 signal wait_cnt_sig : integer range 0 to 10 := 0; 96 signal new_period_sr_sig : std_logic_vector(1 downto 0) := (others => '0'); 97 signal new_period_sig : std_logic := '0'; 98 signal new_period_ack_sig : std_logic := '0'; 99 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111"; 99 100 100 101 type state_central_proc_type is (CP_INIT, CP_INIT_DNA, … … 114 115 begin 115 116 116 central_proc : process (clk, prescaling_FTU01) 117 --central_proc : process (clk, prescaling_FTU01) 118 central_proc : process (clk) 117 119 begin 118 120 if rising_edge (clk) then … … 120 122 121 123 when CP_INIT => -- wait for DCMs to lock 124 current_cc_state <= X"FFFF"; 125 --cc_state_test <= X"00"; 126 cc_state_test <= X"19"; 122 127 if (clk_ready = '1') then 123 128 state_central_proc <= CP_INIT_DNA; 124 129 end if; 125 130 126 when CP_INIT_DNA => -- get FPGA DNA 131 when CP_INIT_DNA => -- get FPGA DNA 132 current_cc_state <= X"FFFF"; 133 cc_state_test <= X"01"; 127 134 if (dna_ready = '1') then 128 135 state_central_proc <= CP_CONFIG; … … 134 141 135 142 when CP_CONFIG_START => 143 current_cc_state <= FTM_STATE_CFG; 144 cc_state_test <= X"02"; 136 145 if (config_started_ack = '1') then 137 146 config_started <= '0'; … … 140 149 141 150 when CP_CONFIG => 151 current_cc_state <= FTM_STATE_CFG; 152 cc_state_test <= X"03"; 142 153 config_start_eth <= '1'; 143 154 if (config_started_eth = '1') then … … 147 158 148 159 when CP_CONFIG_01 => 160 current_cc_state <= FTM_STATE_CFG; 161 cc_state_test <= X"04"; 149 162 if (config_ready_eth = '1') then 150 163 state_central_proc <= CP_CONFIG_CC; … … 154 167 155 168 when CP_CONFIG_CC => 169 current_cc_state <= FTM_STATE_CFG; 170 cc_state_test <= X"05"; 156 171 config_start_cc <= '1'; 157 172 if (config_started_cc = '1') then … … 161 176 162 177 when CP_CONFIG_CC_01 => 178 current_cc_state <= FTM_STATE_CFG; 179 cc_state_test <= X"06"; 163 180 if (config_ready_cc = '1') then 164 181 state_central_proc <= CP_CONFIG_FTU; … … 166 183 167 184 when CP_CONFIG_FTU => 185 current_cc_state <= FTM_STATE_CFG; 186 cc_state_test <= X"07"; 168 187 config_start_ftu <= '1'; 169 188 if (config_started_ftu = '1') then … … 173 192 174 193 when CP_CONFIG_FTU_01 => 194 current_cc_state <= FTM_STATE_CFG; 195 cc_state_test <= X"08"; 175 196 if (config_ready_ftu = '1') then 176 197 state_central_proc <= CP_CONFIG_SCALER; … … 178 199 179 200 when CP_CONFIG_SCALER => 201 current_cc_state <= FTM_STATE_CFG; 202 cc_state_test <= X"09"; 180 203 prescaling_FTU01_sig <= prescaling_FTU01; 181 204 --reset_period_sig <= '1'; … … 183 206 184 207 when CP_CONFIG_SCALER_01 => 208 current_cc_state <= FTM_STATE_CFG; 209 cc_state_test <= X"0A"; 185 210 --reset_period_sig <= '0'; 186 211 if wait_cnt_sig < 5 then … … 195 220 196 221 when CP_CONFIG_TRIGGER => 222 current_cc_state <= FTM_STATE_CFG; 223 cc_state_test <= X"0B"; 197 224 --config trigger_manager block 198 225 config_trigger <= '1'; … … 200 227 201 228 when CP_CONFIG_TRIGGER_01 => 229 current_cc_state <= FTM_STATE_CFG; 230 cc_state_test <= X"0C"; 202 231 config_trigger <= '0'; 203 232 if (config_trigger_done = '1') then … … 207 236 when CP_IDLE => 208 237 current_cc_state <= FTM_STATE_IDLE; 238 cc_state_test <= X"0D"; 209 239 stop_run_ack <= '1'; 210 240 start_run_ack <= '0'; … … 238 268 when CP_RUNNING => 239 269 current_cc_state <= FTM_STATE_RUN; 270 cc_state_test <= X"0E"; 240 271 if (start_run = '0') then 241 272 start_run_ack <= '0'; … … 246 277 when CP_RUNNING_01 => 247 278 current_cc_state <= FTM_STATE_RUN; 279 cc_state_test <= X"0F"; 248 280 start_run_ack <= '1'; 249 281 trigger_start <= '1'; … … 277 309 278 310 when CP_RUNNING_02 => 311 current_cc_state <= FTM_STATE_RUN; 312 cc_state_test <= X"10"; 279 313 if (stop_run = '0') then 280 314 stop_run_ack <= '0'; … … 283 317 284 318 when CP_CONFIG_ACK => 319 current_cc_state <= FTM_STATE_CFG; 320 cc_state_test <= X"11"; 285 321 if (config_started_ack = '1') then 286 322 config_started <= '0'; … … 289 325 290 326 when CP_PING => 327 cc_state_test <= X"12"; 291 328 if (ping_ftu_ready_ftu = '1') then 292 329 if (ping_ftu_start = '0') then … … 299 336 300 337 when CP_START_RATES => 338 cc_state_test <= X"13"; 301 339 new_period_ack_sig <= '0'; 302 340 dd_block_start_ftu <= '1'; … … 309 347 310 348 when CP_READ_RATES => 349 cc_state_test <= X"14"; 311 350 new_period_ack_sig <= '0'; 312 351 if (rates_started_ftu = '1') then … … 316 355 317 356 when CP_READ_RATES_01 => 357 cc_state_test <= X"15"; 318 358 if (rates_ready_ftu = '1') then 319 359 dd_block_ready_ftu <= '1'; … … 326 366 327 367 when CP_SEND_START => 368 cc_state_test <= X"16"; 328 369 dd_send <= '1'; 329 370 if (dd_send_ack = '1') then … … 333 374 334 375 when CP_SEND_END => 376 cc_state_test <= X"17"; 335 377 if (dd_send_ready = '1') then 336 378 --state_central_proc <= CP_IDLE; … … 338 380 end if; 339 381 382 when others => 383 cc_state_test <= X"18"; 384 340 385 end case; 341 386 end if; -
firmware/FTM/FTM_top.vhd
r10639 r10740 177 177 -- on IO-Bank 3 178 178 ------------------------------------------------------------------------------- 179 --Crate_Res0 : out STD_LOGIC;180 --Crate_Res1 : out STD_LOGIC;181 --Crate_Res2 : out STD_LOGIC;182 --Crate_Res3 : out STD_LOGIC;179 Crate_Res0 : out STD_LOGIC; 180 Crate_Res1 : out STD_LOGIC; 181 Crate_Res2 : out STD_LOGIC; 182 Crate_Res3 : out STD_LOGIC; 183 183 184 184 … … 220 220 TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker 221 221 TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 222 TIM_Sel : out STD_LOGIC -- Time Marker selector on IO-Bank 2222 TIM_Sel : out STD_LOGIC; -- Time Marker selector on IO-Bank 2 223 223 224 224 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA … … 253 253 -- Testpoints 254 254 ------------------------------------------------------------------------------- 255 -- TP : inout STD_LOGIC_VECTOR(32 downto 0);255 TP : inout STD_LOGIC_VECTOR(32 downto 0) 256 256 -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only 257 257 … … 395 395 signal stop_run_ack_sig : std_logic; 396 396 signal current_cc_state_sig : std_logic_vector (15 DOWNTO 0); 397 signal cc_state_test_sig : std_logic_vector ( 7 downto 0); 397 398 signal start_run_param_sig : std_logic_vector (15 DOWNTO 0); 398 399 signal start_run_num_events_sig : std_logic_vector (31 DOWNTO 0); … … 560 561 stop_run_ack : OUT std_logic; 561 562 current_cc_state : OUT std_logic_vector (15 DOWNTO 0); 563 cc_state_test : OUT std_logic_vector ( 7 downto 0); 562 564 start_run_param : IN std_logic_vector (15 DOWNTO 0); 563 565 start_run_num_events : IN std_logic_vector (31 DOWNTO 0); … … 942 944 stop_run_ack => stop_run_ack_sig, 943 945 current_cc_state => current_cc_state_sig, 946 cc_state_test => cc_state_test_sig, 944 947 start_run_param => start_run_param_sig, 945 948 start_run_num_events => start_run_num_events_sig, … … 1149 1152 LED_ye <= led_sig(5 downto 4); 1150 1153 LED_gn <= led_sig(7 downto 6); 1154 1155 TP(32 downto 8) <= (others => '0'); 1156 --TP(8) <= clk_50M_sig; 1157 TP( 7 downto 0) <= cc_state_test_sig; 1158 1159 Crate_Res0 <= '1'; 1160 Crate_Res1 <= '1'; 1161 Crate_Res2 <= '1'; 1162 Crate_Res3 <= '1'; 1151 1163 1152 1164 end Behavioral; -
firmware/FTM/FTM_top_tb.vhd
r10418 r10740 175 175 -- Crate-Resets 176 176 ------------------------------------------------------------------------------- 177 --Crate_Res0 : out STD_LOGIC;178 --Crate_Res1 : out STD_LOGIC;179 --Crate_Res2 : out STD_LOGIC;180 --Crate_Res3 : out STD_LOGIC;177 Crate_Res0 : out STD_LOGIC; 178 Crate_Res1 : out STD_LOGIC; 179 Crate_Res2 : out STD_LOGIC; 180 Crate_Res3 : out STD_LOGIC; 181 181 182 182 … … 215 215 216 216 TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker 217 TIM_Run_n : out STD_LOGIC -- TIM_Run-217 TIM_Run_n : out STD_LOGIC; -- TIM_Run- 218 218 -- TIM_Sel : out STD_LOGIC; -- Time Marker selector 219 219 … … 248 248 -- Testpoints 249 249 ------------------------------------------------------------------------------- 250 -- TP : inout STD_LOGIC_VECTOR(32 downto 0);250 TP : inout STD_LOGIC_VECTOR(32 downto 0) 251 251 -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only 252 252 … … 290 290 signal W_T_sig : STD_LOGIC_VECTOR(3 downto 0) := (others => '0'); 291 291 signal SIO_sig : STD_LOGIC := '0'; 292 signal TP_sig : STD_LOGIC_VECTOR(32 downto 0) := (others => '0'); 292 293 293 294 --Outputs … … 405 406 Bus2_RxD_3 => Bus2_RxD_3_sig, 406 407 Bus2_TxD_3 => Bus2_TxD_3_sig, 407 --Crate_Res0 => Crate_Res0_sig,408 --Crate_Res1 => Crate_Res1_sig,409 --Crate_Res2 => Crate_Res2_sig,410 --Crate_Res3 => Crate_Res3_sig,408 Crate_Res0 => Crate_Res0_sig, 409 Crate_Res1 => Crate_Res1_sig, 410 Crate_Res2 => Crate_Res2_sig, 411 Crate_Res3 => Crate_Res3_sig, 411 412 Busy0 => Busy0_sig, 412 413 Busy1 => Busy1_sig, … … 418 419 TRG_n => TRG_n_sig, 419 420 TIM_Run_p => TIM_Run_p_sig, 420 TIM_Run_n => TIM_Run_n_sig 421 TIM_Run_n => TIM_Run_n_sig, 421 422 -- TIM_Sel => TIM_Sel_sig, 422 423 -- Cal_0_p => Cal_0_p_sig, … … 435 436 -- Cal_6_n => Cal_6_n_sig, 436 437 -- Cal_7_p => Cal_7_p_sig, 437 -- Cal_7_n => Cal_7_n_sig 438 -- Cal_7_n => Cal_7_n_sig, 439 TP => TP_sig 438 440 ); 439 441 -
firmware/FTM/ethernet/w5300_modul.vhd
r10639 r10740 18 18 -- 19 19 ---------------------------------------------------------------------------------- 20 21 20 LIBRARY IEEE; 22 21 USE IEEE.STD_LOGIC_1164.all; … … 118 117 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 119 118 SI, SI0, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR, 120 READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_ FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL);119 READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_DD_BLOCK, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL); 121 120 type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, 122 121 WR_WRITE_START_DEL, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_SD_ADDR, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01, WR_WRITE_END_DEL); 123 122 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); 124 123 type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); 125 type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_CMD, RD_CMD_PARSE, RD_PING, RD_WRITE_SD_ADDR, RD_READ_SD_ADDR, RD_READ_SD_BLOCK, RD_ READ_DD_BLOCK, RD_WRITE_SD_BLOCK, RD_X_EVNTS,RD_END);124 type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_CMD, RD_CMD_PARSE, RD_PING, RD_WRITE_SD_ADDR, RD_READ_SD_ADDR, RD_READ_SD_BLOCK, RD_WRITE_SD_BLOCK, RD_X_EVNTS,RD_END); 126 125 type state_write_sd_type is (WRITE_SD_START, WRITE_SD_WAIT, WRITE_SD_END); 127 126 type state_read_sd_type is (READ_SD_START, READ_SD_WAIT, READ_SD_END); … … 131 130 type state_read_dd_block_type is (READ_DD_BLOCK_START, READ_DD_BLOCK_WRITE_GENERAL, READ_DD_BLOCK_WRITE, READ_DD_BLOCK_END, READ_DD_BLOCK_INTERN); 132 131 type state_send_ftu_error_type is (SFE_START, SFE_END); 132 type state_rd_x_evnts_type is (RD_X_01, RD_X_02, RD_X_03); 133 133 134 134 signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; … … 153 153 signal state_read_dd_block : state_read_dd_block_type := READ_DD_BLOCK_START; 154 154 signal state_send_ftu_error : state_send_ftu_error_type := SFE_START; 155 155 signal state_rd_x_evnts : state_rd_x_evnts_type := RD_X_01; 156 156 157 157 signal interrupt_ignore : std_logic := '1'; … … 460 460 when SI => 461 461 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC; 462 par_data <= X"0101"; -- ALIGN, TCP462 par_data <= X"0101"; -- 0x0101: ALIGN, TCP 463 463 state_init <= WRITE_REG; 464 464 next_state <= SI0; … … 554 554 new_config <= '1'; 555 555 config_started_ack <= '0'; 556 state_init <= MAIN; 557 558 -- main "loop" 559 when MAIN => 556 560 if (config_started = '1') then 557 561 new_config <= '0'; 558 562 config_started_ack <= '1'; 559 state_init <= MAIN;560 563 end if; 561 562 -- main "loop"563 when MAIN =>564 564 chk_recv_cntr <= chk_recv_cntr + 1; 565 565 if (chk_recv_cntr = 1000) then 566 566 chk_recv_cntr <= 0; 567 state_read_data <= RD_1;568 567 state_init <= READ_DATA; 569 568 busy <= '1'; … … 575 574 state_read_dd_block <= READ_DD_BLOCK_END; 576 575 end if; 577 state_read_data <= RD_READ_DD_BLOCK; 578 state_init <= READ_DATA; 576 state_init <= READ_DD_BLOCK; 579 577 elsif ((ftu_error_send = '1') and (wait_for_data_flag = '0')) then 580 578 ftu_error_send_ack <= '1'; … … 587 585 588 586 587 -- read dynamic data block and write it to ethernet 588 when READ_DD_BLOCK => 589 case state_read_dd_block is 590 when READ_DD_BLOCK_START => 591 dd_block_start <= '1'; 592 dd_block_ready <= '0'; 593 if (dd_block_start_ack = '1') then 594 dd_block_start <= '0'; 595 state_read_dd_block <= READ_DD_BLOCK_WRITE_GENERAL; 596 end if; 597 -- write on-time counter and tempertures to dd-block 598 when READ_DD_BLOCK_WRITE_GENERAL => 599 dd_write_general <= '1'; 600 if (dd_write_general_started = '1') then 601 dd_write_general <= '0'; 602 state_read_dd_block <= READ_DD_BLOCK_WRITE; 603 end if; 604 -- write dd-block to ethernet when on-time counter and temperatures are ready 605 when READ_DD_BLOCK_WRITE => 606 if (dd_write_general_ready = '1') then 607 data_package_type <= FTM_PACKAGE_TYPE_DD; 608 data_package_length <= DD_BLOCK_SIZE + 1; -- +1 := package end 609 read_addr_state <= READ_FROM_DD_ADDR; 610 local_sd_addr <= X"000"; -- start at address 0x000 611 local_write_length <= "00000" & DD_BLOCK_SIZE; 612 state_read_dd_block <= READ_DD_BLOCK_END; 613 next_state <= READ_DD_BLOCK; 614 state_init <= WRITE_DATA; 615 end if; 616 when READ_DD_BLOCK_END => 617 dd_block_ready <= '1'; 618 if (internal_cmd = '1') then 619 state_read_dd_block <= READ_DD_BLOCK_INTERN; 620 else 621 next_state_read_data <= RD_CMD; 622 state_read_dd_block <= READ_DD_BLOCK_START; 623 state_init <= READ_DATA; 624 state_read_data <= RD_5; 625 end if; 626 when READ_DD_BLOCK_INTERN => 627 if (dd_send = '0') then 628 dd_send_ready <= '1'; 629 dd_send_ack <= '0'; 630 internal_cmd <= '0'; 631 state_read_dd_block <= READ_DD_BLOCK_START; 632 state_init <= MAIN; 633 end if; 634 end case; -- state_read_dd_block 635 589 636 -- send FTU error message 590 637 when SEND_FTU_ERROR => … … 632 679 else 633 680 busy <= '0'; 681 state_read_data <= RD_1; 634 682 state_init <= MAIN; 635 683 end if; … … 646 694 647 695 when RD_END => 696 state_read_data <= RD_1; 648 697 if (new_config_flag = '1') then 649 698 new_config_flag <= '0'; … … 652 701 next_state <= MAIN; 653 702 end if; 654 if (internal_cmd = '0') then 655 par_addr <= W5300_S0_CR; 656 par_data <= X"0040"; -- RECV 657 state_init <= WRITE_REG; 658 else 659 internal_cmd <= '0'; 660 state_init <= MAIN; 661 end if; 703 par_addr <= W5300_S0_CR; 704 par_data <= X"0040"; -- RECV 705 state_init <= WRITE_REG; 662 706 663 707 … … 701 745 start_run <= '0'; 702 746 state_read_data <= RD_5; 747 else 748 state_init <= MAIN; 703 749 end if; 704 750 -- start run an take X events … … 716 762 stop_run <= '0'; 717 763 state_read_data <= RD_5; 764 else 765 state_init <= MAIN; 718 766 end if; 719 767 … … 724 772 crate_reset <= '0'; 725 773 state_read_data <= RD_5; 774 else 775 state_init <= MAIN; 726 776 end if; 727 777 … … 754 804 -- read dynamic data block 755 805 when PAR_READ_DD => 756 state_read_data <= RD_READ_DD_BLOCK; 806 state_init <= READ_DD_BLOCK; 807 state_read_data <= RD_5; 757 808 when others => 758 809 state_read_data <= RD_5; … … 788 839 ping_ftu_start <= '0'; 789 840 state_ping <= PING_WAIT; 841 else 842 state_init <= MAIN; 790 843 end if; 791 844 when PING_WAIT => 792 845 if (ping_ftu_ready = '1') then 793 846 state_ping <= PING_WRITE_LIST; 847 else 848 state_init <= MAIN; 794 849 end if; 795 850 when PING_WRITE_LIST => … … 803 858 next_state <= READ_DATA; 804 859 state_init <= WRITE_DATA; 805 end case;806 807 -- read dynamic data block and write it to ethernet808 when RD_READ_DD_BLOCK =>809 case state_read_dd_block is810 when READ_DD_BLOCK_START =>811 dd_block_start <= '1';812 dd_block_ready <= '0';813 if (dd_block_start_ack = '1') then814 dd_block_start <= '0';815 state_read_dd_block <= READ_DD_BLOCK_WRITE_GENERAL;816 end if;817 -- write on-time counter and tempertures to dd-block818 when READ_DD_BLOCK_WRITE_GENERAL =>819 dd_write_general <= '1';820 if (dd_write_general_started = '1') then821 dd_write_general <= '0';822 state_read_dd_block <= READ_DD_BLOCK_WRITE;823 end if;824 -- write dd-block to ethernet when on-time counter and temperatures are ready825 when READ_DD_BLOCK_WRITE =>826 if (dd_write_general_ready = '1') then827 data_package_type <= FTM_PACKAGE_TYPE_DD;828 data_package_length <= DD_BLOCK_SIZE + 1; -- +1 := package end829 read_addr_state <= READ_FROM_DD_ADDR;830 local_sd_addr <= X"000"; -- start at address 0x000831 local_write_length <= "00000" & DD_BLOCK_SIZE;832 state_read_dd_block <= READ_DD_BLOCK_END;833 next_state <= READ_DATA;834 state_init <= WRITE_DATA;835 end if;836 when READ_DD_BLOCK_END =>837 dd_block_ready <= '1';838 next_state_read_data <= RD_CMD;839 --840 if (internal_cmd = '1') then841 state_read_dd_block <= READ_DD_BLOCK_INTERN;842 else843 state_read_dd_block <= READ_DD_BLOCK_START;844 state_read_data <= RD_5;845 end if;846 when READ_DD_BLOCK_INTERN =>847 if (dd_send = '0') then848 dd_send_ready <= '1';849 dd_send_ack <= '0';850 state_read_dd_block <= READ_DD_BLOCK_START;851 state_read_data <= RD_5;852 end if;853 854 860 end case; 855 861 … … 913 919 -- read X events 914 920 when RD_X_EVNTS => 915 if (next_packet_data_cnt = 0) then916 start_run_num_events (31 downto 16) <= data_read;917 else918 start_run_num_events (15 downto 0) <= data_read;919 start_run_param <= cmd_array (2);920 start_run <= '1';921 if (start_run_ack = '1') then922 start_run <= '0';923 next_packet_data_cnt <= 0;921 case state_rd_x_evnts is 922 when RD_X_01 => 923 start_run_num_events (31 downto 16) <= data_read; 924 state_read_data <= RD_5; 925 state_rd_x_evnts <= RD_X_02; 926 when RD_X_02 => 927 start_run_num_events (15 downto 0) <= data_read; 928 start_run_param <= cmd_array (2); 929 start_run <= '1'; 924 930 wait_for_data_flag <= '0'; 925 next_state_read_data <= RD_CMD; 926 state_read_data <= RD_5; 927 end if; 928 end if; 929 931 state_rd_x_evnts <= RD_X_03; 932 when RD_X_03 => 933 if (start_run_ack = '1') then 934 start_run <= '0'; 935 state_rd_x_evnts <= RD_X_01; 936 next_state_read_data <= RD_CMD; 937 state_read_data <= RD_5; 938 else 939 state_init <= MAIN; 940 end if; 941 end case; 942 930 943 end case; -- state_read_data 931 944 -
firmware/FTM/ftm_board.ucf
r10418 r10740 251 251 # on IO-Bank 3 252 252 ####################################################### 253 #NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #254 #NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #255 #NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #256 #NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #253 NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 254 NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 255 NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 256 NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 257 257 258 258 … … 330 330 # Connector T7 331 331 # IO-Bank 0 332 #NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; #333 #NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; #334 #NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; #335 #NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; #332 NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; # 333 NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; # 334 NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; # 335 NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; # 336 336 337 337 # Connector T10 338 338 # IO-Bank 0 339 #NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; #340 #NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; #341 #NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; #342 #NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; #339 NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; # 340 NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; # 341 NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; # 342 NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; # 343 343 344 344 # on Connector T12 345 345 # IO-Bank 0 346 #NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; #347 #NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; #346 NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; # 347 NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; # 348 348 349 349 # on Connector T14 350 350 # IO-Bank 0 351 #NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; #352 #NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; #353 #NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; #354 #NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; #351 NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; # 352 NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; # 353 NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; # 354 NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; # 355 355 356 356 # on Connector T16 357 357 # IO-Bank 0 358 #NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; #359 #NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; #360 #NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; #361 #NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; #358 NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; # 359 NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; # 360 NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; # 361 NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; # 362 362 363 363 # on Connector T8 364 364 # IO-Bank 0 365 #NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; #366 #NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; #367 #NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; #368 #NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; #365 NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; # 366 NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; # 367 NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; # 368 NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; # 369 369 370 370 # on Connector T9 371 371 # IO-Bank 0 372 #NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; #373 #NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; #372 NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; # 373 NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; # 374 374 375 375 # on Connector T11 376 376 # IO-Bank 3 377 #NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; #378 #NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; #379 #NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; #380 #NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; #377 NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; # 378 NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; # 379 NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; # 380 NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; # 381 381 382 382 # on Connector T13 383 383 # IO-Bank 3 384 #NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; #385 #NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; #386 #NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; #387 #NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; #384 NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; # 385 NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; # 386 NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; # 387 NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; # 388 388 389 389 # on Connector T15 390 #NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3390 NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 391 391 # NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only 392 392 # NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only -
firmware/FTM/ftm_definitions.vhd
r10639 r10740 331 331 --X"0010", -- SD_ADDR_general_settings -- general settings 332 332 X"0000", -- SD_ADDR_led -- on-board status LEDs 333 X"03 FF", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency333 X"03E8", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency 334 334 --X"0001", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency 335 X"0000", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers 335 336 --X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers 336 X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers337 337 X"0004", -- SD_ADDR_lp1_amplitude -- light pulser 1 amplitude 338 338 X"0005", -- SD_ADDR_lp2_amplitude -- light pulser 2 amplitude … … 344 344 X"0000", -- SD_ADDR_timemarker_delay -- timemarker delay 345 345 X"0017", -- SD_ADDR_dead_time -- dead time, 8ns + 4x23ns = 100ns 346 --X"0000", -- SD_ADDR_dead_time -- dead time, 8ns + 4x25ns = 108ns347 346 X"0003", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16 348 347 X"8000", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0 -
firmware/FTM/ftu_control/FTM_ftu_control.vhd
r10418 r10740 219 219 signal frame_cnt : integer range 0 to (FTU_RS485_BLOCK_WIDTH / 8) := 0; 220 220 signal FTU_list_reg_cnt : integer range 0 to NO_OF_FTU_LIST_REG := 0; 221 signal FTU_list_header_cnt : integer range 0 to FTU_LIST_RAM_OFFSET:= 0;221 signal FTU_list_header_cnt : integer range 0 to (FTU_LIST_RAM_OFFSET + 1):= 0; 222 222 signal DD_RAM_reg_cnt : integer range 0 to NO_OF_DD_RAM_REG := 0; 223 223 … … 442 442 reset_crc_from_FSM_sig <= '0'; 443 443 enable_crc_from_FSM_sig <= '0'; 444 new_config_done <= '0';445 ping_all_done <= '0';446 read_rates_done <= '0';444 --new_config_done <= '0'; 445 --ping_all_done <= '0'; 446 --read_rates_done <= '0'; 447 447 if (new_config = '1') then 448 new_config_done <= '0';-- 448 449 new_config_started <= '1'; 449 450 ping_all_started <= '0'; … … 451 452 FTM_ftu_rs485_control_State <= ACTIVE_LIST; 452 453 elsif (new_config = '0' and ping_all = '1') then 454 ping_all_done <= '0';-- 453 455 new_config_started <= '0'; 454 456 ping_all_started <= '1'; … … 457 459 FTM_ftu_rs485_control_State <= PING; 458 460 elsif (new_config = '0' and ping_all = '0' and read_rates = '1') then 461 read_rates_done <= '0';-- 459 462 new_config_started <= '0'; 460 463 ping_all_started <= '0'; … … 836 839 when PING_END => -- add final ping statistics to FTU-list 837 840 if (FTU_list_header_cnt < FTU_LIST_RAM_OFFSET) then 838 FTU_list_header_cnt <= FTU_list_header_cnt + 1;841 --FTU_list_header_cnt <= FTU_list_header_cnt + 1; 839 842 FTM_ftu_rs485_control_State <= PING_END_1; 840 843 else … … 854 857 if (FTUlist_RAM_busy = '0') then 855 858 write_FTUlist_RAM <= '1'; 856 addr_FTUlist_RAM <= conv_std_logic_vector((FTU_list_header_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH); 857 if ((FTU_list_header_cnt - 1) = 0) then 859 --addr_FTUlist_RAM <= conv_std_logic_vector((FTU_list_header_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH); 860 addr_FTUlist_RAM <= conv_std_logic_vector((FTU_list_header_cnt), FTU_LIST_RAM_ADDR_WIDTH); 861 --if ((FTU_list_header_cnt - 1) = 0) then 862 if ((FTU_list_header_cnt) = 0) then 858 863 data_FTUlist_RAM <= conv_std_logic_vector(no_of_FTU_answer_sig, 16); 859 elsif ((FTU_list_header_cnt - 1) < 5) then 860 data_FTUlist_RAM <= conv_std_logic_vector(FTU_answer_array_sig(FTU_list_header_cnt - 2), 16); 861 elsif ((FTU_list_header_cnt - 1) < 9) then 862 data_FTUlist_RAM <= active_FTU_array_sig(FTU_list_header_cnt - 6); 864 --elsif ((FTU_list_header_cnt - 1) < 5) then 865 elsif ((FTU_list_header_cnt) < 5) then 866 --data_FTUlist_RAM <= conv_std_logic_vector(FTU_answer_array_sig(FTU_list_header_cnt - 2), 16); 867 data_FTUlist_RAM <= conv_std_logic_vector(FTU_answer_array_sig(FTU_list_header_cnt - 1), 16); 868 --elsif ((FTU_list_header_cnt - 1) < 9) then 869 elsif ((FTU_list_header_cnt) < 9) then 870 --data_FTUlist_RAM <= active_FTU_array_sig(FTU_list_header_cnt - 6); 871 --data_FTUlist_RAM <= conv_std_logic_vector(FTU_list_header_cnt - 6, 16); 872 data_FTUlist_RAM <= active_FTU_array_sig(FTU_list_header_cnt - 5); 863 873 end if; 864 874 FTM_ftu_rs485_control_State <= PING_END_2; … … 873 883 when PING_END_3 => 874 884 if (FTUlist_RAM_ready = '1') then 885 FTU_list_header_cnt <= FTU_list_header_cnt + 1; 875 886 FTM_ftu_rs485_control_State <= PING_END; 876 887 end if;
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