- Timestamp:
- 05/18/11 13:59:12 (13 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd
r10639 r10740 45 45 clk : IN STD_LOGIC; -- 50 MHz system clock 46 46 47 48 47 -- Clock conditioner LMK03000 49 48 ------------------------------------------------------------------------------- … … 55 54 LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect 56 55 57 58 56 -- Time Marker 59 57 ------------------------------------------------------------------------------- … … 65 63 -- operation / physics run 66 64 67 68 65 -- FPGA intern clock conditioner configuration data 69 66 ------------------------------------------------------------------------------- … … 77 74 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0'); 78 75 79 80 76 -- FPGA intern control signals 81 77 ------------------------------------------------------------------------------- … … 97 93 -- 0 = time marker from FPGA for normal 98 94 -- operation / physics run 99 95 100 96 ); 101 97 end Clock_cond_interface; … … 103 99 104 100 architecture Behavioral of Clock_cond_interface is 105 106 101 107 102 component microwire_interface IS 108 103 PORT( 109 104 clk : IN std_logic; 110 clk_uwire : OUT std_logic; --- IN or OUT ?105 clk_uwire : OUT std_logic; 111 106 data_uwire : OUT std_logic; 112 107 le_uwire : OUT std_logic; … … 118 113 end component; 119 114 120 121 signal clk_50M_sig : STD_LOGIC; -- system clock 122 --signal start_config_sig : STD_LOGIC; 123 115 signal clk_50M_sig : STD_LOGIC; -- system clock (50MHz) 116 signal clk_uwire_sig : STD_LOGIC; -- 2 MHz 117 124 118 signal config_ready_sig : STD_LOGIC; 125 signal clk_uwire_sig : STD_LOGIC;126 127 119 signal config_started_sig : STD_LOGIC; 128 120 … … 151 143 signal tim_sel_state : TIM_SEL_STATE_TYPE := IDLE; 152 144 145 signal load_detect_sr : std_logic_vector (1 downto 0) := "00"; 153 146 154 147 begin … … 162 155 clk_cond_array => clk_cond_array_sig, 163 156 config_start => start_config, 164 165 -- config_start => start_config_sig,166 -- config_start <= start_config_sig,167 168 157 config_ready => config_ready_sig, 169 158 config_started => config_started_sig 170 159 ); 171 160 172 173 161 sync_ld_proc : process (clk_uwire_sig) 162 begin 163 if rising_edge(clk_uwire_sig) then 164 load_detect_sr <= load_detect_sr(0) & LD_Clk_Cond; 165 end if; 166 end process sync_ld_proc; 167 174 168 --config_done <= config_ready_sig; -- indicates that the configuration 175 169 -- has been loaded 176 170 177 178 179 config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration 171 --config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration 180 172 -- has been loaded and 181 -- the PLL is locked again 182 183 184 185 --TIM_Sel <= timemarker_select; 186 173 -- the PLL has locked 174 175 config_done <= config_ready_sig and (load_detect_sr(1) and load_detect_sr(0)); 176 187 177 TIM_Sel <= timemarker_select_sig; 188 178 189 179 tim_sel_proc : process (clk_uwire_sig) 190 180 begin … … 205 195 end process tim_sel_proc; 206 196 207 208 197 CLK_Clk_Cond <= clk_uwire_sig; 209 198 210 199 clk_50M_sig <= clk; 211 200 212 -- start_config_sig <= start_config;213 -- start_config <= start_config_sig;214 201 config_started <= config_started_sig; 215 202
Note:
See TracChangeset
for help on using the changeset viewer.
