Changeset 10639 for firmware/FTM/ethernet
- Timestamp:
- 05/10/11 08:52:40 (14 years ago)
- File:
-
- 1 edited
-
firmware/FTM/ethernet/w5300_modul.vhd (modified) (16 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FTM/ethernet/w5300_modul.vhd
r10441 r10639 18 18 -- 19 19 ---------------------------------------------------------------------------------- 20 -- hds interface_start 20 21 21 LIBRARY IEEE; 22 22 USE IEEE.STD_LOGIC_1164.all; … … 117 117 type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, 118 118 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 119 SI, SI 1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR,119 SI, SI0, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR, 120 120 READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL); 121 121 type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, 122 WR_WRITE_START_DEL, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_ FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01, WR_WRITE_END_DEL);122 WR_WRITE_START_DEL, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_SD_ADDR, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01, WR_WRITE_END_DEL); 123 123 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); 124 124 type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); … … 179 179 signal cmd_array : cmd_array_type; 180 180 signal internal_cmd : std_logic := '0'; 181 signal wait_for_data_flag : std_logic := '0'; 181 182 182 183 signal autosend_flag : std_logic := '1'; … … 461 462 par_data <= X"0101"; -- ALIGN, TCP 462 463 state_init <= WRITE_REG; 464 next_state <= SI0; 465 -- keep alive 466 when SI0 => 467 par_addr <= W5300_S0_KPALVTR + socket_cnt * W5300_S_INC; 468 par_data <= X"0C00"; -- 12 * 5s = 60s 469 state_init <= WRITE_REG; 463 470 next_state <= SI1; 464 471 -- Sx Interrupt Mask … … 520 527 ftu_error_send_ready <= '0'; 521 528 led_int <= X"00"; 529 wait_for_data_flag <= '0'; 522 530 -- -- -- 523 531 else … … 560 568 state_init <= READ_DATA; 561 569 busy <= '1'; 562 elsif ( dd_send = '1') then570 elsif ((dd_send = '1') and (wait_for_data_flag = '0')) then 563 571 internal_cmd <= '1'; 564 572 dd_send_ack <= '1'; … … 569 577 state_read_data <= RD_READ_DD_BLOCK; 570 578 state_init <= READ_DATA; 571 elsif ( ftu_error_send = '1') then579 elsif ((ftu_error_send = '1') and (wait_for_data_flag = '0')) then 572 580 ftu_error_send_ack <= '1'; 573 581 ftu_error_send_ready <= '0'; … … 697 705 when PAR_START_X_EVNTS => 698 706 next_state_read_data <= RD_X_EVNTS; 707 wait_for_data_flag <= '1'; 699 708 state_read_data <= RD_5; 700 709 when others => … … 721 730 -- write to address in static data block 722 731 when PAR_WRITE_SD_ADDR => 723 new_config_flag <= '1';732 wait_for_data_flag <= '1'; 724 733 next_state_read_data <= RD_WRITE_SD_ADDR; 725 734 state_read_data <= RD_5; 726 735 -- write static data block 727 736 when PAR_WRITE_SD => 728 new_config_flag <= '1';737 wait_for_data_flag <= '1'; 729 738 next_state_read_data <= RD_WRITE_SD_BLOCK; 730 739 state_read_data <= RD_5; … … 737 746 -- read from address in static data block 738 747 when PAR_READ_SD_ADDR => 748 wait_for_data_flag <= '1'; 739 749 next_state_read_data <= RD_READ_SD_ADDR; 740 750 state_read_data <= RD_5; … … 865 875 local_write_length <= '0' & X"0001"; -- one word will be written to ethernet 866 876 next_state_read_data <= RD_CMD; 877 wait_for_data_flag <= '0'; 867 878 next_state <= READ_DATA; 868 879 state_init <= WRITE_DATA; … … 879 890 if (next_packet_data_cnt = (SD_BLOCK_SIZE - 1)) then 880 891 next_packet_data_cnt <= 0; 892 wait_for_data_flag <= '0'; 893 new_config_flag <= '1'; 881 894 next_state_read_data <= RD_CMD; 882 895 end if; … … 891 904 local_sd_data <= data_read; 892 905 next_packet_data_cnt <= 0; 906 wait_for_data_flag <= '0'; 907 new_config_flag <= '1'; 893 908 next_state_read_data <= RD_CMD; 894 909 next_state <= READ_DATA; … … 907 922 start_run <= '0'; 908 923 next_packet_data_cnt <= 0; 924 wait_for_data_flag <= '0'; 909 925 next_state_read_data <= RD_CMD; 910 926 state_read_data <= RD_5; … … 1106 1122 1107 1123 -- Fill FIFO 1124 -- write header 1108 1125 when WR_FIFO_HEADER => 1109 1126 state_init <= READ_FROM_HEADER_MODUL; … … 1120 1137 state_write <= WR_FIFO_HEADER; 1121 1138 else 1122 state_write <= WR_FIFO_DATA; 1123 end if; 1124 1139 if (data_package_type = FTM_PACKAGE_TYPE_SD_WORD) then 1140 state_write <= WR_SD_ADDR; 1141 else 1142 state_write <= WR_FIFO_DATA; 1143 end if; 1144 end if; 1145 1146 -- write static data ram address (only for single address request) 1147 when WR_SD_ADDR => 1148 write_length_bytes <= write_length_bytes + 2; -- one extra word to write 1149 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 1150 par_data <= "0000" & local_sd_addr; 1151 state_init <= WRITE_REG; 1152 next_state <= WRITE_DATA; 1153 state_write <= WR_FIFO_DATA; 1154 1155 -- write data 1125 1156 when WR_FIFO_DATA => 1126 1157 state_init <= read_addr_state;
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