Changeset 10744 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Timestamp:
- 05/18/11 18:47:32 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 7 edited
-
data_generator.vhd (modified) (2 diffs)
-
fad_board_struct.vhd (modified) (6 diffs)
-
fad_definitions.vhd (modified) (1 diff)
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fad_main_struct.vhd (modified) (9 diffs)
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memory_manager_beha.vhd (modified) (7 diffs)
-
spi_interface_struct.vhd (modified) (2 diffs)
-
w5300_modul.vhd (modified) (5 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10729 r10744 165 165 signal adc_data_sig : adc_data_array_type; 166 166 signal adc_otr_sig : std_logic_vector(3 downto 0) ; 167 type adc_data_16bit_t is array (3 downto 0) of s dt_logic_vector(15 downto 0);167 type adc_data_16bit_t is array (3 downto 0) of std_logic_vector(15 downto 0); 168 168 signal data_16bit : adc_data_16bit_t; 169 169 … … 425 425 if (data_cntr < roi_max_int (channel_id)) then 426 426 data_out <= adc_data_array(3)(7 downto 0) & "000" & adc_otr(3) & adc_data_array(3)(11 downto 8) & 427 428 429 427 adc_data_array(2)(7 downto 0) & "000" & adc_otr(2) & adc_data_array(2)(11 downto 8) & 428 adc_data_array(1)(7 downto 0) & "000" & adc_otr(1) & adc_data_array(1)(11 downto 8) & 429 adc_data_array(0)(7 downto 0) & "000" & adc_otr(0) & adc_data_array(0)(11 downto 8) ; 430 430 431 431 addr_cntr <= addr_cntr + 1; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10729 r10744 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 1 7:58:44 17.05.20115 -- at - 10:24:04 18.05.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 76 76 -- Created: 77 77 -- by - daqct3.UNKNOWN (IHP110) 78 -- at - 1 7:58:44 17.05.201178 -- at - 10:24:05 18.05.2011 79 79 -- 80 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 108 108 SIGNAL debug_data_valid : std_logic; 109 109 SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); 110 SIGNAL mem_manager_state : std_logic_vector(3 DOWNTO 0); -- state is encoded here ... useful for debugging. 110 111 SIGNAL w5300_state : std_logic_vector(7 DOWNTO 0); -- state is encoded here ... useful for debugging. 111 112 … … 154 155 green : OUT std_logic ; 155 156 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 157 mem_manager_state : OUT std_logic_vector (3 DOWNTO 0); -- state is encoded here ... useful for debugging. 156 158 mosi : OUT std_logic := '0'; 157 159 red : OUT std_logic ; … … 209 211 --A1_T(7 downto 0) <= (others => '0'); 210 212 211 A1_T <= counter_result ( 7 downto 0); 213 --A1_T <= counter_result ( 7 downto 0); 214 A1_T(3 downto 0) <= mem_manager_state; 215 A1_T(7 downto 4) <= "1100"; 212 216 --D_T(3 downto 0) <= counter_result ( 11 downto 8); 213 217 --D_T(4) <= alarm_refclk_too_low; … … 274 278 green => RED_LED, 275 279 led => led, 280 mem_manager_state => mem_manager_state, 276 281 mosi => MOSI, 277 282 red => GREEN_LED, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10729 r10744 57 57 --constant SUBVERSION_NUMBER : std_logic_vector (15 downto 0) := conv_std_logic_vector(str_to_int(SUBVERSION_STRING),16); 58 58 constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"01"; 59 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"0 7";59 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"0A"; 60 60 constant PACKAGE_HEADER_LENGTH : integer := 36; 61 61 constant PACKAGE_HEADER_ZEROS : integer := 0; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10729 r10744 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 1 7:58:42 17.05.20115 -- at - 10:24:03 18.05.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 55 55 green : OUT std_logic; 56 56 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 57 mem_manager_state : OUT std_logic_vector (3 DOWNTO 0); -- state is encoded here ... useful for debugging. 57 58 mosi : OUT std_logic := '0'; 58 59 red : OUT std_logic; … … 79 80 -- Created: 80 81 -- by - daqct3.UNKNOWN (IHP110) 81 -- at - 1 7:58:43 17.05.201182 -- at - 10:24:04 18.05.2011 82 83 -- 83 84 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 183 184 SIGNAL socks_connected : std_logic; 184 185 SIGNAL socks_waiting : std_logic; 186 SIGNAL software_trigger_in : std_logic; 185 187 SIGNAL spi_interface_config_start : std_logic := '0'; 186 188 SIGNAL spi_interface_config_valid : std_logic; … … 338 340 runnumber : IN std_logic_vector (31 DOWNTO 0); 339 341 timer_value : IN std_logic_vector (31 DOWNTO 0); -- time in units of 100us 340 trigger : IN std_logic ; 342 hardware_trigger_in : IN std_logic ; 343 software_trigger_in : IN std_logic ; 341 344 adc_data_array : IN adc_data_array_type ; 342 345 adc_output_enable_inverted : OUT std_logic := '1'; … … 410 413 ); 411 414 PORT ( 415 state : OUT std_logic_vector (3 DOWNTO 0); -- state is encoded here ... useful for debugging. 412 416 clk : IN std_logic ; 413 417 config_start : IN std_logic ; … … 610 614 denable <= denable_sig; 611 615 616 -- ModuleWare code(v1.9) for instance 'U_6' of 'gnd' 617 software_trigger_in <= '0'; 618 612 619 -- ModuleWare code(v1.9) for instance 'U_15' of 'gnd' 613 620 reset_synch_i <= '0'; … … 755 762 runnumber => runnumber, 756 763 timer_value => time, 757 trigger => trigger_out, 764 hardware_trigger_in => trigger_out, 765 software_trigger_in => software_trigger_in, 758 766 adc_data_array => adc_data_array_int, 759 767 adc_output_enable_inverted => adc_oeb, … … 822 830 ) 823 831 PORT MAP ( 832 state => mem_manager_state, 824 833 clk => CLK_25, 825 834 config_start => memory_manager_config_start, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd
r10738 r10744 33 33 ); 34 34 PORT( 35 state : OUT std_logic_vector (3 DOWNTO 0); -- state is encoded here ... useful for debugging. 36 35 37 clk : IN std_logic; 36 38 config_start : IN std_logic; … … 112 114 -- no shift register, but local copy. 113 115 signal roi_array_local : roi_array_type; 116 117 118 signal state_sig : std_logic_vector( 3 downto 0 ) := "0000"; 114 119 115 120 BEGIN 116 121 state <= state_sig; 117 122 -- led <= conv_std_logic_vector (events_in_ram, 4) & "00" & wiz_ack & wiz_busy; 118 123 data_ram_empty <= '1' when events_in_ram = 0 else '0'; … … 243 248 244 249 when MM_MAIN => 250 state_sig <= X"1"; 245 251 state_mm <= MM_MAIN1; 246 252 if (config_start_sr = "11") then 247 253 --config_ready <= '0'; 248 if (events_in_ram = 0) then 254 if (events_in_ram = 0) then 249 255 state_mm <= MM_CONFIG; 250 256 end if; … … 252 258 253 259 when MM_MAIN1 => 260 state_sig <= X"2"; 254 261 state_mm <= MM_MAIN2; 255 262 if ((ram_write_ready_sr = "11") and (event_ready_flag = '0')) then … … 269 276 270 277 when MM_MAIN2 => 278 state_sig <= X"3"; 271 279 state_mm <= MM_MAIN3; 272 280 if ((event_ready_flag = '1') and (ram_write_ready_sr = "00")) then … … 282 290 283 291 when MM_MAIN3 => 292 state_sig <= X"4"; 284 293 state_mm <= MM_MAIN4; 285 294 if ((wiz_ack_sr = "11") and (wiz_ack_flag = '0')) then … … 300 309 301 310 when MM_MAIN4 => 311 state_sig <= X"5"; 302 312 state_mm <= MM_MAIN; 303 313 if ((events_in_ram > 0) and (wiz_busy_sr = "00")) then -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd
r10729 r10744 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 10:39:55 17.05.20115 -- at - 08:31:16 18.05.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 39 39 -- Created: 40 40 -- by - daqct3.UNKNOWN (IHP110) 41 -- at - 10:39:56 17.05.201141 -- at - 08:31:16 18.05.2011 42 42 -- 43 43 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10738 r10744 107 107 SI, SI1, SI1b, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, 108 108 109 --CONFIG, WAIT_FOR_OLLI, WAIT_FOR_DATA_RAM_EMPTY,109 CONFIG, WAIT_FOR_OLLI, WAIT_FOR_DATA_RAM_EMPTY, 110 110 CONFIG_MEMORY_MANAGER, WAIT_FOR_CONFIG_MEMORY_MANAGER, 111 111 CONFIG_DATA_GENERATOR, WAIT_FOR_CONFIG_DATA_GENERATOR, … … 694 694 end case; 695 695 696 --when CONFIG => -- Triggers are disabled here!697 --state_sig <= X"06";698 --trigger_enable_storage_sig <= trigger_enable_sig; -- store last value of this signal.699 --trigger_enable_sig <= '0'; --no triggers must occur, while configurating.700 --state_init <= WAIT_FOR_OLLI; -- now wait until the last event was send down..701 --702 --when WAIT_FOR_OLLI => -- This single wait state is not needed, I guess.703 --state_sig <= X"16";704 --state_init <= WAIT_FOR_DATA_RAM_EMPTY; -- should be removed asap, but not now. 28.04.11 DN705 --706 --707 -- when WAIT_FOR_DATA_RAM_EMPTY => 708 --state_sig <= X"17";709 --if (data_ram_empty_sr(1) = '1') then710 --state_init <= CONFIG_MEMORY_MANAGER;711 --end if;696 when CONFIG => -- Triggers are disabled here! 697 state_sig <= X"06"; 698 trigger_enable_storage_sig <= trigger_enable_sig; -- store last value of this signal. 699 trigger_enable_sig <= '0'; --no triggers must occur, while configurating. 700 state_init <= WAIT_FOR_OLLI; -- now wait until the last event was send down.. 701 702 when WAIT_FOR_OLLI => -- This single wait state is not needed, I guess. 703 state_sig <= X"16"; 704 state_init <= WAIT_FOR_DATA_RAM_EMPTY; -- should be removed asap, but not now. 28.04.11 DN 705 706 707 when WAIT_FOR_DATA_RAM_EMPTY => -- GUARANTIED DEAD LOCK HERE, because RAM will never empty, when staying in this state. 708 state_sig <= X"17"; 709 if (data_ram_empty_sr(1) = '1') then 710 state_init <= CONFIG_MEMORY_MANAGER; 711 end if; 712 712 713 713 when CONFIG_MEMORY_MANAGER => … … 768 768 769 769 if (update_of_rois = '1') then 770 if (trigger_enable_sig = '1') then771 trigger_enable_storage_sig <= trigger_enable_sig;772 end if;773 trigger_enable_sig <= '0';774 775 770 update_of_rois <= '0'; 776 state_init <= CONFIG_MEMORY_MANAGER; 771 state_init <= CONFIG; 772 -- if (trigger_enable_sig = '1') then 773 -- trigger_enable_storage_sig <= trigger_enable_sig; 774 -- end if; 775 -- trigger_enable_sig <= '0'; 776 -- 777 -- update_of_rois <= '0'; 778 -- state_init <= CONFIG_MEMORY_MANAGER; 777 779 -- if (data_ram_empty_sr(1) = '1') then 778 780 -- update_of_rois <= '0'; … … 781 783 -- state_init <= MAIN2; 782 784 -- end if; 785 783 786 elsif (update_of_lessimportant = '1') then 784 787 update_of_lessimportant <= '0'; … … 818 821 state_init <= MAIN3; 819 822 else 820 state_init <= MAIN ; -- MAIN1823 state_init <= MAIN1; 821 824 end if; 822 825 when MAIN3 =>
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