Changeset 10883 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Timestamp:
- 05/27/11 17:51:42 (13 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 9 edited
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continous_pulser_beha.vhd (modified) (4 diffs)
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data_generator.vhd (modified) (29 diffs)
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fad_board.ucf (modified) (1 diff)
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fad_board_struct.vhd (modified) (11 diffs)
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fad_definitions.vhd (modified) (4 diffs)
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fad_main_struct.vhd (modified) (27 diffs)
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memory_manager_beha.vhd (modified) (6 diffs)
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transcript (modified) (1 diff)
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w5300_modul.vhd (modified) (39 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/continous_pulser_beha.vhd
r10172 r10883 40 40 signal trigger_loc : std_logic := '0'; 41 41 signal mult_int : integer range 0 to 65535 :=0; 42 signal prescaler: integer range 0 to (MINIMAL_TRIGGER_WAIT_TIME); 43 signal scaler: integer range 0 to 256; 42 44 43 45 BEGIN … … 47 49 48 50 counter : process (CLK) 49 variable Y: integer range 0 to (MINIMAL_TRIGGER_WAIT_TIME) - 1; 50 variable Z: integer range 0 to 256; 51 51 52 begin 52 53 if rising_edge(CLK) then … … 54 55 55 56 56 if ( Y< MINIMAL_TRIGGER_WAIT_TIME - 1) then57 Y := Y+ 1;57 if (prescaler < MINIMAL_TRIGGER_WAIT_TIME - 1) then 58 prescaler <= prescaler + 1; 58 59 else 59 Y := 0;60 if ( Z < mult_int + 1) then61 Z := Z+ 1;60 prescaler <= 0; 61 if ( scaler < mult_int ) then 62 scaler <= scaler + 1; 62 63 else 63 Z := 0;64 scaler <= 0; 64 65 end if; 65 66 end if; 66 67 67 if ( ( Y = 0)and(Z= 0) ) then68 if ( (prescaler = 0)and(scaler = 0) ) then 68 69 trigger_loc <= '1'; 69 70 end if; 70 if ( Y= TRIGGER_WIDTH) then71 if (prescaler = TRIGGER_WIDTH) then 71 72 trigger_loc <= '0'; 72 73 end if; … … 74 75 end process counter; 75 76 76 77 77 78 78 79 79 80 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10744 r10883 25 25 ); 26 26 port( 27 -- for debugging 28 state : out std_logic_vector(7 downto 0); 29 is_idle : out std_logic; 30 27 31 clk : in std_logic; -- CLK_25. 28 32 data_out : out std_logic_vector (63 downto 0); … … 32 36 ram_write_ea : in std_logic; 33 37 ram_write_ready : out std_logic := '0'; 34 ram_write_ready_ack : IN std_logic;35 38 36 39 roi_array : in roi_array_type; … … 132 135 -- this flag is set, when ever a rising edge on 'config_start' is detected. 133 136 -- this flag is cleared only, when a configuration was successfully processed 134 signal config_start_sig : std_logic := '0'; 135 137 138 signal state_sig : std_logic_vector(7 downto 0) := (others => '0'); 136 139 137 140 signal state_generate : state_generate_type := CONFIG; … … 170 173 begin 171 174 drs_readout_started <= sig_drs_readout_started; 175 state <= state_sig; 172 176 generate_data : process (clk) 173 177 begin 174 178 if rising_edge (clk) then 179 is_idle <= '0'; 175 180 -- synch 176 181 config_start_sr <= config_start_sr(0) & config_start; 177 182 178 if (config_start_sr(1) = '1') then 179 config_start_sig <= '1'; 180 config_done <= '0'; 181 end if; 183 182 184 hardware_trigger_sr <= hardware_trigger_sr(0) & hardware_trigger_in; --synching in of asynchrounous trigger signal. 183 185 software_trigger_sr <= software_trigger_sr(0) & software_trigger_in; --synching in of asynchrounous trigger signal. … … 188 190 189 191 when CONFIG => 192 state_sig <= X"01"; 190 193 internal_roi_array <= roi_array; 191 194 package_length_sig <= package_length; … … 195 198 -- all this might be done in the drs_pulser entity 196 199 when CONFIG_DRS_01 => -- BEGIN CONFIG DRS 200 state_sig <= X"02"; 197 201 drs_channel_id <= DRS_WRITE_SHIFT_REG; 198 202 drs_srin_data <= "11111111"; … … 203 207 end if; 204 208 when CONFIG_DRS_02 => 209 state_sig <= X"03"; 205 210 if (drs_srin_write_ready = '1') then 206 211 state_generate <= CONFIG_DRS_03; 207 212 end if; 208 213 when CONFIG_DRS_03 => 214 state_sig <= X"04"; 209 215 drs_channel_id <= DRS_WRITE_CONFIG_REG; 210 216 drs_srin_data <= "11111111"; … … 219 225 -- all other interesting input signals should be sampled here as well! 220 226 when WAIT_FOR_DRS_CONFIG_READY => -- END OF CONFIG 227 state_sig <= X"05"; 221 228 if (drs_srin_write_ready = '1') then 222 229 drs_channel_id <= DRS_ADDR_IDLE; -- to make sure not to write accidentally into DRS shift registers … … 229 236 230 237 when IDLE => 238 is_idle <= '1'; 239 state_sig <= X"10"; 231 240 state_generate <= IDLE; 232 241 trigger_veto <= '0'; 233 if (config_start_sig = '1') then 234 config_start_sig <= '0'; 242 if (config_start_sr(1) = '1') then 235 243 state_generate <= CONFIG; 236 end if; 237 238 if (ram_write_ea = '1' and ( hardware_trigger_sr = "01" or software_trigger_sr = "01") ) then 244 config_done <= '0'; 245 end if; 246 247 248 if (ram_write_ea = '1' and ( hardware_trigger_sr(1) = '1' or software_trigger_sr(1) = '1') ) then 239 249 sig_drs_readout_started <= '1'; -- is set to '0' in next state ... just a pulse. 240 250 runnumber_local_copy <= runnumber; … … 252 262 253 263 when WRITE_HEADER => 264 state_sig <= X"11"; 254 265 sig_drs_readout_started <= '0'; -- is set to '1' in state IDLE 255 266 dataRAM_write_ea_o <= "1"; … … 259 270 denable_enable_in & -- 1 bit 260 271 dwrite_enable_in & -- 1 bit 261 refclk_too_high& -- 1 bit272 '0' & -- 1 bit 262 273 refclk_too_low & -- 1 bit 263 274 DCM_locked_status & -- 1 bit … … 272 283 273 284 when WRITE_FTM_INFO => 285 state_sig <= X"12"; 274 286 -- THIS is just a dummy STATE just to make reading easier. 275 287 -- at this point normally the FTM RS485 data would be written .. but we do not know it … … 279 291 280 292 when WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER => 293 state_sig <= X"13"; 281 294 data_out <= 282 295 "0000" & refclk_counter & … … 288 301 289 302 when WRITE_BOARD_ID => 303 state_sig <= X"14"; 290 304 data_out <= TRG_GEN_div & -- this is a kind of prescaler for the continouus trigger generator 291 305 X"0000" & -- this might be the number of soft triggers beeing generated in a 'burst' not implemented yet … … 296 310 297 311 when WRITE_DNA => 312 state_sig <= X"15"; 298 313 data_out <= 299 314 dna(55 downto 48) & dna(63 downto 56) & … … 305 320 306 321 when WRITE_TIMER => 322 state_sig <= X"16"; 307 323 data_out <= 308 324 runnumber_local_copy(15 downto 0) & -- 2times 16bit reserved for additional status info … … 315 331 -- DANGER: thist state can wait endlessly, if somethings wrong. 316 332 when WRITE_TEMPERATURES => -- temperatures 333 state_sig <= X"17"; 317 334 if (sensor_ready = '1') then 318 335 data_out <= conv_std_logic_vector (sensor_array (3), 16) & … … 325 342 326 343 when WRITE_DAC1 => 344 state_sig <= X"18"; 327 345 data_out <= conv_std_logic_vector (dac_array (3), 16) & 328 346 conv_std_logic_vector (dac_array (2), 16) & … … 332 350 state_generate <= WRITE_DAC2; 333 351 when WRITE_DAC2 => 352 state_sig <= X"19"; 334 353 data_out <= conv_std_logic_vector (dac_array (7), 16) & 335 354 conv_std_logic_vector (dac_array (6), 16) & … … 340 359 341 360 when WAIT_FOR_STOP_CELL => 361 state_sig <= X"1A"; 342 362 start_read_drs_stop_cell <= '0'; 343 363 if (drs_read_s_cell_ready = '1') then … … 368 388 369 389 when WRITE_CHANNEL_ID => -- write DRS and Channel IDs 390 state_sig <= X"1B"; 370 391 data_out <= conv_std_logic_vector(3,12) & conv_std_logic_vector(channel_id,4) & 371 392 conv_std_logic_vector(2,12) & conv_std_logic_vector(channel_id,4) & … … 375 396 state_generate <= WRITE_START_CELL; 376 397 when WRITE_START_CELL => -- write start cells 398 state_sig <= X"1C"; 377 399 data_out <= "000000" & drs_s_cell_array (3) & 378 400 "000000" & drs_s_cell_array (2) & … … 383 405 384 406 when WRITE_ROI => -- write ROI 407 state_sig <= X"1D"; 385 408 data_out <= "00000" & conv_std_logic_vector (internal_roi_array((3) * 9 + channel_id), 11) & 386 409 "00000" & conv_std_logic_vector (internal_roi_array((2) * 9 + channel_id), 11) & … … 391 414 392 415 when WRITE_FILLING => -- write FILLING 416 state_sig <= X"1E"; 393 417 data_out <= conv_std_logic_vector(0,64); -- filling 394 418 addr_cntr <= addr_cntr + 1; … … 396 420 397 421 when WAIT_FOR_ADC => 422 state_sig <= X"1F"; 398 423 -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 399 424 if (adc_wait_cnt < 4 ) then -- anpassen!!!! -- 3 für Simulation, 4 für FPGA??? … … 423 448 424 449 when WRITE_ADC_DATA => 450 state_sig <= X"20"; 425 451 if (data_cntr < roi_max_int (channel_id)) then 426 452 data_out <= adc_data_array(3)(7 downto 0) & "000" & adc_otr(3) & adc_data_array(3)(11 downto 8) & … … 448 474 449 475 when WAIT_FOR_EXTERNAL_TRIGGER_READY => 476 state_sig <= X"21"; 450 477 state_generate <= WAIT_FOR_EXTERNAL_TRIGGER_READY; 451 478 if (FTM_RS485_ready = '1') then … … 457 484 458 485 when WRITE_EXTERNAL_TRIGGER => -- external trigger ID 486 state_sig <= X"22"; 459 487 addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH); 460 488 data_out <= FTM_trigger_info_local_copy(15 downto 0) & … … 465 493 466 494 when WRITE_END_FLAG => 495 state_sig <= X"23"; 467 496 data_out <= conv_std_logic_vector(0, 32) & X"04FE" & X"4242"; 468 497 addr_cntr <= addr_cntr + 1; 469 498 state_generate <= WRITE_DATA_END; 470 499 when WRITE_DATA_END => 500 state_sig <= X"24"; 471 501 dataRAM_write_ea_o <= "0"; 472 502 --information to: memory manager. 473 503 -- one Event was completely written into dataRAM. 474 ram_write_ready <= '1'; 475 state_generate <= WRITE_DATA_END_WAIT; 504 505 -- post writing handshake with MM: 506 -- if 'write_enable' = '1' everything is normal and DG informs MM 507 -- about finished write process by raising 'write_ready' 508 -- if 'write_enable' = '0' 509 -- something strange happened and waiting for 'write_enable' going '1' might cause a dead lock. 510 -- so the reaction is to go back to IDLE state without informing MM. 511 -- this means actually discarding the event. 512 if ( ram_write_ea ='1' ) then 513 ram_write_ready <= '1'; 514 state_generate <= WRITE_DATA_END_WAIT; 515 else 516 state_generate <= WRITE_DATA_STOP; 517 end if; 518 476 519 when WRITE_DATA_END_WAIT => 477 -- check if memory manager received the formaer information. 478 -- go on to next state. 479 if (ram_write_ready_ack = '1') then 520 state_sig <= X"25"; 521 if (ram_write_ea = '0') then 480 522 state_generate <= WRITE_DATA_STOP; 481 523 ram_write_ready <= '0'; 482 524 end if; 483 525 when WRITE_DATA_STOP => 484 if (ram_write_ready_ack = '0') then485 486 487 488 489 490 end if;526 state_sig <= X"26"; 527 drs_readout_ready <= '1'; --info to: trigger manager. 528 data_cntr <= 0; 529 addr_cntr <= 0; 530 channel_id <= 0; 531 state_generate <= WRITE_DATA_STOP1; 532 491 533 when WRITE_DATA_STOP1 => 534 state_sig <= X"27"; 492 535 if (drs_readout_ready_ack = '1') then 493 536 drs_readout_ready <= '0'; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf
r10129 r10883 26 26 NET RS485_C_RE LOC = C6 | IOSTANDARD=LVCMOS33; #ok 27 27 NET RS485_C_DO LOC = C7 | IOSTANDARD=LVCMOS33; #ok 28 NET RS485_C_DI LOC = C8 | IOSTANDARD=LVCMOS33; #ok28 #NET RS485_C_DI LOC = C8 | IOSTANDARD=LVCMOS33; #ok 29 29 30 30 NET RS485_E_DE LOC = D20 | IOSTANDARD=LVCMOS33; #ok -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10744 r10883 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 1 0:24:04 18.05.20115 -- at - 11:58:57 27.05.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 26 26 LINE : IN std_logic_vector ( 5 DOWNTO 0 ); 27 27 REFCLK : IN std_logic; 28 RS485_C_DI : IN std_logic;29 28 RS485_E_DI : IN std_logic; 30 29 TRG : IN STD_LOGIC; … … 76 75 -- Created: 77 76 -- by - daqct3.UNKNOWN (IHP110) 78 -- at - 1 0:24:05 18.05.201177 -- at - 11:58:58 27.05.2011 79 78 -- 80 79 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 98 97 SIGNAL ADC_CLK : std_logic; 99 98 SIGNAL CLK_50 : std_logic; 99 -- for debugging 100 SIGNAL DG_state : std_logic_vector(7 DOWNTO 0); 100 101 SIGNAL SRCLK : std_logic := '0'; 101 102 SIGNAL adc_data_array : adc_data_array_type; … … 109 110 SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); 110 111 SIGNAL mem_manager_state : std_logic_vector(3 DOWNTO 0); -- state is encoded here ... useful for debugging. 112 SIGNAL socket_tx_free_out : std_logic_vector(16 DOWNTO 0); -- 17bit value .. that's true 111 113 SIGNAL w5300_state : std_logic_vector(7 DOWNTO 0); -- state is encoded here ... useful for debugging. 112 114 … … 136 138 CLK_25_PS : OUT std_logic ; 137 139 CLK_50 : OUT std_logic ; 140 -- for debugging 141 DG_state : OUT std_logic_vector (7 DOWNTO 0); 138 142 FTM_RS485_rx_en : OUT std_logic ; 139 143 FTM_RS485_tx_d : OUT std_logic ; … … 160 164 sclk : OUT std_logic ; 161 165 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 166 socket_tx_free_out : OUT std_logic_vector (16 DOWNTO 0); -- 17bit value .. that's true 162 167 trigger_veto : OUT std_logic := '1'; 163 168 w5300_state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging. … … 205 210 D_T <= w5300_state; 206 211 D_T2(0) <= debug_data_valid; 207 D_T2(1) <= debug_data_ram_empty; 212 --D_T2(1) <= debug_data_ram_empty; 213 D_T2(1) <= socket_tx_free_out(16); 208 214 --D_T2 <= ( others => '0' ); 209 215 210 -- A0_T(7 downto 0) <= (others => '0'); 211 --A1_T(7 downto 0) <= (others => '0'); 212 213 --A1_T <= counter_result ( 7 downto 0); 214 A1_T(3 downto 0) <= mem_manager_state; 215 A1_T(7 downto 4) <= "1100"; 216 217 218 219 --A0_T <= DG_state; 220 --A1_T(3 downto 0) <= mem_manager_state; 221 --A1_T(7 downto 4) <= "1100"; 222 223 A0_T <= socket_tx_free_out(7 downto 0); 224 A1_T <= socket_tx_free_out(15 downto 8); 225 216 226 --D_T(3 downto 0) <= counter_result ( 11 downto 8); 217 227 --D_T(4) <= alarm_refclk_too_low; … … 220 230 --D_T(7) <= '0'; 221 231 222 -- led output is driven by w5300 modul 223 -- for debugging only. 224 A0_T <= led; 232 225 233 226 234 -- additional MAX3485 is switched to shutdown mode … … 259 267 CLK_25_PS => OPEN, 260 268 CLK_50 => CLK_50, 269 DG_state => DG_state, 261 270 FTM_RS485_rx_en => RS485_E_RE, 262 271 FTM_RS485_tx_d => RS485_E_DO, … … 283 292 sclk => S_CLK, 284 293 sensor_cs => TCS, 294 socket_tx_free_out => socket_tx_free_out, 285 295 trigger_veto => TRG_V, 286 296 w5300_state => w5300_state, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10744 r10883 57 57 --constant SUBVERSION_NUMBER : std_logic_vector (15 downto 0) := conv_std_logic_vector(str_to_int(SUBVERSION_STRING),16); 58 58 constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"01"; 59 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"0 A";59 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"0B"; 60 60 constant PACKAGE_HEADER_LENGTH : integer := 36; 61 61 constant PACKAGE_HEADER_ZEROS : integer := 0; … … 143 143 144 144 -- Commands 145 constant CMD_WRITE : std_logic_vector := X"0 5";145 constant CMD_WRITE : std_logic_vector := X"02"; -- was 0x05 before 146 146 constant CMD_DENABLE : std_logic_vector := X"06"; 147 147 constant CMD_DDISABLE : std_logic_vector := X"07"; … … 159 159 constant CMD_TRIGGERS_ON : std_logic_vector := X"18"; 160 160 constant CMD_TRIGGERS_OFF : std_logic_vector := X"19"; 161 constant CMD_TRIGGER_S : std_logic_vector := X"20"; 161 162 162 constant CMD_RESET_TRIGGER_ID : std_logic_vector := X"2A"; 163 163 … … 167 167 constant CMD_MODE_ALL_SOCKETS : std_logic_vector := X"31"; 168 168 constant CMD_TRIGGER : std_logic_vector := X"A0"; 169 constant CMD_TRIGGER_C : std_logic_vector := X"B0"; 170 169 constant CMD_TRIGGER_C : std_logic_vector := X"B0"; -- should be 1F in next revision .. T.B. wants it. 170 constant CMD_TRIGGER_S : std_logic_vector := X"20"; 171 171 172 172 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10744 r10883 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 1 0:24:03 18.05.20115 -- at - 11:58:56 27.05.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 36 36 CLK_25_PS : OUT std_logic; 37 37 CLK_50 : OUT std_logic; 38 -- for debugging 39 DG_state : OUT std_logic_vector (7 DOWNTO 0); 38 40 FTM_RS485_rx_en : OUT std_logic; 39 41 FTM_RS485_tx_d : OUT std_logic; … … 60 62 sclk : OUT std_logic; 61 63 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 64 socket_tx_free_out : OUT std_logic_vector (16 DOWNTO 0); -- 17bit value .. that's true 62 65 trigger_veto : OUT std_logic := '1'; 63 66 w5300_state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging. … … 80 83 -- Created: 81 84 -- by - daqct3.UNKNOWN (IHP110) 82 -- at - 1 0:24:04 18.05.201185 -- at - 11:58:57 27.05.2011 83 86 -- 84 87 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 125 128 SIGNAL cont_trigger : std_logic; 126 129 SIGNAL current_dac_array : dac_array_type := ( others => 0); 127 SIGNAL dac_setting : dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd 128 SIGNAL data_generator_config_start : std_logic := '0'; 129 SIGNAL data_generator_config_valid : std_logic; 130 SIGNAL dac_setting : dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd 130 131 SIGNAL data_out : std_logic_vector(63 DOWNTO 0); 131 132 SIGNAL data_ram_empty : std_logic; 132 SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off 133 SIGNAL denable_prim : std_logic := '0'; -- default domino wave off 134 SIGNAL denable_sig : std_logic := '0'; -- default domino wave off 135 SIGNAL din1 : std_logic := '0'; -- default domino wave off 133 SIGNAL data_valid_ack : std_logic := '0'; 134 SIGNAL denable_prim : std_logic := '0'; -- default domino wave off 135 SIGNAL denable_sig : std_logic := '0'; -- default domino wave off 136 SIGNAL dg_config_done : std_logic; 137 SIGNAL dg_start_config : std_logic := '0'; 138 SIGNAL din1 : std_logic := '0'; -- default domino wave off 136 139 SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0'); 137 140 SIGNAL dout : STD_LOGIC; … … 156 159 SIGNAL enable_i : std_logic; 157 160 SIGNAL enabled_trigger_or_s_trigger : std_logic; 161 SIGNAL is_idle : std_logic; 158 162 SIGNAL memory_manager_config_start : std_logic := '0'; 159 163 SIGNAL memory_manager_config_valid : std_logic; 160 164 SIGNAL package_length : std_logic_vector(15 DOWNTO 0); 161 SIGNAL ps_direction : std_logic := '1'; 162 SIGNAL ps_do_phase_shift : std_logic := '0'; 163 SIGNAL ps_reset : std_logic := '0'; 165 SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards 166 SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once 167 SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift 164 168 SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0); 165 169 SIGNAL ram_data : std_logic_vector(15 DOWNTO 0); … … 167 171 SIGNAL ram_write_ea : std_logic; 168 172 SIGNAL ram_write_ready : std_logic := '0'; 169 -- --170 SIGNAL ram_write_ready_ack : std_logic := '0';171 173 SIGNAL ready : STD_LOGIC := '0'; 172 174 SIGNAL rec_timeout_occured : std_logic := '0'; … … 175 177 SIGNAL roi_max : roi_max_type; 176 178 SIGNAL roi_setting : roi_array_type; 177 SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte 178 SIGNAL runnumber : std_logic_vector(31 DOWNTO 0) := conv_std_logic_vector(0 ,31); 179 SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte 180 -- EVT HEADER - part 6 181 SIGNAL runnumber : std_logic_vector(31 DOWNTO 0); 179 182 SIGNAL s_trigger : std_logic; 180 183 SIGNAL s_trigger_or_cont_trigger : std_logic; … … 196 199 SIGNAL trigger_or_s_trigger : std_logic; 197 200 SIGNAL trigger_out : std_logic; 198 SIGNAL wiz_ack : std_logic;199 SIGNAL wiz_busy : std_logic;200 201 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); 201 202 SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); … … 296 297 ); 297 298 PORT ( 299 -- for debugging 300 state : OUT std_logic_vector (7 DOWNTO 0); 301 is_idle : OUT std_logic ; 298 302 clk : IN std_logic ; -- CLK_25. 299 303 data_out : OUT std_logic_vector (63 DOWNTO 0); … … 303 307 ram_write_ea : IN std_logic ; 304 308 ram_write_ready : OUT std_logic := '0'; 305 ram_write_ready_ack : IN std_logic ;306 309 roi_array : IN roi_array_type ; 307 310 roi_max : IN roi_max_type ; … … 407 410 ); 408 411 END COMPONENT; 409 COMPONENT memory_manager 412 COMPONENT memory_manager_2 410 413 GENERIC ( 411 414 RAM_ADDR_WIDTH_64B : integer := 12; … … 413 416 ); 414 417 PORT ( 415 state : OUT std_logic_vector (3 DOWNTO 0); -- state is encoded here ... useful for debugging. 416 clk : IN std_logic ; 417 config_start : IN std_logic ; 418 ram_write_ready : IN std_logic ; 419 -- -- 420 ram_write_ready_ack : OUT std_logic := '0'; 421 -- -- 422 roi_array : IN roi_array_type ; 418 clk : IN std_logic; 419 config_start : IN std_logic; 420 dg_config_done : IN std_logic; 421 ram_write_ready : IN std_logic; 422 roi_array : IN roi_array_type; 423 wiz_read_done : IN std_logic; 424 config_ready : OUT std_logic := '1'; 425 data_ram_empty : OUT std_logic; 426 dg_start_config : OUT std_logic := '0'; 427 package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 428 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0'); 423 429 ram_write_ea : OUT std_logic := '0'; 424 config_ready : OUT std_logic := '1';425 430 roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); 426 package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 431 state : OUT std_logic_vector (3 DOWNTO 0); 432 wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 427 433 wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 DOWNTO 0) := (others => '0'); 428 wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0');429 wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');430 434 wiz_write_ea : OUT std_logic := '0'; 435 wiz_write_end : OUT std_logic := '0'; 431 436 wiz_write_header : OUT std_logic := '0'; 432 wiz_write_end : OUT std_logic := '0'; 433 wiz_busy : IN std_logic ; 434 wiz_ack : IN std_logic ; 435 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0'); 436 data_ram_empty : OUT std_logic 437 wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0') 437 438 ); 438 439 END COMPONENT; … … 494 495 debug_data_ram_empty : OUT std_logic ; 495 496 debug_data_valid : OUT std_logic ; 497 data_generator_idle_i : IN std_logic ; 498 socket_tx_free_out : OUT std_logic_vector (16 DOWNTO 0); -- 17bit value .. that's true 496 499 clk : IN std_logic ; 497 500 wiz_reset : OUT std_logic := '1'; … … 523 526 spi_interface_config_start_o : OUT std_logic := '0'; 524 527 spi_interface_config_valid_i : IN std_logic ; 525 data_generator_config_start_o : OUT std_logic:= '0';526 data_generator_config_valid_i : IN std_logic;528 --data_generator_config_start_o : out std_logic := '0'; 529 --data_generator_config_valid_i : in std_logic; 527 530 dac_setting : OUT dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd 528 531 roi_setting : OUT roi_array_type := DEFAULT_ROI; --<<-- default defined in fad_definitions.vhd 529 runnumber : OUT std_logic_vector (31 DOWNTO 0) := conv_std_logic_vector(0 ,3 1);532 runnumber : OUT std_logic_vector (31 DOWNTO 0) := conv_std_logic_vector(0 ,32); 530 533 reset_trigger_id : OUT std_logic := '0'; 531 534 data_ram_empty : IN std_logic ; … … 578 581 FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser; 579 582 FOR ALL : led_controller USE ENTITY FACT_FAD_lib.led_controller; 580 FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager;583 FOR ALL : memory_manager_2 USE ENTITY FACT_FAD_lib.memory_manager_2; 581 584 FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface; 582 585 FOR ALL : timer USE ENTITY FACT_FAD_lib.timer; … … 621 624 622 625 -- ModuleWare code(v1.9) for instance 'inverter_1' of 'inv' 623 din1 <= NOT( denable_inhibit);626 din1 <= NOT(alarm_refclk_too_low_internal); 624 627 625 628 -- ModuleWare code(v1.9) for instance 'U_2' of 'or' … … 628 631 -- ModuleWare code(v1.9) for instance 'or_1' of 'or' 629 632 s_trigger_or_cont_trigger <= s_trigger OR cont_trigger; 630 631 -- ModuleWare code(v1.9) for instance 'or_2' of 'or'632 denable_inhibit <= alarm_refclk_too_low_internal633 OR alarm_refclk_too_high_internal;634 633 635 634 -- ModuleWare code(v1.9) for instance 'or_5' of 'or' … … 702 701 continous_pulser_instance : continous_pulser 703 702 GENERIC MAP ( 704 MINIMAL_TRIGGER_WAIT_TIME => 25000 0,703 MINIMAL_TRIGGER_WAIT_TIME => 25000, 705 704 TRIGGER_WIDTH => 5 706 705 ) … … 726 725 ) 727 726 PORT MAP ( 727 state => DG_state, 728 is_idle => is_idle, 728 729 clk => CLK_25, 729 730 data_out => data_out, … … 733 734 ram_write_ea => ram_write_ea, 734 735 ram_write_ready => ram_write_ready, 735 ram_write_ready_ack => ram_write_ready_ack,736 736 roi_array => roi_setting, 737 737 roi_max => roi_max, … … 739 739 sensor_ready => sensor_ready, 740 740 dac_array => current_dac_array, 741 config_start => d ata_generator_config_start,742 config_done => d ata_generator_config_valid,741 config_start => dg_start_config, 742 config_done => dg_config_done, 743 743 package_length => package_length, 744 744 pll_lock => plllock_in, … … 824 824 socks_connected => socks_connected 825 825 ); 826 I _main_memory_manager : memory_manager826 Inst_memory_manager_2 : memory_manager_2 827 827 GENERIC MAP ( 828 828 RAM_ADDR_WIDTH_64B => RAMADDRWIDTH64b, … … 833 833 clk => CLK_25, 834 834 config_start => memory_manager_config_start, 835 ram_write_ready => ram_write_ready, 836 ram_write_ready_ack => ram_write_ready_ack, 835 config_ready => memory_manager_config_valid, 837 836 roi_array => roi_setting, 838 ram_write_ea => ram_write_ea,839 config_ready => memory_manager_config_valid,840 837 roi_max => roi_max, 841 838 package_length => package_length, 839 wiz_number_of_channels => wiz_number_of_channels, 840 dg_start_config => dg_start_config, 841 dg_config_done => dg_config_done, 842 ram_write_ready => ram_write_ready, 843 ram_write_ea => ram_write_ea, 844 ram_start_addr => ram_start_addr, 845 wiz_read_done => data_valid_ack, 846 wiz_write_ea => wiz_write_ea, 847 wiz_write_length => wiz_write_length, 842 848 wiz_ram_start_addr => wiz_ram_start_addr, 843 wiz_write_length => wiz_write_length,844 wiz_number_of_channels => wiz_number_of_channels,845 wiz_write_ea => wiz_write_ea,846 849 wiz_write_header => wiz_write_header, 847 850 wiz_write_end => wiz_write_end, 848 wiz_busy => wiz_busy,849 wiz_ack => wiz_ack,850 ram_start_addr => ram_start_addr,851 851 data_ram_empty => data_ram_empty 852 852 ); … … 904 904 debug_data_ram_empty => debug_data_ram_empty, 905 905 debug_data_valid => debug_data_valid, 906 data_generator_idle_i => is_idle, 907 socket_tx_free_out => socket_tx_free_out, 906 908 clk => CLK_50_internal, 907 909 wiz_reset => wiz_reset, … … 918 920 ram_addr => ram_addr, 919 921 data_valid => wiz_write_ea, 920 data_valid_ack => wiz_ack,921 busy => wiz_busy,922 data_valid_ack => data_valid_ack, 923 busy => OPEN, 922 924 write_header_flag => wiz_write_header, 923 925 write_end_flag => wiz_write_end, … … 930 932 spi_interface_config_start_o => spi_interface_config_start, 931 933 spi_interface_config_valid_i => spi_interface_config_valid, 932 data_generator_config_start_o => data_generator_config_start,933 data_generator_config_valid_i => data_generator_config_valid,934 934 dac_setting => dac_setting, 935 935 roi_setting => roi_setting, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd
r10744 r10883 137 137 138 138 when MM_CONFIG => 139 state_sig <= X"6"; 139 140 -- this if clause was doubled ... already in MAIN state config_start = '1' was checked... 140 141 -- this is imho not needed and can cause trouble... DN 17.05.11 … … 152 153 -- calculate max ROIs and channel sizes 153 154 when MAX_ROI => 155 state_sig <= X"7"; 154 156 roi_index <= (drs_id * 9) + channel_id; 155 157 state_mm <= MAX_ROI1; 156 158 when MAX_ROI1 => 159 state_sig <= X"8"; 157 160 temp_roi <= roi_array_local (roi_index); 158 161 state_mm <= MAX_ROI2; 159 162 when MAX_ROI2 => 163 state_sig <= X"9"; 160 164 if (channel_id < 9) then 161 165 if ( temp_roi > roi_max_array (channel_id)) then … … 179 183 -- calculate number of channels that fit in FIFO 180 184 when FIFO_CALC => 185 state_sig <= X"A"; 181 186 if (channel_id < 9) then 182 187 if ((fifo_write_length (package_index) + channel_size (channel_id)) <= W5300_TX_FIFO_SIZE) then … … 202 207 203 208 when RAM_CALC => 209 state_sig <= X"B"; 204 210 if (package_index < number_of_packages) then 205 211 if (channel_index < fifo_channels_array (package_index)) then … … 219 225 end if; 220 226 when RAM_CALC1 => 227 state_sig <= X"C"; 221 228 max_events_ram <= max_events_ram + 1; 222 229 if ((max_events_ram * event_size_ram) <= RAM_SIZE_16B) then … … 227 234 end if; 228 235 when RAM_CALC2 => 236 state_sig <= X"D"; 229 237 event_size_ram_64b <= (event_size_ram / 4); 230 238 events_in_ram <= 0; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/transcript
r10225 r10883 10 10 # // AND IS SUBJECT TO LICENSE TERMS. 11 11 # // 12 # OpenFile D:/firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/ data_generator.vhd12 # OpenFile D:/firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10744 r10883 15 15 debug_data_ram_empty : OUT std_logic; 16 16 debug_data_valid : OUT std_logic; 17 data_generator_idle_i : IN std_logic; 18 socket_tx_free_out : out std_logic_vector (16 DOWNTO 0); -- 17bit value .. that's true 17 19 18 20 clk : IN std_logic; … … 49 51 spi_interface_config_valid_i : in std_logic; 50 52 51 data_generator_config_start_o : out std_logic := '0';52 data_generator_config_valid_i : in std_logic;53 --data_generator_config_start_o : out std_logic := '0'; 54 --data_generator_config_valid_i : in std_logic; 53 55 54 56 dac_setting : out dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd 55 57 roi_setting : out roi_array_type := DEFAULT_ROI; --<<-- default defined in fad_definitions.vhd 56 58 57 runnumber : out std_logic_vector (31 DOWNTO 0) := conv_std_logic_vector(0 ,3 1);59 runnumber : out std_logic_vector (31 DOWNTO 0) := conv_std_logic_vector(0 ,32); 58 60 reset_trigger_id : out std_logic := '0'; 59 61 … … 107 109 SI, SI1, SI1b, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, 108 110 109 CONFIG, WAIT_ FOR_OLLI, WAIT_FOR_DATA_RAM_EMPTY,111 CONFIG, WAIT_100NS, WAIT_UNTIL_DG_IDLE, WAIT_FOR_DATA_RAM_EMPTY, -- <-- this is THE deadlock state 110 112 CONFIG_MEMORY_MANAGER, WAIT_FOR_CONFIG_MEMORY_MANAGER, 111 113 CONFIG_DATA_GENERATOR, WAIT_FOR_CONFIG_DATA_GENERATOR, … … 119 121 WR_MOD7_STARTED, WR_WAIT_FOR_MOD7, 120 122 WR_CHECK_FOR_FIFO_SPACE_01, WR_CHECK_FOR_FIFO_SPACE_02, WR_CHECK_FOR_FIFO_SPACE_03, WR_CHECK_FOR_FIFO_SPACE_04, 121 WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, 123 WR_05, WR_05_PREPARE_LENGTH_INFO, WR_05_POSTPREPARE_LENGTH_INFO, 124 WR_05a, WR_05b, WR_06, WR_07, 125 WR_ACK, WR_WAIT_FOR_ACK, 126 WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, 122 127 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3 123 128 ); … … 189 194 signal local_fifo_channels : std_logic_vector (3 downto 0); 190 195 196 signal wait_100ns_sig : std_logic_vector (2 downto 0) := "000"; 197 191 198 signal config_addr : integer range 0 to 44; 192 199 type config_data_type is array (0 to 46) of std_logic_vector(15 downto 0); 193 200 signal config_setting : config_data_type := ( 194 -- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs TESTING ONLY195 -- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs TESTING ONLY196 -- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs TESTING ONLY197 -- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs TESTING ONLY198 199 200 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs 201 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs202 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs 203 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs 201 -- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs = 10 TESTING ONLY 202 -- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs = 10 TESTING ONLY 203 -- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs = 10 TESTING ONLY 204 -- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs = 10 TESTING ONLY 205 206 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs = 1024 207 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs = 1024 208 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs = 1024 209 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs = 1024 210 204 211 X"61A8", X"0000", X"0000", X"0000", X"7080", X"7080", X"7080", X"7080", --<<-- DACs 205 212 X"0000", 206 X" 1234", X"ABCD" -- MSword // LSword213 X"0000", X"0000" -- MSword // LSword 207 214 ); 215 216 208 217 209 218 -- signals used for MAC/IP calculation: … … 231 240 signal memory_manager_config_valid_i_sr : std_logic_vector(1 downto 0) := "00"; 232 241 signal spi_interface_config_valid_i_sr : std_logic_vector(1 downto 0) := "00"; 233 signal data_generator_config_valid_i_sr : std_logic_vector(1 downto 0) := "00";242 --signal data_generator_config_valid_i_sr : std_logic_vector(1 downto 0) := "00"; 234 243 signal data_ram_empty_sr : std_logic_vector(1 downto 0) := (OTHERS => '0'); 235 244 236 245 237 246 signal data_generator_idle_sr : std_logic_vector(2 downto 0) := "000"; 238 247 239 248 -- only for debugging … … 243 252 signal data_generator_run_mode_signal : std_logic := '1'; -- default triggers will be accepted 244 253 -- signals for different socket modes: DN 04.01.11 245 signal socket_nr_counter : integer range 1 to 7 :=1; --used to determine which socket is used for data sending246 254 signal socket_send_mode : std_logic := '0'; -- if 0 data is send via socket 0; if 1 data is send via the other sockets. 247 255 -- signals for Sockek Number calculation … … 252 260 signal mod7_result : std_logic_vector(2 downto 0); 253 261 262 254 263 signal state_sig : std_logic_vector(7 downto 0) := X"FF"; 255 264 265 signal number_of_words_written_to_fifo : std_logic_vector(15 downto 0) := (others => '0'); 266 signal number_of_bytes_written_to_fifo : std_logic_vector(16 downto 0) := (others => '0'); 256 267 257 268 COMPONENT mod7 … … 290 301 -- output config settings as DAC and ROI arrays. 291 302 state <= state_sig; 292 debug_data_ram_empty <= data_ram_empty_sr(1); 293 debug_data_valid <= data_valid_sr(1); 294 303 debug_data_ram_empty <= int_flag; 304 debug_data_valid <= interrupt_ignore; 305 --debug_data_ram_empty <= data_ram_empty_sr(1); 306 --debug_data_valid <= data_valid_sr(1); 295 307 roi_mapping : for i in 0 to 35 generate 296 308 roi_setting(i) <= conv_integer(config_setting(i)) when (conv_integer(config_setting(i)) < 1025) else 1024; … … 305 317 trigger_enable <= trigger_enable_sig; 306 318 319 307 320 w5300_proc : process (clk) 308 321 begin 309 322 if rising_edge (clk) then 323 --socket_tx_free_out <= socket_tx_free; 324 325 310 326 -- synch asynchronous inputs in: 311 327 memory_manager_config_valid_i_sr <= memory_manager_config_valid_i_sr(0) & memory_manager_config_valid_i; 312 328 spi_interface_config_valid_i_sr <= spi_interface_config_valid_i_sr(0) & spi_interface_config_valid_i; 313 data_generator_config_valid_i_sr <= data_generator_config_valid_i_sr(0) & data_generator_config_valid_i; 314 data_ram_empty_sr <= data_ram_empty_sr(0) & data_ram_empty; 329 --data_generator_config_valid_i_sr <= data_generator_config_valid_i_sr(0) & data_generator_config_valid_i; 330 data_ram_empty_sr <= data_ram_empty_sr(0) & data_ram_empty; 331 data_generator_idle_sr <= data_generator_idle_sr( 1 downto 0 ) & data_generator_idle_i; 315 332 316 333 w5300_interrupt_sr <= w5300_interrupt_sr(0) & int; … … 322 339 -- When sockets receive disconnection request. 323 340 324 if (w5300_interrupt_sr = "10") and (interrupt_ignore = '0') then341 if (w5300_interrupt_sr(1) = '0') and (interrupt_ignore = '0') then 325 342 case state_interrupt_1 is 326 343 when IR1_01 => 344 state_sig <= X"FF"; 327 345 int_flag <= '1'; 328 346 busy <= '1'; 329 347 state_interrupt_1 <= IR1_02; --wait one cycle 330 348 when IR1_02 => 349 state_sig <= X"FE"; 331 350 state_interrupt_1 <= IR1_03; 332 351 when IR1_03 => 352 state_sig <= X"FD"; 333 353 state_init <= INTERRUPT; 334 354 socket_cnt <= "000"; … … 340 360 state_interrupt_1 <= IR1_04; --this state is not existing? bad coding habit??? 341 361 when others => 362 state_sig <= X"FC"; 342 363 null; 343 364 end case; … … 350 371 case state_interrupt_2 is 351 372 when IR2_01 => 373 state_sig <= X"FB"; 352 374 par_addr <= W5300_IR; 353 375 state_init <= READ_REG; … … 360 382 -- if an Sx Interrupt was found go to --> IR2_03 and check what happened. 361 383 when IR2_02 => 384 state_sig <= X"FA"; 362 385 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt 363 386 state_interrupt_2 <= IR2_03; … … 373 396 -- check the Interrupt register of the Socket, which caused the Interrupt. 374 397 when IR2_03 => 398 state_sig <= X"F9"; 375 399 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register 376 400 state_init <= READ_REG; … … 379 403 -- before checking what happened, clear the Interrupt register, so we can proceed. 380 404 when IR2_04 => 405 state_sig <= X"F8"; 381 406 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; 382 407 par_data <= data_read; -- clear Interrupts … … 388 413 -- if this was not Socket 7 ... if it was Socket 7, we're done anyway. 389 414 when IR2_05 => 415 state_sig <= X"F7"; 390 416 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; 391 417 par_data <= X"0010"; -- CLOSE … … 401 427 -- we go on and reset, the W5300 and this entire state machine. 402 428 when IR2_06 => 429 state_sig <= X"F6"; 430 state_interrupt_1 <= IR1_01; 431 state_interrupt_2 <= IR2_01; 432 socket_cnt <= "000"; 433 state_init <= RESET; 434 when others => 403 435 state_interrupt_1 <= IR1_01; 404 436 state_interrupt_2 <= IR2_01; … … 674 706 675 707 when ESTABLISH => 708 state_sig <= X"07"; 676 709 socks_waiting <= '1'; 677 710 socks_connected <= '0'; … … 680 713 next_state <= EST1; 681 714 when EST1 => 715 state_sig <= X"08"; 682 716 case data_read (7 downto 0) is 683 717 when X"17" => -- established … … 686 720 busy <= '0'; 687 721 state_init <= MAIN; 722 --state_init <= CONFIG_MEMORY_MANAGER; 688 723 else 689 724 socket_cnt <= socket_cnt + 1; … … 698 733 trigger_enable_storage_sig <= trigger_enable_sig; -- store last value of this signal. 699 734 trigger_enable_sig <= '0'; --no triggers must occur, while configurating. 700 state_init <= WAIT_FOR_OLLI; -- now wait until the last event was send down.. 735 state_init <= WAIT_100NS; 736 737 when WAIT_100NS => 738 state_sig <= X"15"; 739 wait_100ns_sig <= wait_100ns_sig + 1; 740 if (wait_100ns_sig = "100") then 741 wait_100ns_sig <= "000"; 742 state_init <= WAIT_UNTIL_DG_IDLE; 743 end if; 744 745 when WAIT_UNTIL_DG_IDLE => 746 state_sig <= X"16"; 747 if (data_generator_idle_sr = "111") then 748 --state_init <= CONFIG_MEMORY_MANAGER; 749 state_init <= MAIN; 750 end if; 701 751 702 when WAIT_FOR_OLLI => -- This single wait state is not needed, I guess. 703 state_sig <= X"16"; 704 state_init <= WAIT_FOR_DATA_RAM_EMPTY; -- should be removed asap, but not now. 28.04.11 DN 752 753 705 754 706 755 … … 721 770 state_sig <= X"19"; 722 771 memory_manager_config_start_o <= '0'; 723 if (memory_manager_config_valid_i_sr = "11") then 724 state_init <= CONFIG_DATA_GENERATOR; 772 if (memory_manager_config_valid_i_sr(1) = '1') then 773 --state_init <= CONFIG_DATA_GENERATOR; 774 state_init <= MAIN; 725 775 end if; 726 776 727 when CONFIG_DATA_GENERATOR =>728 state_sig <= X"1A";729 data_generator_config_start_o <= '1';730 if (data_generator_config_valid_i_sr = "00") then731 state_init <= WAIT_FOR_CONFIG_DATA_GENERATOR;732 end if;733 when WAIT_FOR_CONFIG_DATA_GENERATOR =>734 state_sig <= X"1B";735 data_generator_config_start_o <= '0';736 if (data_generator_config_valid_i_sr ="11") then737 trigger_enable_sig <= trigger_enable_storage_sig; --restore value of this signal to the value it had before CONFIG738 state_init <= MAIN;739 end if;777 -- when CONFIG_DATA_GENERATOR => 778 -- state_sig <= X"1A"; 779 -- data_generator_config_start_o <= '1'; 780 -- if (data_generator_config_valid_i_sr = "00") then 781 -- state_init <= WAIT_FOR_CONFIG_DATA_GENERATOR; 782 -- end if; 783 -- when WAIT_FOR_CONFIG_DATA_GENERATOR => 784 -- state_sig <= X"1B"; 785 -- data_generator_config_start_o <= '0'; 786 -- if (data_generator_config_valid_i_sr ="11") then 787 -- trigger_enable_sig <= trigger_enable_storage_sig; --restore value of this signal to the value it had before CONFIG 788 -- state_init <= MAIN; 789 -- end if; 740 790 741 791 … … 769 819 if (update_of_rois = '1') then 770 820 update_of_rois <= '0'; 771 state_init <= CONFIG ;821 state_init <= CONFIG_MEMORY_MANAGER; 772 822 -- if (trigger_enable_sig = '1') then 773 823 -- trigger_enable_storage_sig <= trigger_enable_sig; … … 826 876 state_sig <= X"23"; 827 877 -- needed for the check: if there is enough space in W5300 FIFO 828 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2)829 data_valid_ack <= '1';878 write_length_bytes <= (local_write_length (15 downto 0) & '0') ; -- shift left (*2) 879 830 880 next_state <= MAIN; 831 881 state_init <= WRITE_DATA; 882 832 883 833 884 ---------------------------------------------------------------------------------- … … 1016 1067 state_sig <= X"40"; 1017 1068 if (local_write_header_flag = '1') then 1018 1019 1020 1069 ram_addr <= local_ram_start_addr + 6; -- Address of HIGH word of Event ID 1070 state_write <= WR_GET_EVT_ID_WAIT1; 1071 else 1021 1072 state_write <= WR_CHECK_FOR_FIFO_SPACE_01; 1022 1073 end if; … … 1051 1102 when WR_WAIT_FOR_MOD7 => 1052 1103 state_sig <= X"45"; 1104 next_state_tmp <= next_state; 1053 1105 if (mod7_valid = '1') then 1054 1106 if (socket_send_mode = '1') then -- send via all sockets 1055 local_socket_nr <= mod7_result ;1107 local_socket_nr <= mod7_result + 1; 1056 1108 else -- only send via socket 0\ 1057 1109 local_socket_nr <= "000"; 1058 1110 end if; 1059 next_state_tmp <= next_state;1111 1060 1112 data_cnt <= 0; 1061 1113 state_write <= WR_CHECK_FOR_FIFO_SPACE_01; … … 1084 1136 when WR_CHECK_FOR_FIFO_SPACE_04 => 1085 1137 state_sig <= X"49"; 1138 socket_tx_free_out <= socket_tx_free; 1086 1139 -- if (socket_tx_free (16 downto 0) < write_length_bytes) then 1087 1140 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then 1141 1088 1142 state_write <= WR_CHECK_FOR_FIFO_SPACE_01; 1089 1143 else … … 1116 1170 ram_access <= '1'; 1117 1171 state_init <= WRITE_REG; 1172 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; 1118 1173 next_state <= WRITE_DATA; 1119 1174 state_write <= WR_FIFO; … … 1148 1203 state_write <= WR_ADC2; 1149 1204 when WR_ADC2 => 1205 1150 1206 if (data_cnt < data_end) then 1151 1207 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 1152 1208 ram_access <= '1'; 1153 1209 state_init <= WRITE_REG; 1210 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; 1154 1211 next_state <= WRITE_DATA; 1155 1212 data_cnt <= data_cnt + 1; … … 1177 1234 state_write <= WR_ENDFLAG; 1178 1235 else 1179 state_write <= WR_05 ;1236 state_write <= WR_05a; 1180 1237 end if; 1181 1238 end if; … … 1186 1243 -- Write End Package Flag 1187 1244 when WR_ENDFLAG => 1188 state_sig <= X"4 E";1245 state_sig <= X"4F"; 1189 1246 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4); 1190 1247 state_write <= WR_ENDFLAG1; … … 1193 1250 ram_access <= '1'; 1194 1251 state_init <= WRITE_REG; 1252 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; 1195 1253 next_state <= WRITE_DATA; 1196 1254 state_write <= WR_ENDFLAG2; … … 1201 1259 state_init <= WRITE_REG; 1202 1260 next_state <= WRITE_DATA; 1261 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; 1203 1262 state_write <= WR_05a; 1204 1263 … … 1207 1266 -- Wait???? 1208 1267 when WR_05a => 1268 state_sig <= X"4E"; 1209 1269 if (wait_cntr < 10) then -- 3000 works??? 1210 1270 wait_cntr <= wait_cntr + 1; … … 1214 1274 end if; 1215 1275 when WR_05b => 1216 state_write <= WR_05; 1217 1218 --Send FIFO 1276 state_write <= WR_05_PREPARE_LENGTH_INFO; 1277 1278 --Send FIFO 1279 when WR_05_PREPARE_LENGTH_INFO => 1280 --number_of_words_written_to_fifo <= number_of_words_written_to_fifo - 1; 1281 state_init <= WRITE_DATA; 1282 state_write <= WR_05_POSTPREPARE_LENGTH_INFO; 1283 1284 1285 when WR_05_POSTPREPARE_LENGTH_INFO => 1286 number_of_bytes_written_to_fifo <= number_of_words_written_to_fifo(15 downto 0) & '0'; 1287 state_init <= WRITE_DATA; 1288 state_write <= WR_05; 1289 1290 1219 1291 when WR_05 => 1220 1292 ram_access <= '0'; 1293 state_sig <= X"50"; 1221 1294 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC; 1222 1295 par_data <= (0 => write_length_bytes (16), others => '0'); 1296 --par_data <= (0 => number_of_bytes_written_to_fifo(16), others => '0'); 1223 1297 state_init <= WRITE_REG; 1224 1298 state_write <= WR_06; … … 1226 1300 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2"; 1227 1301 par_data <= write_length_bytes (15 downto 0); 1302 --par_data <= number_of_bytes_written_to_fifo(15 downto 0); 1303 1228 1304 state_init <= WRITE_REG; 1229 1305 state_write <= WR_07; 1230 1306 when WR_07 => 1307 number_of_words_written_to_fifo <= (others => '0'); 1308 state_sig <= X"51"; 1231 1309 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC; 1232 1310 par_data <= X"0020"; -- Send 1233 1311 state_init <= WRITE_REG; 1234 state_write <= WR_08; 1312 state_write <= WR_ACK; 1313 when WR_ACK => 1314 data_valid_ack <= '1'; 1315 state_write <= WR_WAIT_FOR_ACK; 1316 when WR_WAIT_FOR_ACK => 1317 state_write <= WR_WAIT_FOR_ACK; 1318 if (data_valid_sr(1) = '0') then 1319 data_valid_ack <= '0'; 1320 state_init <= next_state_tmp; 1321 state_write <= WR_START; 1322 end if; 1323 1324 1235 1325 when others => 1236 state_init <= next_state_tmp;1237 state_write <= WR_START;1238 1326 state_sig <= X"4F"; 1239 1327 end case; … … 1241 1329 1242 1330 when READ_REG => 1243 state_sig <= X"50";1331 --state_sig <= X"50"; 1244 1332 case count is 1245 1333 when "000" => … … 1269 1357 1270 1358 when WRITE_REG => 1271 state_sig <= X"60";1359 --state_sig <= X"60"; 1272 1360 case count is 1273 1361 when "000" =>
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