Changeset 10760
- Timestamp:
- 05/20/11 12:24:51 (13 years ago)
- Location:
- firmware/FTM
- Files:
-
- 3 edited
-
FTM_central_control.vhd (modified) (9 diffs)
-
FTM_top.vhd (modified) (7 diffs)
-
Timing_counters/Timing_counter.vhd (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FTM/FTM_central_control.vhd
r10740 r10760 82 82 trigger_start : out std_logic := '0'; 83 83 trigger_stop : out std_logic := '1'; 84 enable_ID_sending : out std_logic := '0' 84 enable_ID_sending : out std_logic := '0'; 85 reset_timer : out std_logic := '0' 85 86 ); 86 87 end FTM_central_control; … … 99 100 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111"; 100 101 101 type state_central_proc_type is (CP_INIT, CP_INIT_DNA, 102 type state_central_proc_type is (CP_INIT, CP_INIT_DNA, CP_INIT_TIMER, 102 103 CP_RUNNING, CP_RUNNING_01, CP_RUNNING_02, CP_CONFIG_ACK, 103 104 CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01, … … 124 125 current_cc_state <= X"FFFF"; 125 126 --cc_state_test <= X"00"; 126 cc_state_test <= X" 19";127 cc_state_test <= X"01"; 127 128 if (clk_ready = '1') then 128 129 state_central_proc <= CP_INIT_DNA; … … 133 134 cc_state_test <= X"01"; 134 135 if (dna_ready = '1') then 135 state_central_proc <= CP_ CONFIG;136 state_central_proc <= CP_INIT_TIMER; 136 137 dna_start <= '0'; 138 reset_timer <= '1'; -- reset timer after power-up 137 139 else 138 140 dna_start <= '1'; 139 141 state_central_proc <= CP_INIT_DNA; 140 142 end if; 143 144 when CP_INIT_TIMER => 145 current_cc_state <= X"FFFF"; 146 cc_state_test <= X"01"; 147 reset_timer <= '0'; -- finish reset timer after power-up 148 state_central_proc <= CP_CONFIG; 141 149 142 150 when CP_CONFIG_START => … … 236 244 when CP_IDLE => 237 245 current_cc_state <= FTM_STATE_IDLE; 246 reset_timer <= '0'; 238 247 cc_state_test <= X"0D"; 239 248 stop_run_ack <= '1'; … … 262 271 start_run_ack <= '1'; 263 272 if (start_run_param = PAR_START_RUN) then 273 reset_timer <= '1'; 264 274 state_central_proc <= CP_RUNNING; 265 275 end if; … … 267 277 268 278 when CP_RUNNING => 279 reset_timer <= '0'; 269 280 current_cc_state <= FTM_STATE_RUN; 270 281 cc_state_test <= X"0E"; … … 313 324 if (stop_run = '0') then 314 325 stop_run_ack <= '0'; 326 reset_timer <= '1'; 315 327 state_central_proc <= CP_IDLE; 316 328 end if; … … 393 405 period_finished_sig <= '0'; 394 406 elsif rising_edge(clk_scaler) then 395 if (scaler_counts_sig < scaler_period_sig) then407 if (scaler_counts_sig < (scaler_period_sig - 1)) then 396 408 scaler_counts_sig <= scaler_counts_sig + 1; 397 409 period_finished_sig <= '0'; -
firmware/FTM/FTM_top.vhd
r10740 r10760 364 364 signal trigger_ID_sig : std_logic_vector(55 downto 0); -- initialized in trigger manager 365 365 signal trigger_ID_read_sig : std_logic; -- initialized in FTM_fad_broadcast 366 367 signal trigger_active_sig : std_logic; -- initialized in trigger manager 366 368 367 369 signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up … … 403 405 404 406 signal enable_ID_sending_sig : std_logic; 407 signal reset_timer_sig : std_logic; -- initialized in FTM_central_control 405 408 406 409 -- component FTM_clk_gen … … 566 569 trigger_start : out std_logic; 567 570 trigger_stop : out std_logic; 568 enable_ID_sending : out std_logic 571 enable_ID_sending : out std_logic; 572 reset_timer : out std_logic 569 573 ); 570 574 end component; … … 750 754 end component; 751 755 752 component counter_dummy IS 753 PORT( 754 clk : IN std_logic; 755 get_counter : IN std_logic; 756 get_counter_started : OUT std_logic := '0'; 757 get_counter_ready : OUT std_logic := '0'; 758 counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0') 756 -- component counter_dummy IS 757 -- PORT( 758 -- clk : IN std_logic; 759 -- get_counter : IN std_logic; 760 -- get_counter_started : OUT std_logic := '0'; 761 -- get_counter_ready : OUT std_logic := '0'; 762 -- counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0') 763 -- ); 764 -- end component; 765 766 component Timing_counter is 767 port( 768 clk : in STD_LOGIC; -- 50 MHz system clock 769 enable : in STD_LOGIC; -- enable counter 770 reset : in Std_LOGIC; -- reset counter 771 read_counter : in STD_LOGIC; -- read counter 772 reading_started : out STD_LOGIC; 773 reading_valid : out STD_LOGIC; -- counter reading at output ready 774 counter_reading : out std_logic_vector (TC_WIDTH - 1 downto 0) 759 775 ); 760 776 end component; 761 777 778 762 779 begin 763 780 … … 867 884 trig_cnt_copy => trigger_counter_sig, --counter reading 868 885 trig_cnt_copy_valid => trigger_counter_valid_sig, --trigger counter reading is valid 869 trigger_active => open, --phys triggers are enabled/active886 trigger_active => trigger_active_sig, --phys triggers are enabled/active 870 887 config_done => config_trigger_done_sig, 871 888 LP1_pulse => open, --send start signal to light pulser 1 … … 949 966 trigger_start => trigger_start_sig, 950 967 trigger_stop => trigger_stop_sig, 951 enable_ID_sending => enable_ID_sending_sig 968 enable_ID_sending => enable_ID_sending_sig, 969 reset_timer => reset_timer_sig 952 970 ); 953 971 … … 1131 1149 ); 1132 1150 1133 Inst_counter_dummy_ts : counter_dummy 1151 -- Inst_counter_dummy_ts : counter_dummy 1152 -- port map( 1153 -- clk => clk_50M_sig, 1154 -- get_counter => get_ts_counter_sig, 1155 -- get_counter_started => get_ts_counter_started_sig, 1156 -- get_counter_ready => get_ts_counter_ready_sig, 1157 -- counter => timestamp_counter_sig 1158 -- ); 1159 1160 -- Inst_counter_dummy_ot : counter_dummy 1161 -- port map( 1162 -- clk => clk_50M_sig, 1163 -- get_counter => get_ot_counter_sig, 1164 -- get_counter_started => get_ot_counter_started_sig, 1165 -- get_counter_ready => get_ot_counter_ready_sig, 1166 -- counter => on_time_counter_sig 1167 -- ); 1168 1169 Inst_Timing_counter_ts : Timing_counter 1134 1170 port map( 1135 1171 clk => clk_50M_sig, 1136 get_counter => get_ts_counter_sig, 1137 get_counter_started => get_ts_counter_started_sig, 1138 get_counter_ready => get_ts_counter_ready_sig, 1139 counter => timestamp_counter_sig 1140 ); 1141 1142 Inst_counter_dummy_ot : counter_dummy 1172 enable => '1', 1173 reset => reset_timer_sig, 1174 read_counter => get_ts_counter_sig, 1175 reading_started => get_ts_counter_started_sig, 1176 reading_valid => get_ts_counter_ready_sig, 1177 counter_reading => timestamp_counter_sig 1178 ); 1179 1180 Inst_Timing_counter_ot : Timing_counter 1143 1181 port map( 1144 1182 clk => clk_50M_sig, 1145 get_counter => get_ot_counter_sig, 1146 get_counter_started => get_ot_counter_started_sig, 1147 get_counter_ready => get_ot_counter_ready_sig, 1148 counter => on_time_counter_sig 1183 enable => trigger_active_sig, 1184 reset => reset_timer_sig, 1185 read_counter => get_ot_counter_sig, 1186 reading_started => get_ot_counter_started_sig, 1187 reading_valid => get_ot_counter_ready_sig, 1188 counter_reading => on_time_counter_sig 1149 1189 ); 1150 1190 -
firmware/FTM/Timing_counters/Timing_counter.vhd
r10742 r10760 70 70 signal read_counter_state : type_read_counter_state := IDLE; 71 71 72 signal counting : std_logic_vector (TC_WIDTH - 1 downto 0) ;73 signal counter_reading_sig : std_logic_vector (TC_WIDTH - 1 downto 0) ;74 signal precounting : std_logic_vector (PRECOUNT_WIDTH - 1 downto 0) ;72 signal counting : std_logic_vector (TC_WIDTH - 1 downto 0) := (others => '0'); 73 signal counter_reading_sig : std_logic_vector (TC_WIDTH - 1 downto 0) := (others => '0'); 74 signal precounting : std_logic_vector (PRECOUNT_WIDTH - 1 downto 0) := (others => '0'); 75 75 76 76 … … 87 87 if enable = '1' then 88 88 precounting <= precounting + 1; 89 if (precounting = PRECOUNT_DIVIDER) then89 if (precounting = (PRECOUNT_DIVIDER - 1)) then 90 90 counting <= counting + 1; 91 precounting <= (others => '0'); 91 precounting <= (others => '0'); 92 92 end if; 93 93 end if;
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