- Timestamp:
- 05/23/11 08:46:13 (14 years ago)
- Location:
- trunk/FACT++/src
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/FACT++/src/HeadersFAD.cc
r10755 r10766 11 11 void FAD::EventHeader::print(std::ostream &out) const 12 12 { 13 out << hex << "Delimiter:";13 out << "Delimiter: "; 14 14 if (fStartDelimiter==kDelimiterStart) 15 15 out << "ok"; 16 16 else 17 out << fStartDelimiter;18 out << " (Crate=" << dec << (fBoardId>>8) << ", Board=" << (fBoardId&0xff) << ", Version=" << (fVersion>>8) << "." << (fVersion&0xff) << ", DNA=" << fDNA <<")" << endl;17 out << hex << fStartDelimiter; 18 out << " (Crate=" << dec << (fBoardId>>8) << ", Board=" << (fBoardId&0xff) << ", Version=" << (fVersion>>8) << "." << (fVersion&0xff) << ", DNA=" << hex << fDNA <<")" << endl; 19 19 20 20 out << dec; 21 21 out << "PkgLength: " << fPackageLength << endl; 22 22 23 out << "RunNumber: " << dec<<fRunNumber << endl;23 out << "RunNumber: " << fRunNumber << endl; 24 24 out << "Time: " << fTimeStamp/10000. << "s" << endl; 25 out << "EvtCounter: " << dec <<fEventCounter << " of " << fNumTriggersToGenerate << endl;26 out << "Trigger: Type=" << dec <<fTriggerType << " Id=" << fTriggerId << " Crc=0x" << hex << fTriggerCrc << endl;25 out << "EvtCounter: " << fEventCounter << " of " << fNumTriggersToGenerate << endl; 26 out << "Trigger: Type=" << fTriggerType << " Id=" << fTriggerId << " Crc=0x" << hex << fTriggerCrc << endl; 27 27 28 28 out << "RefClock: " << dec << fFreqRefClock << endl; … … 40 40 out << endl; 41 41 42 out << "PLL_LCK=" << hex << fPLLLCK << endl; 43 out << " PLL-Lock: " << hex << PllLock() << endl; 44 out << " Denable: " << HasDenable() << endl; 45 out << " Dwrite: " << HasDwrite() << endl; 46 out << " RefClk too high: " << IsRefClockTooHigh() << endl; 47 out << " RefClk too low: " << IsRefClockTooLow() << endl; 48 out << " DCM locked: " << IsDcmLocked() << endl; 49 out << " DCM ready: " << IsDcmReady() << endl; 50 out << " SPI_SCLK enabled: " << HasSpiSclk() << endl; 42 out << "Status=" << hex << fStatus << endl; 43 // PllLock -> 1111 44 out << " RefClk locked (PLLLCK): " << hex << (int)PLLLCK(); 45 if (IsRefClockTooHigh()) 46 out << " (too high)"; 47 if (IsRefClockTooLow()) 48 out << " (too low)"; 49 out << endl; 50 out << " Domino wave (Denable): " << (HasDenable()?"enabled":"disabled") << endl; 51 out << " DRS sampling (Dwrite): " << (HasDwrite()?"enabled":"disabled") << endl; 52 out << " Dig.clock manager (DCM): " << (IsDcmLocked()?"locked":"unlocked"); 53 out << " / " << (IsDcmReady()?"ready":"not ready") << endl; 54 out << " SPI Serial Clock (SCLK): " << (HasSpiSclk()?"enabled":"disabled") << endl; 51 55 } 52 56 -
trunk/FACT++/src/HeadersFAD.h
r10756 r10766 112 112 uint16_t fPackageLength; 113 113 uint16_t fVersion; 114 uint16_t f PLLLCK;114 uint16_t fStatus; 115 115 // 116 116 uint16_t fTriggerCrc; … … 182 182 : (fTempDrs[i]&0x007fff))>>3)/16.; } 183 183 184 uint8_t P llLock() const { return fPLLLCK>>12; }185 186 bool HasDenable() const { return f PLLLCK&kDenable; }187 bool HasDwrite() const { return f PLLLCK&kDwrite; }188 bool IsRefClockTooHigh() const { return f PLLLCK&kRefClkTooHigh; }189 bool IsRefClockTooLow() const { return f PLLLCK&kRefClkTooLow; }190 bool IsDcmLocked() const { return f PLLLCK&kDcmLocked; }191 bool IsDcmReady() const { return f PLLLCK&kDcmReady; }192 bool HasSpiSclk() const { return f PLLLCK&kSpiSclk; }184 uint8_t PLLLCK() const { return fStatus>>12; } 185 186 bool HasDenable() const { return fStatus&kDenable; } 187 bool HasDwrite() const { return fStatus&kDwrite; } 188 bool IsRefClockTooHigh() const { return fStatus&kRefClkTooHigh; } 189 bool IsRefClockTooLow() const { return fStatus&kRefClkTooLow; } 190 bool IsDcmLocked() const { return fStatus&kDcmLocked; } 191 bool IsDcmReady() const { return fStatus&kDcmReady; } 192 bool HasSpiSclk() const { return fStatus&kSpiSclk; } 193 193 194 194 void clear() { reset(*this); } … … 244 244 245 245 uint32_t fFreqRefClock; 246 uint16_t f PLLLCK;246 uint16_t fStatus; 247 247 uint16_t fAdcClockPhaseShift; 248 248 uint16_t fNumTriggersToGenerate; … … 253 253 fTimeStamp(h.fTimeStamp), 254 254 fFreqRefClock(h.fFreqRefClock), 255 f PLLLCK(h.fPLLLCK),255 fStatus(h.fStatus), 256 256 fAdcClockPhaseShift(h.fAdcClockPhaseShift), 257 257 fNumTriggersToGenerate(h.fNumTriggersToGenerate), … … 261 261 } 262 262 263 uint8_t P llLock() const { return fPLLLCK>>12; }264 265 bool HasDenable() const { return f PLLLCK&EventHeader::kDenable; }266 bool HasDwrite() const { return f PLLLCK&EventHeader::kDwrite; }267 bool IsRefClockTooHigh() const { return f PLLLCK&EventHeader::kRefClkTooHigh; }268 bool IsRefClockTooLow() const { return f PLLLCK&EventHeader::kRefClkTooLow; }269 bool IsDcmLocked() const { return f PLLLCK&EventHeader::kDcmLocked; }270 bool IsDcmReady() const { return f PLLLCK&EventHeader::kDcmReady; }271 bool HasSpiSclk() const { return f PLLLCK&EventHeader::kSpiSclk; }263 uint8_t PLLLCK() const { return fStatus>>12; } 264 265 bool HasDenable() const { return fStatus&EventHeader::kDenable; } 266 bool HasDwrite() const { return fStatus&EventHeader::kDwrite; } 267 bool IsRefClockTooHigh() const { return fStatus&EventHeader::kRefClkTooHigh; } 268 bool IsRefClockTooLow() const { return fStatus&EventHeader::kRefClkTooLow; } 269 bool IsDcmLocked() const { return fStatus&EventHeader::kDcmLocked; } 270 bool IsDcmReady() const { return fStatus&EventHeader::kDcmReady; } 271 bool HasSpiSclk() const { return fStatus&EventHeader::kSpiSclk; } 272 272 273 273 } __attribute__((__packed__));
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